)]}'
{
  "commit": "6e20e161b8981076a44d93504dcfcb22a1452803",
  "tree": "49b5ca2c0a8e7e0c7153745a08b94ff41cfbe7d7",
  "parents": [
    "4461c226ca63dd796d04bfc713f980ba38fd003b"
  ],
  "author": {
    "name": "Diksha Singh",
    "email": "diksha.singh@ittiam.com",
    "time": "Sat Nov 05 20:47:51 2022 +0530"
  },
  "committer": {
    "name": "Yunqing Wang",
    "email": "yunqingwang@google.com",
    "time": "Wed Nov 09 00:52:46 2022 +0000"
  },
  "message": "Improve AVX2 intrinsic of av1_block_error_lp()\n\nThe CL optimizes av1_block_error_lp_avx2() by reducing\nthe occurences of expanding to higher precision while\naccumulation.\n\nEncoder speed-up for RT preset,\n\n                Instruction Count\ncpu   Testset     Reduction(%)\n 7         rtc      0.712\n 7    rtc_derf      0.557\n 8         rtc      0.560\n 8    rtc_derf      0.426\n 9         rtc      0.580\n 9    rtc_derf      0.414\n 9  rtc_screen      0.529\n10         rtc      0.527\n10    rtc_derf      0.395\n10  rtc_screen      0.529\n\nChange-Id: I82b706897dc1c2d611d01714443fd1c2706db09b\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "12dda3ad01009c69a854b26928b158b95b20f829",
      "old_mode": 33188,
      "old_path": "av1/encoder/x86/error_intrin_avx2.c",
      "new_id": "57725d17959d37a72fd0df2351c658b5c7a1f75a",
      "new_mode": 33188,
      "new_path": "av1/encoder/x86/error_intrin_avx2.c"
    }
  ]
}