[CFL] drop skip logic, always write alpha
Results on Subset 1 (Compared to a0f8c145 with CfL)
PSNR | PSNR Cb | PSNR Cr | PSNR HVS | SSIM | MS SSIM | CIEDE 2000
0.0677 | -0.3359 | -0.2115 | 0.0529 | 0.0735 | 0.0495 | -0.0907
Change-Id: Ib61ff862e8cfbdf0c693a4eba5f2712a6e9ab819
Signed-off-by: David Michael Barr <b@rr-dav.id.au>
diff --git a/av1/common/cfl.h b/av1/common/cfl.h
index 0ad09b4..dcc896d 100644
--- a/av1/common/cfl.h
+++ b/av1/common/cfl.h
@@ -42,11 +42,6 @@
// The rate associated with each alpha codeword
int costs[CFL_ALPHABET_SIZE];
-
- // Count the number of TX blocks in a predicted block to know when you are at
- // the last one, so you can check for skips.
- // TODO(any) Is there a better way to do this?
- int num_tx_blk[CFL_PRED_PLANES];
} CFL_CTX;
static const double cfl_alpha_mags[CFL_MAGS_SIZE] = {
diff --git a/av1/decoder/decodemv.c b/av1/decoder/decodemv.c
index dda15a3..10fefa6 100644
--- a/av1/decoder/decodemv.c
+++ b/av1/decoder/decodemv.c
@@ -161,27 +161,21 @@
}
#if CONFIG_CFL
-static int read_cfl_alphas(FRAME_CONTEXT *const ec_ctx, aom_reader *r, int skip,
+static int read_cfl_alphas(FRAME_CONTEXT *const ec_ctx, aom_reader *r,
CFL_SIGN_TYPE signs_out[CFL_PRED_PLANES]) {
- if (skip) {
- signs_out[CFL_PRED_U] = CFL_SIGN_POS;
- signs_out[CFL_PRED_V] = CFL_SIGN_POS;
- return 0;
- } else {
- const int ind = aom_read_symbol(r, ec_ctx->cfl_alpha_cdf, CFL_ALPHABET_SIZE,
- "cfl:alpha");
- // Signs are only coded for nonzero values
- // sign == 0 implies negative alpha
- // sign == 1 implies positive alpha
- signs_out[CFL_PRED_U] = cfl_alpha_codes[ind][CFL_PRED_U]
- ? aom_read_bit(r, "cfl:sign")
- : CFL_SIGN_POS;
- signs_out[CFL_PRED_V] = cfl_alpha_codes[ind][CFL_PRED_V]
- ? aom_read_bit(r, "cfl:sign")
- : CFL_SIGN_POS;
+ const int ind =
+ aom_read_symbol(r, ec_ctx->cfl_alpha_cdf, CFL_ALPHABET_SIZE, "cfl:alpha");
+ // Signs are only coded for nonzero values
+ // sign == 0 implies negative alpha
+ // sign == 1 implies positive alpha
+ signs_out[CFL_PRED_U] = cfl_alpha_codes[ind][CFL_PRED_U]
+ ? aom_read_bit(r, "cfl:sign")
+ : CFL_SIGN_POS;
+ signs_out[CFL_PRED_V] = cfl_alpha_codes[ind][CFL_PRED_V]
+ ? aom_read_bit(r, "cfl:sign")
+ : CFL_SIGN_POS;
- return ind;
- }
+ return ind;
}
#endif
@@ -1158,8 +1152,7 @@
#if CONFIG_CFL
// TODO(ltrudeau) support PALETTE
if (mbmi->uv_mode == DC_PRED) {
- mbmi->cfl_alpha_idx =
- read_cfl_alphas(ec_ctx, r, mbmi->skip, mbmi->cfl_alpha_signs);
+ mbmi->cfl_alpha_idx = read_cfl_alphas(ec_ctx, r, mbmi->cfl_alpha_signs);
}
#endif // CONFIG_CFL
@@ -1654,7 +1647,7 @@
#else
cm->fc,
#endif // CONFIG_EC_ADAPT
- r, mbmi->skip, mbmi->cfl_alpha_signs);
+ r, mbmi->cfl_alpha_signs);
}
#endif // CONFIG_CFL
diff --git a/av1/encoder/bitstream.c b/av1/encoder/bitstream.c
index 016722a..41c925b 100644
--- a/av1/encoder/bitstream.c
+++ b/av1/encoder/bitstream.c
@@ -1813,29 +1813,23 @@
}
#if CONFIG_CFL
-static void write_cfl_alphas(FRAME_CONTEXT *const frame_ctx, int skip, int ind,
+static void write_cfl_alphas(FRAME_CONTEXT *const frame_ctx, int ind,
const CFL_SIGN_TYPE signs[CFL_SIGNS],
aom_writer *w) {
- if (skip) {
- assert(ind == 0);
+ // Check for uninitialized signs
+ if (cfl_alpha_codes[ind][CFL_PRED_U] == 0)
assert(signs[CFL_PRED_U] == CFL_SIGN_POS);
+ if (cfl_alpha_codes[ind][CFL_PRED_V] == 0)
assert(signs[CFL_PRED_V] == CFL_SIGN_POS);
- } else {
- // Check for uninitialized signs
- if (cfl_alpha_codes[ind][CFL_PRED_U] == 0)
- assert(signs[CFL_PRED_U] == CFL_SIGN_POS);
- if (cfl_alpha_codes[ind][CFL_PRED_V] == 0)
- assert(signs[CFL_PRED_V] == CFL_SIGN_POS);
- // Write a symbol representing a combination of alpha Cb and alpha Cr.
- aom_write_symbol(w, ind, frame_ctx->cfl_alpha_cdf, CFL_ALPHABET_SIZE);
+ // Write a symbol representing a combination of alpha Cb and alpha Cr.
+ aom_write_symbol(w, ind, frame_ctx->cfl_alpha_cdf, CFL_ALPHABET_SIZE);
- // Signs are only signaled for nonzero codes.
- if (cfl_alpha_codes[ind][CFL_PRED_U] != 0)
- aom_write_bit(w, signs[CFL_PRED_U]);
- if (cfl_alpha_codes[ind][CFL_PRED_V] != 0)
- aom_write_bit(w, signs[CFL_PRED_V]);
- }
+ // Signs are only signaled for nonzero codes.
+ if (cfl_alpha_codes[ind][CFL_PRED_U] != 0)
+ aom_write_bit(w, signs[CFL_PRED_U]);
+ if (cfl_alpha_codes[ind][CFL_PRED_V] != 0)
+ aom_write_bit(w, signs[CFL_PRED_V]);
}
#endif
@@ -1987,8 +1981,7 @@
#if CONFIG_CFL
if (mbmi->uv_mode == DC_PRED) {
- write_cfl_alphas(ec_ctx, mbmi->skip, mbmi->cfl_alpha_idx,
- mbmi->cfl_alpha_signs, w);
+ write_cfl_alphas(ec_ctx, mbmi->cfl_alpha_idx, mbmi->cfl_alpha_signs, w);
}
#endif
@@ -2390,8 +2383,7 @@
#if CONFIG_CFL
if (mbmi->uv_mode == DC_PRED) {
- write_cfl_alphas(ec_ctx, mbmi->skip, mbmi->cfl_alpha_idx,
- mbmi->cfl_alpha_signs, w);
+ write_cfl_alphas(ec_ctx, mbmi->cfl_alpha_idx, mbmi->cfl_alpha_signs, w);
}
#endif
diff --git a/av1/encoder/encodemb.c b/av1/encoder/encodemb.c
index 8c9168c..6c56a1a 100644
--- a/av1/encoder/encodemb.c
+++ b/av1/encoder/encodemb.c
@@ -1443,53 +1443,9 @@
// Note : *(args->skip) == mbmi->skip
#endif
#if CONFIG_CFL
- MB_MODE_INFO *mbmi = &xd->mi[0]->mbmi;
if (plane == AOM_PLANE_Y && x->cfl_store_y) {
cfl_store(xd->cfl, dst, dst_stride, blk_row, blk_col, tx_size);
}
-
- if (mbmi->uv_mode == DC_PRED) {
- // TODO(ltrudeau) find a cleaner way to detect last transform block
- if (plane == AOM_PLANE_U) {
- xd->cfl->num_tx_blk[CFL_PRED_U] =
- (blk_row == 0 && blk_col == 0) ? 1
- : xd->cfl->num_tx_blk[CFL_PRED_U] + 1;
- }
-
- if (plane == AOM_PLANE_V) {
- xd->cfl->num_tx_blk[CFL_PRED_V] =
- (blk_row == 0 && blk_col == 0) ? 1
- : xd->cfl->num_tx_blk[CFL_PRED_V] + 1;
-
- if (mbmi->skip &&
- xd->cfl->num_tx_blk[CFL_PRED_U] == xd->cfl->num_tx_blk[CFL_PRED_V]) {
- assert(plane_bsize != BLOCK_INVALID);
- const int block_width = block_size_wide[plane_bsize];
- const int block_height = block_size_high[plane_bsize];
-
- // if SKIP is chosen at the block level, and ind != 0, we must change
- // the prediction
- if (mbmi->cfl_alpha_idx != 0) {
- const struct macroblockd_plane *const pd_cb = &xd->plane[AOM_PLANE_U];
- uint8_t *const dst_cb = pd_cb->dst.buf;
- const int dst_stride_cb = pd_cb->dst.stride;
- uint8_t *const dst_cr = pd->dst.buf;
- const int dst_stride_cr = pd->dst.stride;
- for (int j = 0; j < block_height; j++) {
- for (int i = 0; i < block_width; i++) {
- dst_cb[dst_stride_cb * j + i] =
- (uint8_t)(xd->cfl->dc_pred[CFL_PRED_U] + 0.5);
- dst_cr[dst_stride_cr * j + i] =
- (uint8_t)(xd->cfl->dc_pred[CFL_PRED_V] + 0.5);
- }
- }
- mbmi->cfl_alpha_idx = 0;
- mbmi->cfl_alpha_signs[CFL_PRED_U] = CFL_SIGN_POS;
- mbmi->cfl_alpha_signs[CFL_PRED_V] = CFL_SIGN_POS;
- }
- }
- }
- }
#endif
}
