diff --git a/aom_dsp/aom_dsp_rtcd_defs.pl b/aom_dsp/aom_dsp_rtcd_defs.pl
index 187babe..202047d 100755
--- a/aom_dsp/aom_dsp_rtcd_defs.pl
+++ b/aom_dsp/aom_dsp_rtcd_defs.pl
@@ -62,14 +62,9 @@
   }
 }
 
-@pred_names = qw/dc dc_top dc_left dc_128 v h d207e d63e d45e d117 d135 d153/;
-if (aom_config("CONFIG_ALT_INTRA") eq "yes") {
-  push @pred_names, qw/paeth smooth/;
-  if (aom_config("CONFIG_SMOOTH_HV") eq "yes") {
-    push @pred_names, qw/smooth_v smooth_h/;
-  }
-} else {
-  push @pred_names, 'tm';
+@pred_names = qw/dc dc_top dc_left dc_128 v h d207e d63e d45e d117 d135 d153 paeth smooth/;
+if (aom_config("CONFIG_SMOOTH_HV") eq "yes") {
+  push @pred_names, qw/smooth_v smooth_h/;
 }
 
 #
@@ -93,9 +88,6 @@
 specialize qw/aom_d135_predictor_4x4 neon/;
 specialize qw/aom_d153_predictor_4x4 ssse3/;
 specialize qw/aom_v_predictor_4x4 neon msa sse2/;
-if (aom_config("CONFIG_ALT_INTRA") eq "") {
-  specialize qw/aom_tm_predictor_4x4 neon dspr2 msa sse2/;
-}  # CONFIG_ALT_INTRA
 specialize qw/aom_dc_predictor_4x4 dspr2 msa neon sse2/;
 specialize qw/aom_dc_top_predictor_4x4 msa neon sse2/;
 specialize qw/aom_dc_left_predictor_4x4 msa neon sse2/;
@@ -103,9 +95,6 @@
 specialize qw/aom_h_predictor_8x8 neon dspr2 msa sse2/;
 specialize qw/aom_d153_predictor_8x8 ssse3/;
 specialize qw/aom_v_predictor_8x8 neon msa sse2/;
-if (aom_config("CONFIG_ALT_INTRA") eq "") {
-  specialize qw/aom_tm_predictor_8x8 neon dspr2 msa sse2/;
-}  # CONFIG_ALT_INTRA
 specialize qw/aom_dc_predictor_8x8 dspr2 neon msa sse2/;
 specialize qw/aom_dc_top_predictor_8x8 neon msa sse2/;
 specialize qw/aom_dc_left_predictor_8x8 neon msa sse2/;
@@ -113,9 +102,6 @@
 specialize qw/aom_h_predictor_16x16 neon dspr2 msa sse2/;
 specialize qw/aom_d153_predictor_16x16 ssse3/;
 specialize qw/aom_v_predictor_16x16 neon msa sse2/;
-if (aom_config("CONFIG_ALT_INTRA") eq "") {
-  specialize qw/aom_tm_predictor_16x16 neon msa sse2/;
-}  # CONFIG_ALT_INTRA
 specialize qw/aom_dc_predictor_16x16 dspr2 neon msa sse2/;
 specialize qw/aom_dc_top_predictor_16x16 neon msa sse2/;
 specialize qw/aom_dc_left_predictor_16x16 neon msa sse2/;
@@ -123,9 +109,6 @@
 specialize qw/aom_h_predictor_32x32 neon msa sse2/;
 specialize qw/aom_d153_predictor_32x32 ssse3/;
 specialize qw/aom_v_predictor_32x32 neon msa sse2/;
-if (aom_config("CONFIG_ALT_INTRA") eq "") {
-  specialize qw/aom_tm_predictor_32x32 neon msa sse2/;
-}  # CONFIG_ALT_INTRA
 specialize qw/aom_dc_predictor_32x32 msa neon sse2/;
 specialize qw/aom_dc_top_predictor_32x32 msa neon sse2/;
 specialize qw/aom_dc_left_predictor_32x32 msa neon sse2/;
@@ -133,24 +116,12 @@
 
 if (aom_config("CONFIG_HIGHBITDEPTH") eq "yes") {
   specialize qw/aom_highbd_v_predictor_4x4 sse2/;
-  if (aom_config("CONFIG_ALT_INTRA") eq "") {
-    specialize qw/aom_highbd_tm_predictor_4x4 sse2/;
-  }  # CONFIG_ALT_INTRA
   specialize qw/aom_highbd_dc_predictor_4x4 sse2/;
   specialize qw/aom_highbd_v_predictor_8x8 sse2/;
-  if (aom_config("CONFIG_ALT_INTRA") eq "") {
-    specialize qw/aom_highbd_tm_predictor_8x8 sse2/;
-  }  # CONFIG_ALT_INTRA
   specialize qw/aom_highbd_dc_predictor_8x8 sse2/;;
   specialize qw/aom_highbd_v_predictor_16x16 sse2/;
-  if (aom_config("CONFIG_ALT_INTRA") eq "") {
-    specialize qw/aom_highbd_tm_predictor_16x16 sse2/;
-  }  # CONFIG_ALT_INTRA
   specialize qw/aom_highbd_dc_predictor_16x16 sse2/;
   specialize qw/aom_highbd_v_predictor_32x32 sse2/;
-  if (aom_config("CONFIG_ALT_INTRA") eq "") {
-    specialize qw/aom_highbd_tm_predictor_32x32 sse2/;
-  }  # CONFIG_ALT_INTRA
   specialize qw/aom_highbd_dc_predictor_32x32 sse2/;
 }  # CONFIG_HIGHBITDEPTH
 
diff --git a/aom_dsp/arm/intrapred_neon.c b/aom_dsp/arm/intrapred_neon.c
index 2dc5b2e..7d5f640 100644
--- a/aom_dsp/arm/intrapred_neon.c
+++ b/aom_dsp/arm/intrapred_neon.c
@@ -529,229 +529,4 @@
     }
   }
 }
-
-void aom_tm_predictor_4x4_neon(uint8_t *dst, ptrdiff_t stride,
-                               const uint8_t *above, const uint8_t *left) {
-  int i;
-  uint16x8_t q1u16, q3u16;
-  int16x8_t q1s16;
-  uint8x8_t d0u8 = vdup_n_u8(0);
-  uint32x2_t d2u32 = vdup_n_u32(0);
-
-  d0u8 = vld1_dup_u8(above - 1);
-  d2u32 = vld1_lane_u32((const uint32_t *)above, d2u32, 0);
-  q3u16 = vsubl_u8(vreinterpret_u8_u32(d2u32), d0u8);
-  for (i = 0; i < 4; i++, dst += stride) {
-    q1u16 = vdupq_n_u16((uint16_t)left[i]);
-    q1s16 =
-        vaddq_s16(vreinterpretq_s16_u16(q1u16), vreinterpretq_s16_u16(q3u16));
-    d0u8 = vqmovun_s16(q1s16);
-    vst1_lane_u32((uint32_t *)dst, vreinterpret_u32_u8(d0u8), 0);
-  }
-}
-
-void aom_tm_predictor_8x8_neon(uint8_t *dst, ptrdiff_t stride,
-                               const uint8_t *above, const uint8_t *left) {
-  int j;
-  uint16x8_t q0u16, q3u16, q10u16;
-  int16x8_t q0s16;
-  uint16x4_t d20u16;
-  uint8x8_t d0u8, d2u8, d30u8;
-
-  d0u8 = vld1_dup_u8(above - 1);
-  d30u8 = vld1_u8(left);
-  d2u8 = vld1_u8(above);
-  q10u16 = vmovl_u8(d30u8);
-  q3u16 = vsubl_u8(d2u8, d0u8);
-  d20u16 = vget_low_u16(q10u16);
-  for (j = 0; j < 2; j++, d20u16 = vget_high_u16(q10u16)) {
-    q0u16 = vdupq_lane_u16(d20u16, 0);
-    q0s16 =
-        vaddq_s16(vreinterpretq_s16_u16(q3u16), vreinterpretq_s16_u16(q0u16));
-    d0u8 = vqmovun_s16(q0s16);
-    vst1_u64((uint64_t *)dst, vreinterpret_u64_u8(d0u8));
-    dst += stride;
-    q0u16 = vdupq_lane_u16(d20u16, 1);
-    q0s16 =
-        vaddq_s16(vreinterpretq_s16_u16(q3u16), vreinterpretq_s16_u16(q0u16));
-    d0u8 = vqmovun_s16(q0s16);
-    vst1_u64((uint64_t *)dst, vreinterpret_u64_u8(d0u8));
-    dst += stride;
-    q0u16 = vdupq_lane_u16(d20u16, 2);
-    q0s16 =
-        vaddq_s16(vreinterpretq_s16_u16(q3u16), vreinterpretq_s16_u16(q0u16));
-    d0u8 = vqmovun_s16(q0s16);
-    vst1_u64((uint64_t *)dst, vreinterpret_u64_u8(d0u8));
-    dst += stride;
-    q0u16 = vdupq_lane_u16(d20u16, 3);
-    q0s16 =
-        vaddq_s16(vreinterpretq_s16_u16(q3u16), vreinterpretq_s16_u16(q0u16));
-    d0u8 = vqmovun_s16(q0s16);
-    vst1_u64((uint64_t *)dst, vreinterpret_u64_u8(d0u8));
-    dst += stride;
-  }
-}
-
-void aom_tm_predictor_16x16_neon(uint8_t *dst, ptrdiff_t stride,
-                                 const uint8_t *above, const uint8_t *left) {
-  int j, k;
-  uint16x8_t q0u16, q2u16, q3u16, q8u16, q10u16;
-  uint8x16_t q0u8, q1u8;
-  int16x8_t q0s16, q1s16, q8s16, q11s16;
-  uint16x4_t d20u16;
-  uint8x8_t d2u8, d3u8, d18u8, d22u8, d23u8;
-
-  q0u8 = vld1q_dup_u8(above - 1);
-  q1u8 = vld1q_u8(above);
-  q2u16 = vsubl_u8(vget_low_u8(q1u8), vget_low_u8(q0u8));
-  q3u16 = vsubl_u8(vget_high_u8(q1u8), vget_high_u8(q0u8));
-  for (k = 0; k < 2; k++, left += 8) {
-    d18u8 = vld1_u8(left);
-    q10u16 = vmovl_u8(d18u8);
-    d20u16 = vget_low_u16(q10u16);
-    for (j = 0; j < 2; j++, d20u16 = vget_high_u16(q10u16)) {
-      q0u16 = vdupq_lane_u16(d20u16, 0);
-      q8u16 = vdupq_lane_u16(d20u16, 1);
-      q1s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q0u16), vreinterpretq_s16_u16(q2u16));
-      q0s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q0u16), vreinterpretq_s16_u16(q3u16));
-      q11s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q8u16), vreinterpretq_s16_u16(q2u16));
-      q8s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q8u16), vreinterpretq_s16_u16(q3u16));
-      d2u8 = vqmovun_s16(q1s16);
-      d3u8 = vqmovun_s16(q0s16);
-      d22u8 = vqmovun_s16(q11s16);
-      d23u8 = vqmovun_s16(q8s16);
-      vst1_u64((uint64_t *)dst, vreinterpret_u64_u8(d2u8));
-      vst1_u64((uint64_t *)(dst + 8), vreinterpret_u64_u8(d3u8));
-      dst += stride;
-      vst1_u64((uint64_t *)dst, vreinterpret_u64_u8(d22u8));
-      vst1_u64((uint64_t *)(dst + 8), vreinterpret_u64_u8(d23u8));
-      dst += stride;
-
-      q0u16 = vdupq_lane_u16(d20u16, 2);
-      q8u16 = vdupq_lane_u16(d20u16, 3);
-      q1s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q0u16), vreinterpretq_s16_u16(q2u16));
-      q0s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q0u16), vreinterpretq_s16_u16(q3u16));
-      q11s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q8u16), vreinterpretq_s16_u16(q2u16));
-      q8s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q8u16), vreinterpretq_s16_u16(q3u16));
-      d2u8 = vqmovun_s16(q1s16);
-      d3u8 = vqmovun_s16(q0s16);
-      d22u8 = vqmovun_s16(q11s16);
-      d23u8 = vqmovun_s16(q8s16);
-      vst1_u64((uint64_t *)dst, vreinterpret_u64_u8(d2u8));
-      vst1_u64((uint64_t *)(dst + 8), vreinterpret_u64_u8(d3u8));
-      dst += stride;
-      vst1_u64((uint64_t *)dst, vreinterpret_u64_u8(d22u8));
-      vst1_u64((uint64_t *)(dst + 8), vreinterpret_u64_u8(d23u8));
-      dst += stride;
-    }
-  }
-}
-
-void aom_tm_predictor_32x32_neon(uint8_t *dst, ptrdiff_t stride,
-                                 const uint8_t *above, const uint8_t *left) {
-  int j, k;
-  uint16x8_t q0u16, q3u16, q8u16, q9u16, q10u16, q11u16;
-  uint8x16_t q0u8, q1u8, q2u8;
-  int16x8_t q12s16, q13s16, q14s16, q15s16;
-  uint16x4_t d6u16;
-  uint8x8_t d0u8, d1u8, d2u8, d3u8, d26u8;
-
-  q0u8 = vld1q_dup_u8(above - 1);
-  q1u8 = vld1q_u8(above);
-  q2u8 = vld1q_u8(above + 16);
-  q8u16 = vsubl_u8(vget_low_u8(q1u8), vget_low_u8(q0u8));
-  q9u16 = vsubl_u8(vget_high_u8(q1u8), vget_high_u8(q0u8));
-  q10u16 = vsubl_u8(vget_low_u8(q2u8), vget_low_u8(q0u8));
-  q11u16 = vsubl_u8(vget_high_u8(q2u8), vget_high_u8(q0u8));
-  for (k = 0; k < 4; k++, left += 8) {
-    d26u8 = vld1_u8(left);
-    q3u16 = vmovl_u8(d26u8);
-    d6u16 = vget_low_u16(q3u16);
-    for (j = 0; j < 2; j++, d6u16 = vget_high_u16(q3u16)) {
-      q0u16 = vdupq_lane_u16(d6u16, 0);
-      q12s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q0u16), vreinterpretq_s16_u16(q8u16));
-      q13s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q0u16), vreinterpretq_s16_u16(q9u16));
-      q14s16 = vaddq_s16(vreinterpretq_s16_u16(q0u16),
-                         vreinterpretq_s16_u16(q10u16));
-      q15s16 = vaddq_s16(vreinterpretq_s16_u16(q0u16),
-                         vreinterpretq_s16_u16(q11u16));
-      d0u8 = vqmovun_s16(q12s16);
-      d1u8 = vqmovun_s16(q13s16);
-      d2u8 = vqmovun_s16(q14s16);
-      d3u8 = vqmovun_s16(q15s16);
-      q0u8 = vcombine_u8(d0u8, d1u8);
-      q1u8 = vcombine_u8(d2u8, d3u8);
-      vst1q_u64((uint64_t *)dst, vreinterpretq_u64_u8(q0u8));
-      vst1q_u64((uint64_t *)(dst + 16), vreinterpretq_u64_u8(q1u8));
-      dst += stride;
-
-      q0u16 = vdupq_lane_u16(d6u16, 1);
-      q12s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q0u16), vreinterpretq_s16_u16(q8u16));
-      q13s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q0u16), vreinterpretq_s16_u16(q9u16));
-      q14s16 = vaddq_s16(vreinterpretq_s16_u16(q0u16),
-                         vreinterpretq_s16_u16(q10u16));
-      q15s16 = vaddq_s16(vreinterpretq_s16_u16(q0u16),
-                         vreinterpretq_s16_u16(q11u16));
-      d0u8 = vqmovun_s16(q12s16);
-      d1u8 = vqmovun_s16(q13s16);
-      d2u8 = vqmovun_s16(q14s16);
-      d3u8 = vqmovun_s16(q15s16);
-      q0u8 = vcombine_u8(d0u8, d1u8);
-      q1u8 = vcombine_u8(d2u8, d3u8);
-      vst1q_u64((uint64_t *)dst, vreinterpretq_u64_u8(q0u8));
-      vst1q_u64((uint64_t *)(dst + 16), vreinterpretq_u64_u8(q1u8));
-      dst += stride;
-
-      q0u16 = vdupq_lane_u16(d6u16, 2);
-      q12s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q0u16), vreinterpretq_s16_u16(q8u16));
-      q13s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q0u16), vreinterpretq_s16_u16(q9u16));
-      q14s16 = vaddq_s16(vreinterpretq_s16_u16(q0u16),
-                         vreinterpretq_s16_u16(q10u16));
-      q15s16 = vaddq_s16(vreinterpretq_s16_u16(q0u16),
-                         vreinterpretq_s16_u16(q11u16));
-      d0u8 = vqmovun_s16(q12s16);
-      d1u8 = vqmovun_s16(q13s16);
-      d2u8 = vqmovun_s16(q14s16);
-      d3u8 = vqmovun_s16(q15s16);
-      q0u8 = vcombine_u8(d0u8, d1u8);
-      q1u8 = vcombine_u8(d2u8, d3u8);
-      vst1q_u64((uint64_t *)dst, vreinterpretq_u64_u8(q0u8));
-      vst1q_u64((uint64_t *)(dst + 16), vreinterpretq_u64_u8(q1u8));
-      dst += stride;
-
-      q0u16 = vdupq_lane_u16(d6u16, 3);
-      q12s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q0u16), vreinterpretq_s16_u16(q8u16));
-      q13s16 =
-          vaddq_s16(vreinterpretq_s16_u16(q0u16), vreinterpretq_s16_u16(q9u16));
-      q14s16 = vaddq_s16(vreinterpretq_s16_u16(q0u16),
-                         vreinterpretq_s16_u16(q10u16));
-      q15s16 = vaddq_s16(vreinterpretq_s16_u16(q0u16),
-                         vreinterpretq_s16_u16(q11u16));
-      d0u8 = vqmovun_s16(q12s16);
-      d1u8 = vqmovun_s16(q13s16);
-      d2u8 = vqmovun_s16(q14s16);
-      d3u8 = vqmovun_s16(q15s16);
-      q0u8 = vcombine_u8(d0u8, d1u8);
-      q1u8 = vcombine_u8(d2u8, d3u8);
-      vst1q_u64((uint64_t *)dst, vreinterpretq_u64_u8(q0u8));
-      vst1q_u64((uint64_t *)(dst + 16), vreinterpretq_u64_u8(q1u8));
-      dst += stride;
-    }
-  }
-}
 #endif  // !HAVE_NEON_ASM
diff --git a/aom_dsp/arm/intrapred_neon_asm.asm b/aom_dsp/arm/intrapred_neon_asm.asm
index 7d04d35..fba9c1b 100644
--- a/aom_dsp/arm/intrapred_neon_asm.asm
+++ b/aom_dsp/arm/intrapred_neon_asm.asm
@@ -19,10 +19,6 @@
     EXPORT  |aom_h_predictor_8x8_neon|
     EXPORT  |aom_h_predictor_16x16_neon|
     EXPORT  |aom_h_predictor_32x32_neon|
-    EXPORT  |aom_tm_predictor_4x4_neon|
-    EXPORT  |aom_tm_predictor_8x8_neon|
-    EXPORT  |aom_tm_predictor_16x16_neon|
-    EXPORT  |aom_tm_predictor_32x32_neon|
     ARM
     REQUIRE8
     PRESERVE8
@@ -289,345 +285,3 @@
     bgt                 loop_h
     bx                  lr
     ENDP                ; |aom_h_predictor_32x32_neon|
-
-;void aom_tm_predictor_4x4_neon (uint8_t *dst, ptrdiff_t y_stride,
-;                                const uint8_t *above,
-;                                const uint8_t *left)
-; r0  uint8_t *dst
-; r1  ptrdiff_t y_stride
-; r2  const uint8_t *above
-; r3  const uint8_t *left
-
-|aom_tm_predictor_4x4_neon| PROC
-    ; Load ytop_left = above[-1];
-    sub                 r12, r2, #1
-    vld1.u8             {d0[]}, [r12]
-
-    ; Load above 4 pixels
-    vld1.32             {d2[0]}, [r2]
-
-    ; Compute above - ytop_left
-    vsubl.u8            q3, d2, d0
-
-    ; Load left row by row and compute left + (above - ytop_left)
-    ; 1st row and 2nd row
-    vld1.u8             {d2[]}, [r3]!
-    vld1.u8             {d4[]}, [r3]!
-    vmovl.u8            q1, d2
-    vmovl.u8            q2, d4
-    vadd.s16            q1, q1, q3
-    vadd.s16            q2, q2, q3
-    vqmovun.s16         d0, q1
-    vqmovun.s16         d1, q2
-    vst1.32             {d0[0]}, [r0], r1
-    vst1.32             {d1[0]}, [r0], r1
-
-    ; 3rd row and 4th row
-    vld1.u8             {d2[]}, [r3]!
-    vld1.u8             {d4[]}, [r3]
-    vmovl.u8            q1, d2
-    vmovl.u8            q2, d4
-    vadd.s16            q1, q1, q3
-    vadd.s16            q2, q2, q3
-    vqmovun.s16         d0, q1
-    vqmovun.s16         d1, q2
-    vst1.32             {d0[0]}, [r0], r1
-    vst1.32             {d1[0]}, [r0], r1
-    bx                  lr
-    ENDP                ; |aom_tm_predictor_4x4_neon|
-
-;void aom_tm_predictor_8x8_neon (uint8_t *dst, ptrdiff_t y_stride,
-;                                const uint8_t *above,
-;                                const uint8_t *left)
-; r0  uint8_t *dst
-; r1  ptrdiff_t y_stride
-; r2  const uint8_t *above
-; r3  const uint8_t *left
-
-|aom_tm_predictor_8x8_neon| PROC
-    ; Load ytop_left = above[-1];
-    sub                 r12, r2, #1
-    vld1.8              {d0[]}, [r12]
-
-    ; preload 8 left
-    vld1.8              {d30}, [r3]
-
-    ; Load above 8 pixels
-    vld1.64             {d2}, [r2]
-
-    vmovl.u8            q10, d30
-
-    ; Compute above - ytop_left
-    vsubl.u8            q3, d2, d0
-
-    ; Load left row by row and compute left + (above - ytop_left)
-    ; 1st row and 2nd row
-    vdup.16             q0, d20[0]
-    vdup.16             q1, d20[1]
-    vadd.s16            q0, q3, q0
-    vadd.s16            q1, q3, q1
-
-    ; 3rd row and 4th row
-    vdup.16             q8, d20[2]
-    vdup.16             q9, d20[3]
-    vadd.s16            q8, q3, q8
-    vadd.s16            q9, q3, q9
-
-    vqmovun.s16         d0, q0
-    vqmovun.s16         d1, q1
-    vqmovun.s16         d2, q8
-    vqmovun.s16         d3, q9
-
-    vst1.64             {d0}, [r0], r1
-    vst1.64             {d1}, [r0], r1
-    vst1.64             {d2}, [r0], r1
-    vst1.64             {d3}, [r0], r1
-
-    ; 5th row and 6th row
-    vdup.16             q0, d21[0]
-    vdup.16             q1, d21[1]
-    vadd.s16            q0, q3, q0
-    vadd.s16            q1, q3, q1
-
-    ; 7th row and 8th row
-    vdup.16             q8, d21[2]
-    vdup.16             q9, d21[3]
-    vadd.s16            q8, q3, q8
-    vadd.s16            q9, q3, q9
-
-    vqmovun.s16         d0, q0
-    vqmovun.s16         d1, q1
-    vqmovun.s16         d2, q8
-    vqmovun.s16         d3, q9
-
-    vst1.64             {d0}, [r0], r1
-    vst1.64             {d1}, [r0], r1
-    vst1.64             {d2}, [r0], r1
-    vst1.64             {d3}, [r0], r1
-
-    bx                  lr
-    ENDP                ; |aom_tm_predictor_8x8_neon|
-
-;void aom_tm_predictor_16x16_neon (uint8_t *dst, ptrdiff_t y_stride,
-;                                const uint8_t *above,
-;                                const uint8_t *left)
-; r0  uint8_t *dst
-; r1  ptrdiff_t y_stride
-; r2  const uint8_t *above
-; r3  const uint8_t *left
-
-|aom_tm_predictor_16x16_neon| PROC
-    ; Load ytop_left = above[-1];
-    sub                 r12, r2, #1
-    vld1.8              {d0[]}, [r12]
-
-    ; Load above 8 pixels
-    vld1.8              {q1}, [r2]
-
-    ; preload 8 left into r12
-    vld1.8              {d18}, [r3]!
-
-    ; Compute above - ytop_left
-    vsubl.u8            q2, d2, d0
-    vsubl.u8            q3, d3, d0
-
-    vmovl.u8            q10, d18
-
-    ; Load left row by row and compute left + (above - ytop_left)
-    ; Process 8 rows in each single loop and loop 2 times to process 16 rows.
-    mov                 r2, #2
-
-loop_16x16_neon
-    ; Process two rows.
-    vdup.16             q0, d20[0]
-    vdup.16             q8, d20[1]
-    vadd.s16            q1, q0, q2
-    vadd.s16            q0, q0, q3
-    vadd.s16            q11, q8, q2
-    vadd.s16            q8, q8, q3
-    vqmovun.s16         d2, q1
-    vqmovun.s16         d3, q0
-    vqmovun.s16         d22, q11
-    vqmovun.s16         d23, q8
-    vdup.16             q0, d20[2]                  ; proload next 2 rows data
-    vdup.16             q8, d20[3]
-    vst1.64             {d2,d3}, [r0], r1
-    vst1.64             {d22,d23}, [r0], r1
-
-    ; Process two rows.
-    vadd.s16            q1, q0, q2
-    vadd.s16            q0, q0, q3
-    vadd.s16            q11, q8, q2
-    vadd.s16            q8, q8, q3
-    vqmovun.s16         d2, q1
-    vqmovun.s16         d3, q0
-    vqmovun.s16         d22, q11
-    vqmovun.s16         d23, q8
-    vdup.16             q0, d21[0]                  ; proload next 2 rows data
-    vdup.16             q8, d21[1]
-    vst1.64             {d2,d3}, [r0], r1
-    vst1.64             {d22,d23}, [r0], r1
-
-    vadd.s16            q1, q0, q2
-    vadd.s16            q0, q0, q3
-    vadd.s16            q11, q8, q2
-    vadd.s16            q8, q8, q3
-    vqmovun.s16         d2, q1
-    vqmovun.s16         d3, q0
-    vqmovun.s16         d22, q11
-    vqmovun.s16         d23, q8
-    vdup.16             q0, d21[2]                  ; proload next 2 rows data
-    vdup.16             q8, d21[3]
-    vst1.64             {d2,d3}, [r0], r1
-    vst1.64             {d22,d23}, [r0], r1
-
-
-    vadd.s16            q1, q0, q2
-    vadd.s16            q0, q0, q3
-    vadd.s16            q11, q8, q2
-    vadd.s16            q8, q8, q3
-    vqmovun.s16         d2, q1
-    vqmovun.s16         d3, q0
-    vqmovun.s16         d22, q11
-    vqmovun.s16         d23, q8
-    vld1.8              {d18}, [r3]!                  ; preload 8 left into r12
-    vmovl.u8            q10, d18
-    vst1.64             {d2,d3}, [r0], r1
-    vst1.64             {d22,d23}, [r0], r1
-
-    subs                r2, r2, #1
-    bgt                 loop_16x16_neon
-
-    bx                  lr
-    ENDP                ; |aom_tm_predictor_16x16_neon|
-
-;void aom_tm_predictor_32x32_neon (uint8_t *dst, ptrdiff_t y_stride,
-;                                  const uint8_t *above,
-;                                  const uint8_t *left)
-; r0  uint8_t *dst
-; r1  ptrdiff_t y_stride
-; r2  const uint8_t *above
-; r3  const uint8_t *left
-
-|aom_tm_predictor_32x32_neon| PROC
-    ; Load ytop_left = above[-1];
-    sub                 r12, r2, #1
-    vld1.8              {d0[]}, [r12]
-
-    ; Load above 32 pixels
-    vld1.8              {q1}, [r2]!
-    vld1.8              {q2}, [r2]
-
-    ; preload 8 left pixels
-    vld1.8              {d26}, [r3]!
-
-    ; Compute above - ytop_left
-    vsubl.u8            q8, d2, d0
-    vsubl.u8            q9, d3, d0
-    vsubl.u8            q10, d4, d0
-    vsubl.u8            q11, d5, d0
-
-    vmovl.u8            q3, d26
-
-    ; Load left row by row and compute left + (above - ytop_left)
-    ; Process 8 rows in each single loop and loop 4 times to process 32 rows.
-    mov                 r2, #4
-
-loop_32x32_neon
-    ; Process two rows.
-    vdup.16             q0, d6[0]
-    vdup.16             q2, d6[1]
-    vadd.s16            q12, q0, q8
-    vadd.s16            q13, q0, q9
-    vadd.s16            q14, q0, q10
-    vadd.s16            q15, q0, q11
-    vqmovun.s16         d0, q12
-    vqmovun.s16         d1, q13
-    vadd.s16            q12, q2, q8
-    vadd.s16            q13, q2, q9
-    vqmovun.s16         d2, q14
-    vqmovun.s16         d3, q15
-    vadd.s16            q14, q2, q10
-    vadd.s16            q15, q2, q11
-    vst1.64             {d0-d3}, [r0], r1
-    vqmovun.s16         d24, q12
-    vqmovun.s16         d25, q13
-    vqmovun.s16         d26, q14
-    vqmovun.s16         d27, q15
-    vdup.16             q1, d6[2]
-    vdup.16             q2, d6[3]
-    vst1.64             {d24-d27}, [r0], r1
-
-    ; Process two rows.
-    vadd.s16            q12, q1, q8
-    vadd.s16            q13, q1, q9
-    vadd.s16            q14, q1, q10
-    vadd.s16            q15, q1, q11
-    vqmovun.s16         d0, q12
-    vqmovun.s16         d1, q13
-    vadd.s16            q12, q2, q8
-    vadd.s16            q13, q2, q9
-    vqmovun.s16         d2, q14
-    vqmovun.s16         d3, q15
-    vadd.s16            q14, q2, q10
-    vadd.s16            q15, q2, q11
-    vst1.64             {d0-d3}, [r0], r1
-    vqmovun.s16         d24, q12
-    vqmovun.s16         d25, q13
-    vqmovun.s16         d26, q14
-    vqmovun.s16         d27, q15
-    vdup.16             q0, d7[0]
-    vdup.16             q2, d7[1]
-    vst1.64             {d24-d27}, [r0], r1
-
-    ; Process two rows.
-    vadd.s16            q12, q0, q8
-    vadd.s16            q13, q0, q9
-    vadd.s16            q14, q0, q10
-    vadd.s16            q15, q0, q11
-    vqmovun.s16         d0, q12
-    vqmovun.s16         d1, q13
-    vadd.s16            q12, q2, q8
-    vadd.s16            q13, q2, q9
-    vqmovun.s16         d2, q14
-    vqmovun.s16         d3, q15
-    vadd.s16            q14, q2, q10
-    vadd.s16            q15, q2, q11
-    vst1.64             {d0-d3}, [r0], r1
-    vqmovun.s16         d24, q12
-    vqmovun.s16         d25, q13
-    vqmovun.s16         d26, q14
-    vqmovun.s16         d27, q15
-    vdup.16             q0, d7[2]
-    vdup.16             q2, d7[3]
-    vst1.64             {d24-d27}, [r0], r1
-
-    ; Process two rows.
-    vadd.s16            q12, q0, q8
-    vadd.s16            q13, q0, q9
-    vadd.s16            q14, q0, q10
-    vadd.s16            q15, q0, q11
-    vqmovun.s16         d0, q12
-    vqmovun.s16         d1, q13
-    vadd.s16            q12, q2, q8
-    vadd.s16            q13, q2, q9
-    vqmovun.s16         d2, q14
-    vqmovun.s16         d3, q15
-    vadd.s16            q14, q2, q10
-    vadd.s16            q15, q2, q11
-    vst1.64             {d0-d3}, [r0], r1
-    vqmovun.s16         d24, q12
-    vqmovun.s16         d25, q13
-    vld1.8              {d0}, [r3]!                   ; preload 8 left pixels
-    vqmovun.s16         d26, q14
-    vqmovun.s16         d27, q15
-    vmovl.u8            q3, d0
-    vst1.64             {d24-d27}, [r0], r1
-
-    subs                r2, r2, #1
-    bgt                 loop_32x32_neon
-
-    bx                  lr
-    ENDP                ; |aom_tm_predictor_32x32_neon|
-
-    END
diff --git a/aom_dsp/intrapred.c b/aom_dsp/intrapred.c
index b4d47ae..96f02e5 100644
--- a/aom_dsp/intrapred.c
+++ b/aom_dsp/intrapred.c
@@ -179,7 +179,6 @@
   }
 }
 
-#if CONFIG_ALT_INTRA
 static INLINE int abs_diff(int a, int b) { return (a > b) ? a - b : b - a; }
 
 static INLINE uint16_t paeth_predictor_single(uint16_t left, uint16_t top,
@@ -344,21 +343,6 @@
 }
 #endif  // CONFIG_SMOOTH_HV
 
-#else
-
-static INLINE void tm_predictor(uint8_t *dst, ptrdiff_t stride, int bw, int bh,
-                                const uint8_t *above, const uint8_t *left) {
-  int r, c;
-  int ytop_left = above[-1];
-
-  for (r = 0; r < bh; r++) {
-    for (c = 0; c < bw; c++)
-      dst[c] = clip_pixel(left[r] + above[c] - ytop_left);
-    dst += stride;
-  }
-}
-#endif  // CONFIG_ALT_INTRA
-
 static INLINE void dc_128_predictor(uint8_t *dst, ptrdiff_t stride, int bw,
                                     int bh, const uint8_t *above,
                                     const uint8_t *left) {
@@ -794,7 +778,6 @@
   DST(1, 1) = AVG3(J, I, X);
 }
 
-#if CONFIG_ALT_INTRA
 static INLINE void highbd_paeth_predictor(uint16_t *dst, ptrdiff_t stride,
                                           int bw, int bh, const uint16_t *above,
                                           const uint16_t *left, int bd) {
@@ -901,23 +884,7 @@
     dst += stride;
   }
 }
-#endif
-
-#else
-static INLINE void highbd_tm_predictor(uint16_t *dst, ptrdiff_t stride, int bw,
-                                       int bh, const uint16_t *above,
-                                       const uint16_t *left, int bd) {
-  int r, c;
-  int ytop_left = above[-1];
-  (void)bd;
-
-  for (r = 0; r < bh; r++) {
-    for (c = 0; c < bw; c++)
-      dst[c] = clip_pixel_highbd(left[r] + above[c] - ytop_left, bd);
-    dst += stride;
-  }
-}
-#endif  // CONFIG_ALT_INTRA
+#endif  // CONFIG_SMOOTH_HV
 
 static INLINE void highbd_dc_128_predictor(uint16_t *dst, ptrdiff_t stride,
                                            int bw, int bh,
@@ -1118,16 +1085,12 @@
 intra_pred_above_4x4(d153)
 intra_pred_allsizes(v)
 intra_pred_allsizes(h)
-#if CONFIG_ALT_INTRA
 intra_pred_allsizes(smooth)
 #if CONFIG_SMOOTH_HV
 intra_pred_allsizes(smooth_v)
 intra_pred_allsizes(smooth_h)
 #endif  // CONFIG_SMOOTH_HV
 intra_pred_allsizes(paeth)
-#else
-intra_pred_allsizes(tm)
-#endif  // CONFIG_ALT_INTRA
 intra_pred_allsizes(dc_128)
 intra_pred_allsizes(dc_left)
 intra_pred_allsizes(dc_top)
diff --git a/aom_dsp/mips/intrapred4_dspr2.c b/aom_dsp/mips/intrapred4_dspr2.c
index ea7c028..44652dc 100644
--- a/aom_dsp/mips/intrapred4_dspr2.c
+++ b/aom_dsp/mips/intrapred4_dspr2.c
@@ -78,148 +78,4 @@
       : [above] "r"(above), [left] "r"(left), [dst] "r"(dst),
         [stride] "r"(stride));
 }
-
-void aom_tm_predictor_4x4_dspr2(uint8_t *dst, ptrdiff_t stride,
-                                const uint8_t *above, const uint8_t *left) {
-  int32_t abovel, abover;
-  int32_t left0, left1, left2, left3;
-  int32_t res0, res1;
-  int32_t resl;
-  int32_t resr;
-  int32_t top_left;
-  uint8_t *cm = aom_ff_cropTbl;
-
-  __asm__ __volatile__(
-      "ulw             %[resl],       (%[above])                         \n\t"
-
-      "lbu             %[left0],       (%[left])                         \n\t"
-      "lbu             %[left1],       1(%[left])                        \n\t"
-      "lbu             %[left2],       2(%[left])                        \n\t"
-      "lbu             %[left3],       3(%[left])                        \n\t"
-
-      "lbu             %[top_left],    -1(%[above])                      \n\t"
-
-      "preceu.ph.qbl   %[abovel],      %[resl]                           \n\t"
-      "preceu.ph.qbr   %[abover],      %[resl]                           \n\t"
-
-      "replv.ph        %[left0],       %[left0]                          \n\t"
-      "replv.ph        %[left1],       %[left1]                          \n\t"
-      "replv.ph        %[left2],       %[left2]                          \n\t"
-      "replv.ph        %[left3],       %[left3]                          \n\t"
-
-      "replv.ph        %[top_left],    %[top_left]                       \n\t"
-
-      "addu.ph         %[resl],        %[abovel],         %[left0]       \n\t"
-      "subu.ph         %[resl],        %[resl],           %[top_left]    \n\t"
-
-      "addu.ph         %[resr],        %[abover],         %[left0]       \n\t"
-      "subu.ph         %[resr],        %[resr],           %[top_left]    \n\t"
-
-      "sll             %[res0],        %[resr],           16             \n\t"
-      "sra             %[res0],        %[res0],           16             \n\t"
-      "lbux            %[res0],        %[res0](%[cm])                    \n\t"
-
-      "sra             %[res1],        %[resr],           16             \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                    \n\t"
-      "sb              %[res0],        (%[dst])                          \n\t"
-
-      "sll             %[res0],        %[resl],           16             \n\t"
-      "sra             %[res0],        %[res0],           16             \n\t"
-      "lbux            %[res0],        %[res0](%[cm])                    \n\t"
-      "sb              %[res1],        1(%[dst])                         \n\t"
-
-      "sra             %[res1],        %[resl],           16             \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                    \n\t"
-
-      "addu.ph         %[resl],        %[abovel],         %[left1]       \n\t"
-      "subu.ph         %[resl],        %[resl],           %[top_left]    \n\t"
-
-      "addu.ph         %[resr],        %[abover],         %[left1]       \n\t"
-      "subu.ph         %[resr],        %[resr],           %[top_left]    \n\t"
-
-      "sb              %[res0],        2(%[dst])                         \n\t"
-      "sb              %[res1],        3(%[dst])                         \n\t"
-
-      "add             %[dst],          %[dst],           %[stride]      \n\t"
-
-      "sll             %[res0],        %[resr],           16             \n\t"
-      "sra             %[res0],        %[res0],           16             \n\t"
-      "lbux            %[res0],        %[res0](%[cm])                    \n\t"
-
-      "sra             %[res1],        %[resr],           16             \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                    \n\t"
-      "sb              %[res0],        (%[dst])                          \n\t"
-
-      "sll             %[res0],        %[resl],           16             \n\t"
-      "sra             %[res0],        %[res0],           16             \n\t"
-      "lbux            %[res0],        %[res0](%[cm])                    \n\t"
-
-      "sb              %[res1],        1(%[dst])                         \n\t"
-      "sra             %[res1],        %[resl],           16             \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                    \n\t"
-
-      "addu.ph         %[resl],        %[abovel],         %[left2]       \n\t"
-      "subu.ph         %[resl],        %[resl],           %[top_left]    \n\t"
-
-      "addu.ph         %[resr],        %[abover],         %[left2]       \n\t"
-      "subu.ph         %[resr],        %[resr],           %[top_left]    \n\t"
-
-      "sb              %[res0],        2(%[dst])                         \n\t"
-      "sb              %[res1],        3(%[dst])                         \n\t"
-
-      "add             %[dst],          %[dst],           %[stride]      \n\t"
-
-      "sll             %[res0],        %[resr],           16             \n\t"
-      "sra             %[res0],        %[res0],           16             \n\t"
-      "lbux            %[res0],        %[res0](%[cm])                    \n\t"
-
-      "sra             %[res1],        %[resr],           16             \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                    \n\t"
-      "sb              %[res0],        (%[dst])                          \n\t"
-
-      "sll             %[res0],        %[resl],           16             \n\t"
-      "sra             %[res0],        %[res0],           16             \n\t"
-      "lbux            %[res0],        %[res0](%[cm])                    \n\t"
-
-      "sb              %[res1],        1(%[dst])                         \n\t"
-      "sra             %[res1],        %[resl],           16             \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                    \n\t"
-
-      "addu.ph         %[resl],        %[abovel],        %[left3]        \n\t"
-      "subu.ph         %[resl],        %[resl],          %[top_left]     \n\t"
-
-      "addu.ph         %[resr],        %[abover],        %[left3]        \n\t"
-      "subu.ph         %[resr],        %[resr],          %[top_left]     \n\t"
-
-      "sb              %[res0],        2(%[dst])                         \n\t"
-      "sb              %[res1],        3(%[dst])                         \n\t"
-
-      "add             %[dst],          %[dst],          %[stride]       \n\t"
-
-      "sll             %[res0],        %[resr],           16             \n\t"
-      "sra             %[res0],        %[res0],           16             \n\t"
-      "lbux            %[res0],        %[res0](%[cm])                    \n\t"
-
-      "sra             %[res1],        %[resr],           16             \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                    \n\t"
-      "sb              %[res0],        (%[dst])                          \n\t"
-
-      "sll             %[res0],        %[resl],           16             \n\t"
-      "sra             %[res0],        %[res0],           16             \n\t"
-      "lbux            %[res0],        %[res0](%[cm])                    \n\t"
-      "sb              %[res1],        1(%[dst])                         \n\t"
-
-      "sra             %[res1],        %[resl],           16             \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                    \n\t"
-
-      "sb              %[res0],        2(%[dst])                         \n\t"
-      "sb              %[res1],        3(%[dst])                         \n\t"
-
-      : [abovel] "=&r"(abovel), [abover] "=&r"(abover), [left0] "=&r"(left0),
-        [left1] "=&r"(left1), [left2] "=&r"(left2), [res0] "=&r"(res0),
-        [res1] "=&r"(res1), [left3] "=&r"(left3), [resl] "=&r"(resl),
-        [resr] "=&r"(resr), [top_left] "=&r"(top_left)
-      : [above] "r"(above), [left] "r"(left), [dst] "r"(dst),
-        [stride] "r"(stride), [cm] "r"(cm));
-}
 #endif  // #if HAVE_DSPR2
diff --git a/aom_dsp/mips/intrapred8_dspr2.c b/aom_dsp/mips/intrapred8_dspr2.c
index 1114fbc..98bdb08 100644
--- a/aom_dsp/mips/intrapred8_dspr2.c
+++ b/aom_dsp/mips/intrapred8_dspr2.c
@@ -146,458 +146,4 @@
       : [above] "r"(above), [left] "r"(left), [dst] "r"(dst),
         [stride] "r"(stride));
 }
-
-void aom_tm_predictor_8x8_dspr2(uint8_t *dst, ptrdiff_t stride,
-                                const uint8_t *above, const uint8_t *left) {
-  int32_t abovel, abover;
-  int32_t abovel_1, abover_1;
-  int32_t left0;
-  int32_t res0, res1, res2, res3;
-  int32_t reshw;
-  int32_t top_left;
-  uint8_t *cm = aom_ff_cropTbl;
-
-  __asm__ __volatile__(
-      "ulw             %[reshw],       (%[above])                         \n\t"
-      "ulw             %[top_left],    4(%[above])                        \n\t"
-
-      "lbu             %[left0],       (%[left])                          \n\t"
-
-      "preceu.ph.qbl   %[abovel],      %[reshw]                           \n\t"
-      "preceu.ph.qbr   %[abover],      %[reshw]                           \n\t"
-      "preceu.ph.qbl   %[abovel_1],    %[top_left]                        \n\t"
-      "preceu.ph.qbr   %[abover_1],    %[top_left]                        \n\t"
-
-      "lbu             %[top_left],    -1(%[above])                       \n\t"
-      "replv.ph        %[left0],       %[left0]                           \n\t"
-
-      "replv.ph        %[top_left],    %[top_left]                        \n\t"
-
-      "addu.ph         %[reshw],       %[abovel],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        (%[dst])                           \n\t"
-      "sb              %[res1],        1(%[dst])                          \n\t"
-      "sb              %[res2],        2(%[dst])                          \n\t"
-      "sb              %[res3],        3(%[dst])                          \n\t"
-
-      "addu.ph         %[reshw],       %[abovel_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbu             %[left0],       1(%[left])                         \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        4(%[dst])                          \n\t"
-      "sb              %[res1],        5(%[dst])                          \n\t"
-      "sb              %[res2],        6(%[dst])                          \n\t"
-      "sb              %[res3],        7(%[dst])                          \n\t"
-
-      "replv.ph        %[left0],       %[left0]                           \n\t"
-      "add             %[dst],          %[dst],             %[stride]     \n\t"
-
-      "addu.ph         %[reshw],       %[abovel],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        (%[dst])                           \n\t"
-      "sb              %[res1],        1(%[dst])                          \n\t"
-      "sb              %[res2],        2(%[dst])                          \n\t"
-      "sb              %[res3],        3(%[dst])                          \n\t"
-
-      "addu.ph         %[reshw],       %[abovel_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbu             %[left0],       2(%[left])                         \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        4(%[dst])                          \n\t"
-      "sb              %[res1],        5(%[dst])                          \n\t"
-      "sb              %[res2],        6(%[dst])                          \n\t"
-      "sb              %[res3],        7(%[dst])                          \n\t"
-
-      "replv.ph        %[left0],       %[left0]                           \n\t"
-      "add             %[dst],          %[dst],             %[stride]     \n\t"
-
-      "addu.ph         %[reshw],       %[abovel],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        (%[dst])                           \n\t"
-      "sb              %[res1],        1(%[dst])                          \n\t"
-      "sb              %[res2],        2(%[dst])                          \n\t"
-      "sb              %[res3],        3(%[dst])                          \n\t"
-
-      "addu.ph         %[reshw],       %[abovel_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbu             %[left0],       3(%[left])                         \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        4(%[dst])                          \n\t"
-      "sb              %[res1],        5(%[dst])                          \n\t"
-      "sb              %[res2],        6(%[dst])                          \n\t"
-      "sb              %[res3],        7(%[dst])                          \n\t"
-
-      "replv.ph        %[left0],       %[left0]                           \n\t"
-      "add             %[dst],          %[dst],             %[stride]     \n\t"
-
-      "addu.ph         %[reshw],       %[abovel],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        (%[dst])                           \n\t"
-      "sb              %[res1],        1(%[dst])                          \n\t"
-      "sb              %[res2],        2(%[dst])                          \n\t"
-      "sb              %[res3],        3(%[dst])                          \n\t"
-
-      "addu.ph         %[reshw],       %[abovel_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbu             %[left0],       4(%[left])                         \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        4(%[dst])                          \n\t"
-      "sb              %[res1],        5(%[dst])                          \n\t"
-      "sb              %[res2],        6(%[dst])                          \n\t"
-      "sb              %[res3],        7(%[dst])                          \n\t"
-
-      "replv.ph        %[left0],       %[left0]                           \n\t"
-      "add             %[dst],          %[dst],             %[stride]     \n\t"
-
-      "addu.ph         %[reshw],       %[abovel],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        (%[dst])                           \n\t"
-      "sb              %[res1],        1(%[dst])                          \n\t"
-      "sb              %[res2],        2(%[dst])                          \n\t"
-      "sb              %[res3],        3(%[dst])                          \n\t"
-
-      "addu.ph         %[reshw],       %[abovel_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbu             %[left0],       5(%[left])                         \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        4(%[dst])                          \n\t"
-      "sb              %[res1],        5(%[dst])                          \n\t"
-      "sb              %[res2],        6(%[dst])                          \n\t"
-      "sb              %[res3],        7(%[dst])                          \n\t"
-
-      "replv.ph        %[left0],       %[left0]                           \n\t"
-      "add             %[dst],          %[dst],             %[stride]     \n\t"
-
-      "addu.ph         %[reshw],       %[abovel],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        (%[dst])                           \n\t"
-      "sb              %[res1],        1(%[dst])                          \n\t"
-      "sb              %[res2],        2(%[dst])                          \n\t"
-      "sb              %[res3],        3(%[dst])                          \n\t"
-
-      "addu.ph         %[reshw],       %[abovel_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbu             %[left0],       6(%[left])                         \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        4(%[dst])                          \n\t"
-      "sb              %[res1],        5(%[dst])                          \n\t"
-      "sb              %[res2],        6(%[dst])                          \n\t"
-      "sb              %[res3],        7(%[dst])                          \n\t"
-
-      "replv.ph        %[left0],       %[left0]                           \n\t"
-      "add             %[dst],          %[dst],             %[stride]     \n\t"
-
-      "addu.ph         %[reshw],       %[abovel],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        (%[dst])                           \n\t"
-      "sb              %[res1],        1(%[dst])                          \n\t"
-      "sb              %[res2],        2(%[dst])                          \n\t"
-      "sb              %[res3],        3(%[dst])                          \n\t"
-
-      "addu.ph         %[reshw],       %[abovel_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbu             %[left0],       7(%[left])                         \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        4(%[dst])                          \n\t"
-      "sb              %[res1],        5(%[dst])                          \n\t"
-      "sb              %[res2],        6(%[dst])                          \n\t"
-      "sb              %[res3],        7(%[dst])                          \n\t"
-
-      "replv.ph        %[left0],       %[left0]                           \n\t"
-      "add             %[dst],          %[dst],             %[stride]     \n\t"
-
-      "addu.ph         %[reshw],       %[abovel],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover],           %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        (%[dst])                           \n\t"
-      "sb              %[res1],        1(%[dst])                          \n\t"
-      "sb              %[res2],        2(%[dst])                          \n\t"
-      "sb              %[res3],        3(%[dst])                          \n\t"
-
-      "addu.ph         %[reshw],       %[abovel_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res2],        %[reshw],            16            \n\t"
-      "sra             %[res2],        %[res2],             16            \n\t"
-      "sra             %[res3],        %[reshw],            16            \n\t"
-
-      "addu.ph         %[reshw],       %[abover_1],         %[left0]      \n\t"
-      "subu.ph         %[reshw],       %[reshw],            %[top_left]   \n\t"
-
-      "sll             %[res0],        %[reshw],            16            \n\t"
-      "sra             %[res0],        %[res0],             16            \n\t"
-      "sra             %[res1],        %[reshw],            16            \n\t"
-
-      "lbux            %[res0],        %[res0](%[cm])                     \n\t"
-      "lbux            %[res1],        %[res1](%[cm])                     \n\t"
-      "lbux            %[res2],        %[res2](%[cm])                     \n\t"
-      "lbux            %[res3],        %[res3](%[cm])                     \n\t"
-
-      "sb              %[res0],        4(%[dst])                          \n\t"
-      "sb              %[res1],        5(%[dst])                          \n\t"
-      "sb              %[res2],        6(%[dst])                          \n\t"
-      "sb              %[res3],        7(%[dst])                          \n\t"
-
-      : [abovel] "=&r"(abovel), [abover] "=&r"(abover),
-        [abovel_1] "=&r"(abovel_1), [abover_1] "=&r"(abover_1),
-        [left0] "=&r"(left0), [res2] "=&r"(res2), [res3] "=&r"(res3),
-        [res0] "=&r"(res0), [res1] "=&r"(res1), [reshw] "=&r"(reshw),
-        [top_left] "=&r"(top_left)
-      : [above] "r"(above), [left] "r"(left), [dst] "r"(dst),
-        [stride] "r"(stride), [cm] "r"(cm));
-}
 #endif  // #if HAVE_DSPR2
diff --git a/aom_dsp/mips/intrapred_msa.c b/aom_dsp/mips/intrapred_msa.c
index e8eaec7..bcb9c9df 100644
--- a/aom_dsp/mips/intrapred_msa.c
+++ b/aom_dsp/mips/intrapred_msa.c
@@ -382,176 +382,6 @@
   }
 }
 
-static void intra_predict_tm_4x4_msa(const uint8_t *src_top_ptr,
-                                     const uint8_t *src_left, uint8_t *dst,
-                                     int32_t dst_stride) {
-  uint32_t val;
-  uint8_t top_left = src_top_ptr[-1];
-  v16i8 src_left0, src_left1, src_left2, src_left3, tmp0, tmp1, src_top = { 0 };
-  v16u8 src0, src1, src2, src3;
-  v8u16 src_top_left, vec0, vec1, vec2, vec3;
-
-  src_top_left = (v8u16)__msa_fill_h(top_left);
-  val = LW(src_top_ptr);
-  src_top = (v16i8)__msa_insert_w((v4i32)src_top, 0, val);
-
-  src_left0 = __msa_fill_b(src_left[0]);
-  src_left1 = __msa_fill_b(src_left[1]);
-  src_left2 = __msa_fill_b(src_left[2]);
-  src_left3 = __msa_fill_b(src_left[3]);
-
-  ILVR_B4_UB(src_left0, src_top, src_left1, src_top, src_left2, src_top,
-             src_left3, src_top, src0, src1, src2, src3);
-  HADD_UB4_UH(src0, src1, src2, src3, vec0, vec1, vec2, vec3);
-  IPRED_SUBS_UH2_UH(src_top_left, src_top_left, vec0, vec1);
-  IPRED_SUBS_UH2_UH(src_top_left, src_top_left, vec2, vec3);
-  SAT_UH4_UH(vec0, vec1, vec2, vec3, 7);
-  PCKEV_B2_SB(vec1, vec0, vec3, vec2, tmp0, tmp1);
-  ST4x4_UB(tmp0, tmp1, 0, 2, 0, 2, dst, dst_stride);
-}
-
-static void intra_predict_tm_8x8_msa(const uint8_t *src_top_ptr,
-                                     const uint8_t *src_left, uint8_t *dst,
-                                     int32_t dst_stride) {
-  uint64_t val;
-  uint8_t top_left = src_top_ptr[-1];
-  uint32_t loop_cnt;
-  v16i8 src_left0, src_left1, src_left2, src_left3, tmp0, tmp1, src_top = { 0 };
-  v8u16 src_top_left, vec0, vec1, vec2, vec3;
-  v16u8 src0, src1, src2, src3;
-
-  val = LD(src_top_ptr);
-  src_top = (v16i8)__msa_insert_d((v2i64)src_top, 0, val);
-  src_top_left = (v8u16)__msa_fill_h(top_left);
-
-  for (loop_cnt = 2; loop_cnt--;) {
-    src_left0 = __msa_fill_b(src_left[0]);
-    src_left1 = __msa_fill_b(src_left[1]);
-    src_left2 = __msa_fill_b(src_left[2]);
-    src_left3 = __msa_fill_b(src_left[3]);
-    src_left += 4;
-
-    ILVR_B4_UB(src_left0, src_top, src_left1, src_top, src_left2, src_top,
-               src_left3, src_top, src0, src1, src2, src3);
-    HADD_UB4_UH(src0, src1, src2, src3, vec0, vec1, vec2, vec3);
-    IPRED_SUBS_UH2_UH(src_top_left, src_top_left, vec0, vec1);
-    IPRED_SUBS_UH2_UH(src_top_left, src_top_left, vec2, vec3);
-    SAT_UH4_UH(vec0, vec1, vec2, vec3, 7);
-    PCKEV_B2_SB(vec1, vec0, vec3, vec2, tmp0, tmp1);
-    ST8x4_UB(tmp0, tmp1, dst, dst_stride);
-    dst += (4 * dst_stride);
-  }
-}
-
-static void intra_predict_tm_16x16_msa(const uint8_t *src_top_ptr,
-                                       const uint8_t *src_left, uint8_t *dst,
-                                       int32_t dst_stride) {
-  uint8_t top_left = src_top_ptr[-1];
-  uint32_t loop_cnt;
-  v16i8 src_top, src_left0, src_left1, src_left2, src_left3;
-  v8u16 src_top_left, res_r, res_l;
-
-  src_top = LD_SB(src_top_ptr);
-  src_top_left = (v8u16)__msa_fill_h(top_left);
-
-  for (loop_cnt = 4; loop_cnt--;) {
-    src_left0 = __msa_fill_b(src_left[0]);
-    src_left1 = __msa_fill_b(src_left[1]);
-    src_left2 = __msa_fill_b(src_left[2]);
-    src_left3 = __msa_fill_b(src_left[3]);
-    src_left += 4;
-
-    ILVRL_B2_UH(src_left0, src_top, res_r, res_l);
-    HADD_UB2_UH(res_r, res_l, res_r, res_l);
-    IPRED_SUBS_UH2_UH(src_top_left, src_top_left, res_r, res_l);
-
-    SAT_UH2_UH(res_r, res_l, 7);
-    PCKEV_ST_SB(res_r, res_l, dst);
-    dst += dst_stride;
-
-    ILVRL_B2_UH(src_left1, src_top, res_r, res_l);
-    HADD_UB2_UH(res_r, res_l, res_r, res_l);
-    IPRED_SUBS_UH2_UH(src_top_left, src_top_left, res_r, res_l);
-    SAT_UH2_UH(res_r, res_l, 7);
-    PCKEV_ST_SB(res_r, res_l, dst);
-    dst += dst_stride;
-
-    ILVRL_B2_UH(src_left2, src_top, res_r, res_l);
-    HADD_UB2_UH(res_r, res_l, res_r, res_l);
-    IPRED_SUBS_UH2_UH(src_top_left, src_top_left, res_r, res_l);
-    SAT_UH2_UH(res_r, res_l, 7);
-    PCKEV_ST_SB(res_r, res_l, dst);
-    dst += dst_stride;
-
-    ILVRL_B2_UH(src_left3, src_top, res_r, res_l);
-    HADD_UB2_UH(res_r, res_l, res_r, res_l);
-    IPRED_SUBS_UH2_UH(src_top_left, src_top_left, res_r, res_l);
-    SAT_UH2_UH(res_r, res_l, 7);
-    PCKEV_ST_SB(res_r, res_l, dst);
-    dst += dst_stride;
-  }
-}
-
-static void intra_predict_tm_32x32_msa(const uint8_t *src_top,
-                                       const uint8_t *src_left, uint8_t *dst,
-                                       int32_t dst_stride) {
-  uint8_t top_left = src_top[-1];
-  uint32_t loop_cnt;
-  v16i8 src_top0, src_top1, src_left0, src_left1, src_left2, src_left3;
-  v8u16 src_top_left, res_r0, res_r1, res_l0, res_l1;
-
-  LD_SB2(src_top, 16, src_top0, src_top1);
-  src_top_left = (v8u16)__msa_fill_h(top_left);
-
-  for (loop_cnt = 8; loop_cnt--;) {
-    src_left0 = __msa_fill_b(src_left[0]);
-    src_left1 = __msa_fill_b(src_left[1]);
-    src_left2 = __msa_fill_b(src_left[2]);
-    src_left3 = __msa_fill_b(src_left[3]);
-    src_left += 4;
-
-    ILVR_B2_UH(src_left0, src_top0, src_left0, src_top1, res_r0, res_r1);
-    ILVL_B2_UH(src_left0, src_top0, src_left0, src_top1, res_l0, res_l1);
-    HADD_UB4_UH(res_r0, res_l0, res_r1, res_l1, res_r0, res_l0, res_r1, res_l1);
-    IPRED_SUBS_UH2_UH(src_top_left, src_top_left, res_r0, res_l0);
-    IPRED_SUBS_UH2_UH(src_top_left, src_top_left, res_r1, res_l1);
-    SAT_UH4_UH(res_r0, res_l0, res_r1, res_l1, 7);
-    PCKEV_ST_SB(res_r0, res_l0, dst);
-    PCKEV_ST_SB(res_r1, res_l1, dst + 16);
-    dst += dst_stride;
-
-    ILVR_B2_UH(src_left1, src_top0, src_left1, src_top1, res_r0, res_r1);
-    ILVL_B2_UH(src_left1, src_top0, src_left1, src_top1, res_l0, res_l1);
-    HADD_UB4_UH(res_r0, res_l0, res_r1, res_l1, res_r0, res_l0, res_r1, res_l1);
-    IPRED_SUBS_UH2_UH(src_top_left, src_top_left, res_r0, res_l0);
-    IPRED_SUBS_UH2_UH(src_top_left, src_top_left, res_r1, res_l1);
-    SAT_UH4_UH(res_r0, res_l0, res_r1, res_l1, 7);
-    PCKEV_ST_SB(res_r0, res_l0, dst);
-    PCKEV_ST_SB(res_r1, res_l1, dst + 16);
-    dst += dst_stride;
-
-    ILVR_B2_UH(src_left2, src_top0, src_left2, src_top1, res_r0, res_r1);
-    ILVL_B2_UH(src_left2, src_top0, src_left2, src_top1, res_l0, res_l1);
-    HADD_UB4_UH(res_r0, res_l0, res_r1, res_l1, res_r0, res_l0, res_r1, res_l1);
-    IPRED_SUBS_UH2_UH(src_top_left, src_top_left, res_r0, res_l0);
-    IPRED_SUBS_UH2_UH(src_top_left, src_top_left, res_r1, res_l1);
-    SAT_UH4_UH(res_r0, res_l0, res_r1, res_l1, 7);
-    PCKEV_ST_SB(res_r0, res_l0, dst);
-    PCKEV_ST_SB(res_r1, res_l1, dst + 16);
-    dst += dst_stride;
-
-    ILVR_B2_UH(src_left3, src_top0, src_left3, src_top1, res_r0, res_r1);
-    ILVL_B2_UH(src_left3, src_top0, src_left3, src_top1, res_l0, res_l1);
-    HADD_UB4_UH(res_r0, res_l0, res_r1, res_l1, res_r0, res_l0, res_r1, res_l1);
-    IPRED_SUBS_UH2_UH(src_top_left, src_top_left, res_r0, res_l0);
-    IPRED_SUBS_UH2_UH(src_top_left, src_top_left, res_r1, res_l1);
-    SAT_UH4_UH(res_r0, res_l0, res_r1, res_l1, 7);
-    PCKEV_ST_SB(res_r0, res_l0, dst);
-    PCKEV_ST_SB(res_r1, res_l1, dst + 16);
-    dst += dst_stride;
-  }
-}
-
 void aom_v_predictor_4x4_msa(uint8_t *dst, ptrdiff_t y_stride,
                              const uint8_t *above, const uint8_t *left) {
   (void)left;
@@ -717,23 +547,3 @@
 
   intra_predict_128dc_32x32_msa(dst, y_stride);
 }
-
-void aom_tm_predictor_4x4_msa(uint8_t *dst, ptrdiff_t y_stride,
-                              const uint8_t *above, const uint8_t *left) {
-  intra_predict_tm_4x4_msa(above, left, dst, y_stride);
-}
-
-void aom_tm_predictor_8x8_msa(uint8_t *dst, ptrdiff_t y_stride,
-                              const uint8_t *above, const uint8_t *left) {
-  intra_predict_tm_8x8_msa(above, left, dst, y_stride);
-}
-
-void aom_tm_predictor_16x16_msa(uint8_t *dst, ptrdiff_t y_stride,
-                                const uint8_t *above, const uint8_t *left) {
-  intra_predict_tm_16x16_msa(above, left, dst, y_stride);
-}
-
-void aom_tm_predictor_32x32_msa(uint8_t *dst, ptrdiff_t y_stride,
-                                const uint8_t *above, const uint8_t *left) {
-  intra_predict_tm_32x32_msa(above, left, dst, y_stride);
-}
diff --git a/aom_dsp/x86/highbd_intrapred_sse2.asm b/aom_dsp/x86/highbd_intrapred_sse2.asm
index 5d84ef8..91b3d12 100644
--- a/aom_dsp/x86/highbd_intrapred_sse2.asm
+++ b/aom_dsp/x86/highbd_intrapred_sse2.asm
@@ -257,200 +257,3 @@
   dec             nlines4d
   jnz .loop
   REP_RET
-
-INIT_XMM sse2
-cglobal highbd_tm_predictor_4x4, 5, 5, 6, dst, stride, above, left, bps
-  movd                  m1, [aboveq-2]
-  movq                  m0, [aboveq]
-  pshuflw               m1, m1, 0x0
-  movlhps               m0, m0         ; t1 t2 t3 t4 t1 t2 t3 t4
-  movlhps               m1, m1         ; tl tl tl tl tl tl tl tl
-  ; Get the values to compute the maximum value at this bit depth
-  pcmpeqw               m3, m3
-  movd                  m4, bpsd
-  psubw                 m0, m1         ; t1-tl t2-tl t3-tl t4-tl
-  psllw                 m3, m4
-  pcmpeqw               m2, m2
-  pxor                  m4, m4         ; min possible value
-  pxor                  m3, m2         ; max possible value
-  mova                  m1, [leftq]
-  pshuflw               m2, m1, 0x0
-  pshuflw               m5, m1, 0x55
-  movlhps               m2, m5         ; l1 l1 l1 l1 l2 l2 l2 l2
-  paddw                 m2, m0
-  ;Clamp to the bit-depth
-  pminsw                m2, m3
-  pmaxsw                m2, m4
-  ;Store the values
-  movq    [dstq          ], m2
-  movhpd  [dstq+strideq*2], m2
-  lea                 dstq, [dstq+strideq*4]
-  pshuflw               m2, m1, 0xaa
-  pshuflw               m5, m1, 0xff
-  movlhps               m2, m5
-  paddw                 m2, m0
-  ;Clamp to the bit-depth
-  pminsw                m2, m3
-  pmaxsw                m2, m4
-  ;Store the values
-  movq    [dstq          ], m2
-  movhpd  [dstq+strideq*2], m2
-  RET
-
-INIT_XMM sse2
-cglobal highbd_tm_predictor_8x8, 5, 6, 5, dst, stride, above, left, bps, one
-  movd                  m1, [aboveq-2]
-  mova                  m0, [aboveq]
-  pshuflw               m1, m1, 0x0
-  ; Get the values to compute the maximum value at this bit depth
-  mov                 oned, 1
-  pxor                  m3, m3
-  pxor                  m4, m4
-  pinsrw                m3, oned, 0
-  pinsrw                m4, bpsd, 0
-  pshuflw               m3, m3, 0x0
-  DEFINE_ARGS dst, stride, line, left
-  punpcklqdq            m3, m3
-  mov                lineq, -4
-  mova                  m2, m3
-  punpcklqdq            m1, m1
-  psllw                 m3, m4
-  add                leftq, 16
-  psubw                 m3, m2 ; max possible value
-  pxor                  m4, m4 ; min possible value
-  psubw                 m0, m1
-.loop:
-  movd                  m1, [leftq+lineq*4]
-  movd                  m2, [leftq+lineq*4+2]
-  pshuflw               m1, m1, 0x0
-  pshuflw               m2, m2, 0x0
-  punpcklqdq            m1, m1
-  punpcklqdq            m2, m2
-  paddw                 m1, m0
-  paddw                 m2, m0
-  ;Clamp to the bit-depth
-  pminsw                m1, m3
-  pminsw                m2, m3
-  pmaxsw                m1, m4
-  pmaxsw                m2, m4
-  ;Store the values
-  mova      [dstq          ], m1
-  mova      [dstq+strideq*2], m2
-  lea                 dstq, [dstq+strideq*4]
-  inc                lineq
-  jnz .loop
-  REP_RET
-
-INIT_XMM sse2
-cglobal highbd_tm_predictor_16x16, 5, 5, 8, dst, stride, above, left, bps
-  movd                  m2, [aboveq-2]
-  mova                  m0, [aboveq]
-  mova                  m1, [aboveq+16]
-  pshuflw               m2, m2, 0x0
-  ; Get the values to compute the maximum value at this bit depth
-  pcmpeqw               m3, m3
-  movd                  m4, bpsd
-  punpcklqdq            m2, m2
-  psllw                 m3, m4
-  pcmpeqw               m5, m5
-  pxor                  m4, m4         ; min possible value
-  pxor                  m3, m5         ; max possible value
-  DEFINE_ARGS dst, stride, line, left
-  mov                lineq, -8
-  psubw                 m0, m2
-  psubw                 m1, m2
-.loop:
-  movd                  m7, [leftq]
-  pshuflw               m5, m7, 0x0
-  pshuflw               m2, m7, 0x55
-  punpcklqdq            m5, m5         ; l1 l1 l1 l1 l1 l1 l1 l1
-  punpcklqdq            m2, m2         ; l2 l2 l2 l2 l2 l2 l2 l2
-  paddw                 m6, m5, m0     ; t1-tl+l1 to t4-tl+l1
-  paddw                 m5, m1         ; t5-tl+l1 to t8-tl+l1
-  pminsw                m6, m3
-  pminsw                m5, m3
-  pmaxsw                m6, m4         ; Clamp to the bit-depth
-  pmaxsw                m5, m4
-  mova   [dstq           ], m6
-  mova   [dstq        +16], m5
-  paddw                 m6, m2, m0
-  paddw                 m2, m1
-  pminsw                m6, m3
-  pminsw                m2, m3
-  pmaxsw                m6, m4
-  pmaxsw                m2, m4
-  mova   [dstq+strideq*2 ], m6
-  mova [dstq+strideq*2+16], m2
-  lea                 dstq, [dstq+strideq*4]
-  inc                lineq
-  lea                leftq, [leftq+4]
-
-  jnz .loop
-  REP_RET
-
-INIT_XMM sse2
-cglobal highbd_tm_predictor_32x32, 5, 5, 8, dst, stride, above, left, bps
-  movd                  m0, [aboveq-2]
-  mova                  m1, [aboveq]
-  mova                  m2, [aboveq+16]
-  mova                  m3, [aboveq+32]
-  mova                  m4, [aboveq+48]
-  pshuflw               m0, m0, 0x0
-  ; Get the values to compute the maximum value at this bit depth
-  pcmpeqw               m5, m5
-  movd                  m6, bpsd
-  psllw                 m5, m6
-  pcmpeqw               m7, m7
-  pxor                  m6, m6         ; min possible value
-  pxor                  m5, m7         ; max possible value
-  punpcklqdq            m0, m0
-  DEFINE_ARGS dst, stride, line, left
-  mov                lineq, -16
-  psubw                 m1, m0
-  psubw                 m2, m0
-  psubw                 m3, m0
-  psubw                 m4, m0
-.loop:
-  movd                  m7, [leftq]
-  pshuflw               m7, m7, 0x0
-  punpcklqdq            m7, m7         ; l1 l1 l1 l1 l1 l1 l1 l1
-  paddw                 m0, m7, m1
-  pminsw                m0, m5
-  pmaxsw                m0, m6
-  mova   [dstq           ], m0
-  paddw                 m0, m7, m2
-  pminsw                m0, m5
-  pmaxsw                m0, m6
-  mova   [dstq        +16], m0
-  paddw                 m0, m7, m3
-  pminsw                m0, m5
-  pmaxsw                m0, m6
-  mova   [dstq        +32], m0
-  paddw                 m0, m7, m4
-  pminsw                m0, m5
-  pmaxsw                m0, m6
-  mova   [dstq        +48], m0
-  movd                  m7, [leftq+2]
-  pshuflw               m7, m7, 0x0
-  punpcklqdq            m7, m7         ; l2 l2 l2 l2 l2 l2 l2 l2
-  paddw                 m0, m7, m1
-  pminsw                m0, m5
-  pmaxsw                m0, m6
-  mova   [dstq+strideq*2 ], m0
-  paddw                 m0, m7, m2
-  pminsw                m0, m5
-  pmaxsw                m0, m6
-  mova   [dstq+strideq*2+16], m0
-  paddw                 m0, m7, m3
-  pminsw                m0, m5
-  pmaxsw                m0, m6
-  mova   [dstq+strideq*2+32], m0
-  paddw                 m0, m7, m4
-  pminsw                m0, m5
-  pmaxsw                m0, m6
-  mova   [dstq+strideq*2+48], m0
-  lea                 dstq, [dstq+strideq*4]
-  lea                leftq, [leftq+4]
-  inc                lineq
-  jnz .loop
-  REP_RET
diff --git a/aom_dsp/x86/intrapred_sse2.asm b/aom_dsp/x86/intrapred_sse2.asm
index 02567db..9aece27 100644
--- a/aom_dsp/x86/intrapred_sse2.asm
+++ b/aom_dsp/x86/intrapred_sse2.asm
@@ -623,149 +623,3 @@
   lea                     dstq, [dstq+strideq*4]
   jnz .loop
   REP_RET
-
-INIT_XMM sse2
-cglobal tm_predictor_4x4, 4, 4, 5, dst, stride, above, left
-  pxor                  m1, m1
-  movq                  m0, [aboveq-1]; [63:0] tl t1 t2 t3 t4 x x x
-  punpcklbw             m0, m1
-  pshuflw               m2, m0, 0x0   ; [63:0] tl tl tl tl [word]
-  psrldq                m0, 2
-  psubw                 m0, m2        ; [63:0] t1-tl t2-tl t3-tl t4-tl [word]
-  movd                  m2, [leftq]
-  punpcklbw             m2, m1
-  pshuflw               m4, m2, 0x0   ; [63:0] l1 l1 l1 l1 [word]
-  pshuflw               m3, m2, 0x55  ; [63:0] l2 l2 l2 l2 [word]
-  paddw                 m4, m0
-  paddw                 m3, m0
-  packuswb              m4, m4
-  packuswb              m3, m3
-  movd      [dstq        ], m4
-  movd      [dstq+strideq], m3
-  lea                 dstq, [dstq+strideq*2]
-  pshuflw               m4, m2, 0xaa
-  pshuflw               m3, m2, 0xff
-  paddw                 m4, m0
-  paddw                 m3, m0
-  packuswb              m4, m4
-  packuswb              m3, m3
-  movd      [dstq        ], m4
-  movd      [dstq+strideq], m3
-  RET
-
-INIT_XMM sse2
-cglobal tm_predictor_8x8, 4, 4, 5, dst, stride, above, left
-  pxor                  m1, m1
-  movd                  m2, [aboveq-1]
-  movq                  m0, [aboveq]
-  punpcklbw             m2, m1
-  punpcklbw             m0, m1        ; t1 t2 t3 t4 t5 t6 t7 t8 [word]
-  pshuflw               m2, m2, 0x0   ; [63:0] tl tl tl tl [word]
-  DEFINE_ARGS dst, stride, line, left
-  mov                lineq, -4
-  punpcklqdq            m2, m2        ; tl tl tl tl tl tl tl tl [word]
-  psubw                 m0, m2        ; t1-tl t2-tl ... t8-tl [word]
-  movq                  m2, [leftq]
-  punpcklbw             m2, m1        ; l1 l2 l3 l4 l5 l6 l7 l8 [word]
-.loop:
-  pshuflw               m4, m2, 0x0   ; [63:0] l1 l1 l1 l1 [word]
-  pshuflw               m3, m2, 0x55  ; [63:0] l2 l2 l2 l2 [word]
-  punpcklqdq            m4, m4        ; l1 l1 l1 l1 l1 l1 l1 l1 [word]
-  punpcklqdq            m3, m3        ; l2 l2 l2 l2 l2 l2 l2 l2 [word]
-  paddw                 m4, m0
-  paddw                 m3, m0
-  packuswb              m4, m3
-  movq      [dstq        ], m4
-  movhps    [dstq+strideq], m4
-  lea                 dstq, [dstq+strideq*2]
-  psrldq                m2, 4
-  inc                lineq
-  jnz .loop
-  REP_RET
-
-INIT_XMM sse2
-cglobal tm_predictor_16x16, 4, 5, 8, dst, stride, above, left
-  pxor                  m1, m1
-  mova                  m2, [aboveq-16];
-  mova                  m0, [aboveq]   ; t1 t2 ... t16 [byte]
-  punpckhbw             m2, m1         ; [127:112] tl [word]
-  punpckhbw             m4, m0, m1
-  punpcklbw             m0, m1         ; m0:m4 t1 t2 ... t16 [word]
-  DEFINE_ARGS dst, stride, line, left, stride8
-  mov                lineq, -8
-  pshufhw               m2, m2, 0xff
-  mova                  m3, [leftq]    ; l1 l2 ... l16 [byte]
-  punpckhqdq            m2, m2         ; tl repeated 8 times [word]
-  psubw                 m0, m2
-  psubw                 m4, m2         ; m0:m4 t1-tl t2-tl ... t16-tl [word]
-  punpckhbw             m5, m3, m1
-  punpcklbw             m3, m1         ; m3:m5 l1 l2 ... l16 [word]
-  lea             stride8q, [strideq*8]
-.loop:
-  pshuflw               m6, m3, 0x0
-  pshuflw               m7, m5, 0x0
-  punpcklqdq            m6, m6         ; l1 repeated 8 times [word]
-  punpcklqdq            m7, m7         ; l8 repeated 8 times [word]
-  paddw                 m1, m6, m0
-  paddw                 m6, m4         ; m1:m6 ti-tl+l1 [i=1,15] [word]
-  psrldq                m5, 2
-  packuswb              m1, m6
-  mova     [dstq         ], m1
-  paddw                 m1, m7, m0
-  paddw                 m7, m4         ; m1:m7 ti-tl+l8 [i=1,15] [word]
-  psrldq                m3, 2
-  packuswb              m1, m7
-  mova     [dstq+stride8q], m1
-  inc                lineq
-  lea                 dstq, [dstq+strideq]
-  jnz .loop
-  REP_RET
-
-INIT_XMM sse2
-cglobal tm_predictor_32x32, 4, 4, 8, dst, stride, above, left
-  pxor                  m1, m1
-  movd                  m2, [aboveq-1]
-  mova                  m0, [aboveq]
-  mova                  m4, [aboveq+16]
-  punpcklbw             m2, m1
-  punpckhbw             m3, m0, m1
-  punpckhbw             m5, m4, m1
-  punpcklbw             m0, m1
-  punpcklbw             m4, m1
-  pshuflw               m2, m2, 0x0
-  DEFINE_ARGS dst, stride, line, left
-  mov                lineq, -16
-  punpcklqdq            m2, m2
-  add                leftq, 32
-  psubw                 m0, m2
-  psubw                 m3, m2
-  psubw                 m4, m2
-  psubw                 m5, m2
-.loop:
-  movd                  m2, [leftq+lineq*2]
-  pxor                  m1, m1
-  punpcklbw             m2, m1
-  pshuflw               m7, m2, 0x55
-  pshuflw               m2, m2, 0x0
-  punpcklqdq            m2, m2
-  punpcklqdq            m7, m7
-  paddw                 m6, m2, m3
-  paddw                 m1, m2, m0
-  packuswb              m1, m6
-  mova   [dstq           ], m1
-  paddw                 m6, m2, m5
-  paddw                 m1, m2, m4
-  packuswb              m1, m6
-  mova   [dstq+16        ], m1
-  paddw                 m6, m7, m3
-  paddw                 m1, m7, m0
-  packuswb              m1, m6
-  mova   [dstq+strideq   ], m1
-  paddw                 m6, m7, m5
-  paddw                 m1, m7, m4
-  packuswb              m1, m6
-  mova   [dstq+strideq+16], m1
-  lea                 dstq, [dstq+strideq*2]
-  inc                lineq
-  jnz .loop
-  REP_RET
diff --git a/av1/common/av1_loopfilter.c b/av1/common/av1_loopfilter.c
index 4ca4cb1..2cbc0b0 100644
--- a/av1/common/av1_loopfilter.c
+++ b/av1/common/av1_loopfilter.c
@@ -557,12 +557,10 @@
 
 static const int mode_lf_lut[] = {
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  // INTRA_MODES
-#if CONFIG_ALT_INTRA
   0,
 #if CONFIG_SMOOTH_HV
   0, 0,
 #endif         // CONFIG_SMOOTH_HV
-#endif         // CONFIG_ALT_INTRA
   1, 1, 0, 1,  // INTER_MODES (ZEROMV == 0)
 #if CONFIG_EXT_INTER
 #if CONFIG_COMPOUND_SINGLEREF
diff --git a/av1/common/blockd.h b/av1/common/blockd.h
index be46d8e..f6ded02 100644
--- a/av1/common/blockd.h
+++ b/av1/common/blockd.h
@@ -158,13 +158,11 @@
     MB_MODE_COUNT,  // D153_PRED
     MB_MODE_COUNT,  // D207_PRED
     MB_MODE_COUNT,  // D63_PRED
-#if CONFIG_ALT_INTRA
     MB_MODE_COUNT,  // SMOOTH_PRED
 #if CONFIG_SMOOTH_HV
     MB_MODE_COUNT,  // SMOOTH_V_PRED
     MB_MODE_COUNT,  // SMOOTH_H_PRED
 #endif              // CONFIG_SMOOTH_HV
-#endif              // CONFIG_ALT_INTRA
     MB_MODE_COUNT,  // TM_PRED
     MB_MODE_COUNT,  // NEARESTMV
     MB_MODE_COUNT,  // NEARMV
@@ -206,13 +204,11 @@
     MB_MODE_COUNT,  // D153_PRED
     MB_MODE_COUNT,  // D207_PRED
     MB_MODE_COUNT,  // D63_PRED
-#if CONFIG_ALT_INTRA
     MB_MODE_COUNT,  // SMOOTH_PRED
 #if CONFIG_SMOOTH_HV
     MB_MODE_COUNT,  // SMOOTH_V_PRED
     MB_MODE_COUNT,  // SMOOTH_H_PRED
 #endif              // CONFIG_SMOOTH_HV
-#endif              // CONFIG_ALT_INTRA
     MB_MODE_COUNT,  // TM_PRED
     MB_MODE_COUNT,  // NEARESTMV
     MB_MODE_COUNT,  // NEARMV
@@ -518,22 +514,20 @@
 #if CONFIG_CFL
 static INLINE PREDICTION_MODE get_uv_mode(UV_PREDICTION_MODE mode) {
   static const PREDICTION_MODE uv2y[UV_INTRA_MODES] = {
-    DC_PRED,    // UV_DC_PRED
-    V_PRED,     // UV_V_PRED
-    H_PRED,     // UV_H_PRED
-    D45_PRED,   // UV_D45_PRED
-    D135_PRED,  // UV_D135_PRED
-    D117_PRED,  // UV_D117_PRED
-    D153_PRED,  // UV_D153_PRED
-    D207_PRED,  // UV_D207_PRED
-    D63_PRED,   // UV_D63_PRED
-#if CONFIG_ALT_INTRA
+    DC_PRED,      // UV_DC_PRED
+    V_PRED,       // UV_V_PRED
+    H_PRED,       // UV_H_PRED
+    D45_PRED,     // UV_D45_PRED
+    D135_PRED,    // UV_D135_PRED
+    D117_PRED,    // UV_D117_PRED
+    D153_PRED,    // UV_D153_PRED
+    D207_PRED,    // UV_D207_PRED
+    D63_PRED,     // UV_D63_PRED
     SMOOTH_PRED,  // UV_SMOOTH_PRED
 #if CONFIG_SMOOTH_HV
     SMOOTH_V_PRED,  // UV_SMOOTH_V_PRED
     SMOOTH_H_PRED,  // UV_SMOOTH_H_PRED
 #endif              // CONFIG_SMOOTH_HV
-#endif              // CONFIG_ALT_INTRA
     TM_PRED,        // UV_TM_PRED
     DC_PRED,        // CFL_PRED
   };
@@ -815,13 +809,11 @@
   DCT_ADST,   // D153
   DCT_ADST,   // D207
   ADST_DCT,   // D63
-#if CONFIG_ALT_INTRA
   ADST_ADST,  // SMOOTH
 #if CONFIG_SMOOTH_HV
   ADST_DCT,   // SMOOTH_V
   DCT_ADST,   // SMOOTH_H
 #endif        // CONFIG_SMOOTH_HV
-#endif        // CONFIG_ALT_INTRA
   ADST_ADST,  // TM
 };
 
@@ -1204,13 +1196,10 @@
 #define ANGLE_STEP 3
 extern const int16_t dr_intra_derivative[90];
 static const uint8_t mode_to_angle_map[] = {
-  0, 90, 180, 45, 135, 111, 157, 203, 67, 0,
-#if CONFIG_ALT_INTRA
-  0,
+  0, 90, 180, 45, 135, 111, 157, 203, 67, 0, 0,
 #if CONFIG_SMOOTH_HV
   0, 0,
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
 };
 #if CONFIG_INTRA_INTERP
 // Returns whether filter selection is needed for a given
diff --git a/av1/common/entropymode.c b/av1/common/entropymode.c
index 363e8aa..b97e8a8 100644
--- a/av1/common/entropymode.c
+++ b/av1/common/entropymode.c
@@ -1078,7 +1078,6 @@
 int av1_ext_tx_inter_inv[EXT_TX_SETS_INTER][TX_TYPES];
 #endif
 
-#if CONFIG_ALT_INTRA
 #if CONFIG_SMOOTH_HV
 const int av1_intra_mode_ind[INTRA_MODES] = { 0, 2, 3,  6,  4,  5, 8,
                                               9, 7, 10, 11, 12, 1 };
@@ -1092,21 +1091,13 @@
   0, 10, 1, 2, 4, 5, 3, 8, 6, 7, 9
 };
 #endif  // CONFIG_SMOOTH_HV
-#else
-const int av1_intra_mode_ind[INTRA_MODES] = { 0, 2, 3, 6, 4, 5, 8, 9, 7, 1 };
-const int av1_intra_mode_inv[INTRA_MODES] = { 0, 9, 1, 2, 4, 5, 3, 8, 6, 7 };
-#endif  // CONFIG_ALT_INTRA
 
 #if CONFIG_EXT_INTER
 /* clang-format off */
 #if CONFIG_INTERINTRA
 const aom_tree_index av1_interintra_mode_tree[TREE_SIZE(INTERINTRA_MODES)] = {
   -II_DC_PRED, 2,        /* 0 = II_DC_NODE     */
-#if CONFIG_ALT_INTRA
   -II_SMOOTH_PRED, 4,    /* 1 = II_SMOOTH_PRED */
-#else
-  -II_TM_PRED, 4,        /* 1 = II_TM_NODE     */
-#endif
   -II_V_PRED, -II_H_PRED /* 2 = II_V_NODE      */
 };
 #endif  // CONFIG_INTERINTRA
@@ -2113,13 +2104,11 @@
                                        { 0 },
                                        { 0 },
                                        { 0 },
-#if CONFIG_ALT_INTRA
                                        { 0 },
 #if CONFIG_SMOOTH_HV
                                        { 0 },
                                        { 0 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 0 },
                                    },
                                    {
@@ -2132,13 +2121,11 @@
                                        { 0 },
                                        { 0 },
                                        { 0 },
-#if CONFIG_ALT_INTRA
                                        { 0 },
 #if CONFIG_SMOOTH_HV
                                        { 0 },
                                        { 0 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 0 },
                                    },
                                    {
@@ -2151,13 +2138,11 @@
                                        { 0 },
                                        { 0 },
                                        { 0 },
-#if CONFIG_ALT_INTRA
                                        { 0 },
 #if CONFIG_SMOOTH_HV
                                        { 0 },
                                        { 0 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 0 },
                                    },
                                    {
@@ -2170,13 +2155,11 @@
                                        { 0 },
                                        { 0 },
                                        { 0 },
-#if CONFIG_ALT_INTRA
                                        { 0 },
 #if CONFIG_SMOOTH_HV
                                        { 0 },
                                        { 0 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 0 },
                                    },
                                },
@@ -2196,13 +2179,11 @@
                                        { 10, 32, 32, 128, 16, 64 },
                                        { 10, 23, 32, 128, 80, 176 },
                                        { 10, 23, 32, 128, 80, 176 },
-#if CONFIG_ALT_INTRA
                                        { 10, 32, 32, 128, 16, 64 },
 #if CONFIG_SMOOTH_HV
                                        { 10, 32, 32, 128, 16, 64 },
                                        { 10, 32, 32, 128, 16, 64 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 10, 32, 32, 128, 16, 64 },
                                    },
                                    {
@@ -2215,13 +2196,11 @@
                                        { 10, 32, 32, 128, 16, 64 },
                                        { 10, 23, 32, 128, 80, 176 },
                                        { 10, 23, 32, 128, 80, 176 },
-#if CONFIG_ALT_INTRA
                                        { 10, 32, 32, 128, 16, 64 },
 #if CONFIG_SMOOTH_HV
                                        { 10, 32, 32, 128, 16, 64 },
                                        { 10, 32, 32, 128, 16, 64 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 10, 32, 32, 128, 16, 64 },
                                    },
                                    {
@@ -2234,13 +2213,11 @@
                                        { 10, 32, 32, 128, 16, 64 },
                                        { 10, 23, 32, 128, 80, 176 },
                                        { 10, 23, 32, 128, 80, 176 },
-#if CONFIG_ALT_INTRA
                                        { 10, 32, 32, 128, 16, 64 },
 #if CONFIG_SMOOTH_HV
                                        { 10, 32, 32, 128, 16, 64 },
                                        { 10, 32, 32, 128, 16, 64 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 10, 32, 32, 128, 16, 64 },
                                    },
                                    {
@@ -2253,13 +2230,11 @@
                                        { 10, 32, 32, 128, 16, 64 },
                                        { 10, 23, 32, 128, 80, 176 },
                                        { 10, 23, 32, 128, 80, 176 },
-#if CONFIG_ALT_INTRA
                                        { 10, 32, 32, 128, 16, 64 },
 #if CONFIG_SMOOTH_HV
                                        { 10, 32, 32, 128, 16, 64 },
                                        { 10, 32, 32, 128, 16, 64 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 10, 32, 32, 128, 16, 64 },
                                    },
                                },
@@ -2279,13 +2254,11 @@
                                        { 10, 32, 16, 64 },
                                        { 10, 23, 80, 176 },
                                        { 10, 23, 80, 176 },
-#if CONFIG_ALT_INTRA
                                        { 10, 32, 16, 64 },
 #if CONFIG_SMOOTH_HV
                                        { 10, 32, 16, 64 },
                                        { 10, 32, 16, 64 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 10, 32, 16, 64 },
                                    },
                                    {
@@ -2298,13 +2271,11 @@
                                        { 10, 32, 16, 64 },
                                        { 10, 23, 80, 176 },
                                        { 10, 23, 80, 176 },
-#if CONFIG_ALT_INTRA
                                        { 10, 32, 16, 64 },
 #if CONFIG_SMOOTH_HV
                                        { 10, 32, 16, 64 },
                                        { 10, 32, 16, 64 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 10, 32, 16, 64 },
                                    },
                                    {
@@ -2317,13 +2288,11 @@
                                        { 10, 32, 16, 64 },
                                        { 10, 23, 80, 176 },
                                        { 10, 23, 80, 176 },
-#if CONFIG_ALT_INTRA
                                        { 10, 32, 16, 64 },
 #if CONFIG_SMOOTH_HV
                                        { 10, 32, 16, 64 },
                                        { 10, 32, 16, 64 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 10, 32, 16, 64 },
                                    },
                                    {
@@ -2336,13 +2305,11 @@
                                        { 10, 32, 16, 64 },
                                        { 10, 23, 80, 176 },
                                        { 10, 23, 80, 176 },
-#if CONFIG_ALT_INTRA
                                        { 10, 32, 16, 64 },
 #if CONFIG_SMOOTH_HV
                                        { 10, 32, 16, 64 },
                                        { 10, 32, 16, 64 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 10, 32, 16, 64 },
                                    },
                                },
@@ -2364,13 +2331,11 @@
                                        { 128 },
                                        { 128 },
                                        { 128 },
-#if CONFIG_ALT_INTRA
                                        { 128 },
 #if CONFIG_SMOOTH_HV
                                        { 128 },
                                        { 128 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 128 },
                                    },
                                    {
@@ -2383,13 +2348,11 @@
                                        { 128 },
                                        { 128 },
                                        { 128 },
-#if CONFIG_ALT_INTRA
                                        { 128 },
 #if CONFIG_SMOOTH_HV
                                        { 128 },
                                        { 128 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 128 },
                                    },
                                    {
@@ -2402,13 +2365,11 @@
                                        { 128 },
                                        { 128 },
                                        { 128 },
-#if CONFIG_ALT_INTRA
                                        { 128 },
 #if CONFIG_SMOOTH_HV
                                        { 128 },
                                        { 128 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 128 },
                                    },
                                    {
@@ -2421,13 +2382,11 @@
                                        { 128 },
                                        { 128 },
                                        { 128 },
-#if CONFIG_ALT_INTRA
                                        { 128 },
 #if CONFIG_SMOOTH_HV
                                        { 128 },
                                        { 128 },
 #endif  //  CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                        { 128 },
                                    },
                                },
@@ -2650,7 +2609,6 @@
 #endif
     };
 
-#if CONFIG_ALT_INTRA
 #if CONFIG_SMOOTH_HV
 static const aom_cdf_prob
     default_if_y_mode_cdf[BLOCK_SIZE_GROUPS][CDF_SIZE(INTRA_MODES)] = {
@@ -2839,57 +2797,6 @@
         AOM_ICDF(31868), AOM_ICDF(32234), AOM_ICDF(32768), 0 },
     };
 #endif  // CONFIG_SMOOTH_HV
-#else   // !CONFIG_ALT_INTRA
-static const aom_cdf_prob
-    default_if_y_mode_cdf[BLOCK_SIZE_GROUPS][CDF_SIZE(INTRA_MODES)] = {
-      { AOM_ICDF(8320), AOM_ICDF(11376), AOM_ICDF(12880), AOM_ICDF(19959),
-        AOM_ICDF(23072), AOM_ICDF(24067), AOM_ICDF(25461), AOM_ICDF(26917),
-        AOM_ICDF(29157), AOM_ICDF(32768), 0 },
-      { AOM_ICDF(16896), AOM_ICDF(21112), AOM_ICDF(21932), AOM_ICDF(27852),
-        AOM_ICDF(28667), AOM_ICDF(28916), AOM_ICDF(29593), AOM_ICDF(30089),
-        AOM_ICDF(30905), AOM_ICDF(32768), 0 },
-      { AOM_ICDF(22144), AOM_ICDF(25464), AOM_ICDF(26006), AOM_ICDF(30364),
-        AOM_ICDF(30583), AOM_ICDF(30655), AOM_ICDF(31183), AOM_ICDF(31400),
-        AOM_ICDF(31646), AOM_ICDF(32768), 0 },
-      { AOM_ICDF(28288), AOM_ICDF(30650), AOM_ICDF(30964), AOM_ICDF(32288),
-        AOM_ICDF(32308), AOM_ICDF(32331), AOM_ICDF(32495), AOM_ICDF(32586),
-        AOM_ICDF(32607), AOM_ICDF(32768), 0 },
-    };
-
-static const aom_cdf_prob
-    default_uv_mode_cdf[INTRA_MODES][CDF_SIZE(UV_INTRA_MODES)] = {
-      { AOM_ICDF(15360), AOM_ICDF(15836), AOM_ICDF(20863), AOM_ICDF(27513),
-        AOM_ICDF(28269), AOM_ICDF(29048), AOM_ICDF(29455), AOM_ICDF(30154),
-        AOM_ICDF(31206), AOM_ICDF(32768), 0 },
-      { AOM_ICDF(6144), AOM_ICDF(7392), AOM_ICDF(22657), AOM_ICDF(25981),
-        AOM_ICDF(26965), AOM_ICDF(28779), AOM_ICDF(29309), AOM_ICDF(30890),
-        AOM_ICDF(31763), AOM_ICDF(32768), 0 },
-      { AOM_ICDF(8576), AOM_ICDF(9143), AOM_ICDF(11450), AOM_ICDF(27575),
-        AOM_ICDF(28108), AOM_ICDF(28438), AOM_ICDF(28658), AOM_ICDF(28995),
-        AOM_ICDF(30410), AOM_ICDF(32768), 0 },
-      { AOM_ICDF(12416), AOM_ICDF(12814), AOM_ICDF(16244), AOM_ICDF(22057),
-        AOM_ICDF(23492), AOM_ICDF(24700), AOM_ICDF(26213), AOM_ICDF(27954),
-        AOM_ICDF(29778), AOM_ICDF(32768), 0 },
-      { AOM_ICDF(10624), AOM_ICDF(11057), AOM_ICDF(14619), AOM_ICDF(19415),
-        AOM_ICDF(23134), AOM_ICDF(25679), AOM_ICDF(26399), AOM_ICDF(27618),
-        AOM_ICDF(30676), AOM_ICDF(32768), 0 },
-      { AOM_ICDF(10240), AOM_ICDF(10680), AOM_ICDF(15684), AOM_ICDF(19118),
-        AOM_ICDF(21856), AOM_ICDF(27563), AOM_ICDF(28234), AOM_ICDF(29332),
-        AOM_ICDF(31278), AOM_ICDF(32768), 0 },
-      { AOM_ICDF(11008), AOM_ICDF(11433), AOM_ICDF(14100), AOM_ICDF(22522),
-        AOM_ICDF(24365), AOM_ICDF(25330), AOM_ICDF(25737), AOM_ICDF(26341),
-        AOM_ICDF(30433), AOM_ICDF(32768), 0 },
-      { AOM_ICDF(10880), AOM_ICDF(11308), AOM_ICDF(13991), AOM_ICDF(23645),
-        AOM_ICDF(24679), AOM_ICDF(25433), AOM_ICDF(25977), AOM_ICDF(26746),
-        AOM_ICDF(28463), AOM_ICDF(32768), 0 },
-      { AOM_ICDF(9856), AOM_ICDF(10483), AOM_ICDF(16054), AOM_ICDF(19959),
-        AOM_ICDF(21708), AOM_ICDF(23628), AOM_ICDF(24949), AOM_ICDF(28797),
-        AOM_ICDF(30658), AOM_ICDF(32768), 0 },
-      { AOM_ICDF(12928), AOM_ICDF(14556), AOM_ICDF(22168), AOM_ICDF(27789),
-        AOM_ICDF(28543), AOM_ICDF(29663), AOM_ICDF(29893), AOM_ICDF(30645),
-        AOM_ICDF(31682), AOM_ICDF(32768), 0 },
-    };
-#endif  // CONFIG_ALT_INTRA
 
 #if CONFIG_EXT_PARTITION_TYPES
 static const aom_cdf_prob
@@ -3006,13 +2913,11 @@
               { 0 },
               { 0 },
               { 0 },
-#if CONFIG_ALT_INTRA
               { 0 },
 #if CONFIG_SMOOTH_HV
               { 0 },
               { 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { 0 },
           },
           {
@@ -3025,13 +2930,11 @@
               { 0 },
               { 0 },
               { 0 },
-#if CONFIG_ALT_INTRA
               { 0 },
 #if CONFIG_SMOOTH_HV
               { 0 },
               { 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { 0 },
           },
           {
@@ -3044,13 +2947,11 @@
               { 0 },
               { 0 },
               { 0 },
-#if CONFIG_ALT_INTRA
               { 0 },
 #if CONFIG_SMOOTH_HV
               { 0 },
               { 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { 0 },
           },
           {
@@ -3063,13 +2964,11 @@
               { 0 },
               { 0 },
               { 0 },
-#if CONFIG_ALT_INTRA
               { 0 },
 #if CONFIG_SMOOTH_HV
               { 0 },
               { 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { 0 },
           },
       },
@@ -3095,7 +2994,6 @@
                 AOM_ICDF(15528), AOM_ICDF(27380), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(4109), AOM_ICDF(5900), AOM_ICDF(7691),
                 AOM_ICDF(15528), AOM_ICDF(27380), AOM_ICDF(32768), 0 },
-#if CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(8660),
                 AOM_ICDF(10167), AOM_ICDF(15817), AOM_ICDF(32768), 0 },
 #if CONFIG_SMOOTH_HV
@@ -3104,7 +3002,6 @@
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(8660),
                 AOM_ICDF(10167), AOM_ICDF(15817), AOM_ICDF(32768), 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(8660),
                 AOM_ICDF(10167), AOM_ICDF(15817), AOM_ICDF(32768), 0 },
           },
@@ -3129,7 +3026,6 @@
                 AOM_ICDF(15528), AOM_ICDF(27380), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(4109), AOM_ICDF(5900), AOM_ICDF(7691),
                 AOM_ICDF(15528), AOM_ICDF(27380), AOM_ICDF(32768), 0 },
-#if CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(8660),
                 AOM_ICDF(10167), AOM_ICDF(15817), AOM_ICDF(32768), 0 },
 #if CONFIG_SMOOTH_HV
@@ -3138,7 +3034,6 @@
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(8660),
                 AOM_ICDF(10167), AOM_ICDF(15817), AOM_ICDF(32768), 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(8660),
                 AOM_ICDF(10167), AOM_ICDF(15817), AOM_ICDF(32768), 0 },
           },
@@ -3163,7 +3058,6 @@
                 AOM_ICDF(15528), AOM_ICDF(27380), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(4109), AOM_ICDF(5900), AOM_ICDF(7691),
                 AOM_ICDF(15528), AOM_ICDF(27380), AOM_ICDF(32768), 0 },
-#if CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(8660),
                 AOM_ICDF(10167), AOM_ICDF(15817), AOM_ICDF(32768), 0 },
 #if CONFIG_SMOOTH_HV
@@ -3172,7 +3066,6 @@
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(8660),
                 AOM_ICDF(10167), AOM_ICDF(15817), AOM_ICDF(32768), 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(8660),
                 AOM_ICDF(10167), AOM_ICDF(15817), AOM_ICDF(32768), 0 },
           },
@@ -3197,7 +3090,6 @@
                 AOM_ICDF(15528), AOM_ICDF(27380), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(4109), AOM_ICDF(5900), AOM_ICDF(7691),
                 AOM_ICDF(15528), AOM_ICDF(27380), AOM_ICDF(32768), 0 },
-#if CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(8660),
                 AOM_ICDF(10167), AOM_ICDF(15817), AOM_ICDF(32768), 0 },
 #if CONFIG_SMOOTH_HV
@@ -3206,7 +3098,6 @@
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(8660),
                 AOM_ICDF(10167), AOM_ICDF(15817), AOM_ICDF(32768), 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(8660),
                 AOM_ICDF(10167), AOM_ICDF(15817), AOM_ICDF(32768), 0 },
           },
@@ -3231,7 +3122,6 @@
                 AOM_ICDF(26611), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(4109), AOM_ICDF(13065),
                 AOM_ICDF(26611), AOM_ICDF(32768), 0 },
-#if CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(13396),
                 AOM_ICDF(32768), 0 },
 #if CONFIG_SMOOTH_HV
@@ -3240,7 +3130,6 @@
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(13396),
                 AOM_ICDF(32768), 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(13396),
                 AOM_ICDF(32768), 0 },
           },
@@ -3263,7 +3152,6 @@
                 AOM_ICDF(26611), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(4109), AOM_ICDF(13065),
                 AOM_ICDF(26611), AOM_ICDF(32768), 0 },
-#if CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(13396),
                 AOM_ICDF(32768), 0 },
 #if CONFIG_SMOOTH_HV
@@ -3272,7 +3160,6 @@
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(13396),
                 AOM_ICDF(32768), 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(13396),
                 AOM_ICDF(32768), 0 },
           },
@@ -3295,7 +3182,6 @@
                 AOM_ICDF(26611), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(4109), AOM_ICDF(13065),
                 AOM_ICDF(26611), AOM_ICDF(32768), 0 },
-#if CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(13396),
                 AOM_ICDF(32768), 0 },
 #if CONFIG_SMOOTH_HV
@@ -3304,7 +3190,6 @@
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(13396),
                 AOM_ICDF(32768), 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(13396),
                 AOM_ICDF(32768), 0 },
           },
@@ -3327,7 +3212,6 @@
                 AOM_ICDF(26611), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(4109), AOM_ICDF(13065),
                 AOM_ICDF(26611), AOM_ICDF(32768), 0 },
-#if CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(13396),
                 AOM_ICDF(32768), 0 },
 #if CONFIG_SMOOTH_HV
@@ -3336,7 +3220,6 @@
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(13396),
                 AOM_ICDF(32768), 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(5216), AOM_ICDF(6938), AOM_ICDF(13396),
                 AOM_ICDF(32768), 0 },
           },
@@ -3353,13 +3236,11 @@
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
-#if CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
 #if CONFIG_SMOOTH_HV
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
           },
           {
@@ -3372,13 +3253,11 @@
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
-#if CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
 #if CONFIG_SMOOTH_HV
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
           },
           {
@@ -3391,13 +3270,11 @@
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
-#if CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
 #if CONFIG_SMOOTH_HV
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
           },
           {
@@ -3410,13 +3287,11 @@
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
-#if CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
 #if CONFIG_SMOOTH_HV
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               { AOM_ICDF(1280), AOM_ICDF(32768), 0 },
           },
       }
@@ -3653,7 +3528,6 @@
 // CDF version of 'av1_kf_y_mode_prob'.
 const aom_cdf_prob
     av1_kf_y_mode_cdf[INTRA_MODES][INTRA_MODES][CDF_SIZE(INTRA_MODES)] = {
-#if CONFIG_ALT_INTRA
 #if CONFIG_SMOOTH_HV
       {
           { AOM_ICDF(14208), AOM_ICDF(16238), AOM_ICDF(19079), AOM_ICDF(22512),
@@ -4744,308 +4618,6 @@
             AOM_ICDF(27806), AOM_ICDF(29841), AOM_ICDF(32768), 0 },
       },
 #endif  // CONFIG_SMOOTH_HV
-#else   // CONFIG_ALT_INTRA
-      { { AOM_ICDF(17536), AOM_ICDF(19321), AOM_ICDF(21527), AOM_ICDF(25360),
-          AOM_ICDF(27516), AOM_ICDF(28026), AOM_ICDF(29323), AOM_ICDF(30023),
-          AOM_ICDF(30999), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(11776), AOM_ICDF(15466), AOM_ICDF(22360), AOM_ICDF(24865),
-          AOM_ICDF(26991), AOM_ICDF(27889), AOM_ICDF(29299), AOM_ICDF(30519),
-          AOM_ICDF(31398), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(9344), AOM_ICDF(12272), AOM_ICDF(13793), AOM_ICDF(25813),
-          AOM_ICDF(27359), AOM_ICDF(27654), AOM_ICDF(28573), AOM_ICDF(29130),
-          AOM_ICDF(30551), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(11648), AOM_ICDF(14123), AOM_ICDF(16454), AOM_ICDF(19948),
-          AOM_ICDF(22780), AOM_ICDF(23846), AOM_ICDF(27087), AOM_ICDF(28995),
-          AOM_ICDF(30380), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(9216), AOM_ICDF(12436), AOM_ICDF(15295), AOM_ICDF(17996),
-          AOM_ICDF(24006), AOM_ICDF(25465), AOM_ICDF(27405), AOM_ICDF(28725),
-          AOM_ICDF(30383), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(9344), AOM_ICDF(12181), AOM_ICDF(14433), AOM_ICDF(16634),
-          AOM_ICDF(20355), AOM_ICDF(24317), AOM_ICDF(26133), AOM_ICDF(29295),
-          AOM_ICDF(31344), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(8576), AOM_ICDF(10750), AOM_ICDF(12556), AOM_ICDF(17996),
-          AOM_ICDF(22315), AOM_ICDF(23609), AOM_ICDF(25040), AOM_ICDF(26157),
-          AOM_ICDF(30573), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(11008), AOM_ICDF(13303), AOM_ICDF(15432), AOM_ICDF(20646),
-          AOM_ICDF(23506), AOM_ICDF(24100), AOM_ICDF(25624), AOM_ICDF(26824),
-          AOM_ICDF(28055), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(9472), AOM_ICDF(12384), AOM_ICDF(14534), AOM_ICDF(17094),
-          AOM_ICDF(20257), AOM_ICDF(22155), AOM_ICDF(24767), AOM_ICDF(28955),
-          AOM_ICDF(30474), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7552), AOM_ICDF(14152), AOM_ICDF(17352), AOM_ICDF(22654),
-          AOM_ICDF(25123), AOM_ICDF(25783), AOM_ICDF(27911), AOM_ICDF(29182),
-          AOM_ICDF(30849), AOM_ICDF(32768), 0 } },
-      { { AOM_ICDF(8064), AOM_ICDF(11538), AOM_ICDF(21987), AOM_ICDF(24941),
-          AOM_ICDF(26913), AOM_ICDF(28136), AOM_ICDF(29222), AOM_ICDF(30469),
-          AOM_ICDF(31331), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5504), AOM_ICDF(10403), AOM_ICDF(25080), AOM_ICDF(26762),
-          AOM_ICDF(27933), AOM_ICDF(29104), AOM_ICDF(30092), AOM_ICDF(31576),
-          AOM_ICDF(32004), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5632), AOM_ICDF(8706), AOM_ICDF(15097), AOM_ICDF(23714),
-          AOM_ICDF(25344), AOM_ICDF(26072), AOM_ICDF(27380), AOM_ICDF(28580),
-          AOM_ICDF(29840), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7424), AOM_ICDF(11186), AOM_ICDF(17593), AOM_ICDF(20154),
-          AOM_ICDF(22974), AOM_ICDF(24351), AOM_ICDF(26916), AOM_ICDF(29956),
-          AOM_ICDF(30967), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5888), AOM_ICDF(10193), AOM_ICDF(16895), AOM_ICDF(19031),
-          AOM_ICDF(23735), AOM_ICDF(25576), AOM_ICDF(27514), AOM_ICDF(29813),
-          AOM_ICDF(30471), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(4864), AOM_ICDF(8352), AOM_ICDF(16459), AOM_ICDF(18062),
-          AOM_ICDF(21263), AOM_ICDF(25378), AOM_ICDF(26937), AOM_ICDF(30376),
-          AOM_ICDF(31619), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(4992), AOM_ICDF(7922), AOM_ICDF(13842), AOM_ICDF(18004),
-          AOM_ICDF(21779), AOM_ICDF(23527), AOM_ICDF(25115), AOM_ICDF(27357),
-          AOM_ICDF(30232), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6656), AOM_ICDF(9716), AOM_ICDF(16379), AOM_ICDF(20053),
-          AOM_ICDF(22487), AOM_ICDF(23613), AOM_ICDF(25437), AOM_ICDF(27270),
-          AOM_ICDF(28516), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6016), AOM_ICDF(9674), AOM_ICDF(16891), AOM_ICDF(18684),
-          AOM_ICDF(21147), AOM_ICDF(23093), AOM_ICDF(25512), AOM_ICDF(30132),
-          AOM_ICDF(30894), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(4608), AOM_ICDF(11318), AOM_ICDF(21038), AOM_ICDF(23650),
-          AOM_ICDF(25303), AOM_ICDF(26262), AOM_ICDF(28295), AOM_ICDF(30479),
-          AOM_ICDF(31212), AOM_ICDF(32768), 0 } },
-      { { AOM_ICDF(10496), AOM_ICDF(12758), AOM_ICDF(14790), AOM_ICDF(24547),
-          AOM_ICDF(26342), AOM_ICDF(26799), AOM_ICDF(27825), AOM_ICDF(28443),
-          AOM_ICDF(30217), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7040), AOM_ICDF(11462), AOM_ICDF(17121), AOM_ICDF(24215),
-          AOM_ICDF(26504), AOM_ICDF(27267), AOM_ICDF(28492), AOM_ICDF(29444),
-          AOM_ICDF(30846), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5376), AOM_ICDF(8158), AOM_ICDF(9215), AOM_ICDF(26451),
-          AOM_ICDF(27407), AOM_ICDF(27524), AOM_ICDF(27995), AOM_ICDF(28275),
-          AOM_ICDF(29767), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(8704), AOM_ICDF(12652), AOM_ICDF(14145), AOM_ICDF(20101),
-          AOM_ICDF(22879), AOM_ICDF(23675), AOM_ICDF(25629), AOM_ICDF(27079),
-          AOM_ICDF(28923), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7424), AOM_ICDF(12374), AOM_ICDF(14366), AOM_ICDF(18855),
-          AOM_ICDF(23842), AOM_ICDF(24358), AOM_ICDF(25639), AOM_ICDF(27087),
-          AOM_ICDF(29706), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6400), AOM_ICDF(10005), AOM_ICDF(12939), AOM_ICDF(17753),
-          AOM_ICDF(22206), AOM_ICDF(24790), AOM_ICDF(26785), AOM_ICDF(28164),
-          AOM_ICDF(30520), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5632), AOM_ICDF(8176), AOM_ICDF(9713), AOM_ICDF(19053),
-          AOM_ICDF(22343), AOM_ICDF(23222), AOM_ICDF(24453), AOM_ICDF(25070),
-          AOM_ICDF(29761), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7040), AOM_ICDF(9754), AOM_ICDF(10833), AOM_ICDF(21229),
-          AOM_ICDF(23540), AOM_ICDF(23943), AOM_ICDF(24839), AOM_ICDF(25675),
-          AOM_ICDF(27033), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6784), AOM_ICDF(11758), AOM_ICDF(13481), AOM_ICDF(17236),
-          AOM_ICDF(20210), AOM_ICDF(21768), AOM_ICDF(24303), AOM_ICDF(26948),
-          AOM_ICDF(28676), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(4864), AOM_ICDF(12712), AOM_ICDF(14201), AOM_ICDF(23863),
-          AOM_ICDF(25952), AOM_ICDF(26386), AOM_ICDF(27632), AOM_ICDF(28635),
-          AOM_ICDF(30362), AOM_ICDF(32768), 0 } },
-      { { AOM_ICDF(13184), AOM_ICDF(15173), AOM_ICDF(17647), AOM_ICDF(21576),
-          AOM_ICDF(24474), AOM_ICDF(25267), AOM_ICDF(27699), AOM_ICDF(29283),
-          AOM_ICDF(30549), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7552), AOM_ICDF(11295), AOM_ICDF(18257), AOM_ICDF(20811),
-          AOM_ICDF(23213), AOM_ICDF(24606), AOM_ICDF(27731), AOM_ICDF(30407),
-          AOM_ICDF(31237), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7936), AOM_ICDF(10846), AOM_ICDF(12816), AOM_ICDF(22436),
-          AOM_ICDF(24614), AOM_ICDF(25130), AOM_ICDF(26890), AOM_ICDF(28199),
-          AOM_ICDF(29091), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(8576), AOM_ICDF(11411), AOM_ICDF(13830), AOM_ICDF(15918),
-          AOM_ICDF(18996), AOM_ICDF(20044), AOM_ICDF(25114), AOM_ICDF(27835),
-          AOM_ICDF(28972), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7680), AOM_ICDF(10816), AOM_ICDF(13646), AOM_ICDF(15966),
-          AOM_ICDF(21162), AOM_ICDF(22012), AOM_ICDF(24701), AOM_ICDF(27506),
-          AOM_ICDF(29644), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6784), AOM_ICDF(9423), AOM_ICDF(12524), AOM_ICDF(14773),
-          AOM_ICDF(19447), AOM_ICDF(22804), AOM_ICDF(26073), AOM_ICDF(29211),
-          AOM_ICDF(30642), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6784), AOM_ICDF(8916), AOM_ICDF(11059), AOM_ICDF(15861),
-          AOM_ICDF(21174), AOM_ICDF(22338), AOM_ICDF(24620), AOM_ICDF(27071),
-          AOM_ICDF(30899), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(9856), AOM_ICDF(11557), AOM_ICDF(13960), AOM_ICDF(18525),
-          AOM_ICDF(21788), AOM_ICDF(22189), AOM_ICDF(24462), AOM_ICDF(26603),
-          AOM_ICDF(27470), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7808), AOM_ICDF(10636), AOM_ICDF(13143), AOM_ICDF(15844),
-          AOM_ICDF(18698), AOM_ICDF(20272), AOM_ICDF(24323), AOM_ICDF(30096),
-          AOM_ICDF(31787), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6016), AOM_ICDF(10928), AOM_ICDF(14596), AOM_ICDF(18926),
-          AOM_ICDF(21586), AOM_ICDF(22688), AOM_ICDF(26626), AOM_ICDF(29001),
-          AOM_ICDF(30399), AOM_ICDF(32768), 0 } },
-      { { AOM_ICDF(8832), AOM_ICDF(10983), AOM_ICDF(13451), AOM_ICDF(16582),
-          AOM_ICDF(21656), AOM_ICDF(23109), AOM_ICDF(24845), AOM_ICDF(26207),
-          AOM_ICDF(28796), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6784), AOM_ICDF(10844), AOM_ICDF(15554), AOM_ICDF(18073),
-          AOM_ICDF(22954), AOM_ICDF(24901), AOM_ICDF(26776), AOM_ICDF(28649),
-          AOM_ICDF(30419), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5120), AOM_ICDF(8252), AOM_ICDF(10072), AOM_ICDF(20108),
-          AOM_ICDF(23535), AOM_ICDF(24346), AOM_ICDF(25761), AOM_ICDF(26418),
-          AOM_ICDF(28675), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7680), AOM_ICDF(11012), AOM_ICDF(12627), AOM_ICDF(14595),
-          AOM_ICDF(19462), AOM_ICDF(20888), AOM_ICDF(23348), AOM_ICDF(25703),
-          AOM_ICDF(28159), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6656), AOM_ICDF(9818), AOM_ICDF(11790), AOM_ICDF(13813),
-          AOM_ICDF(22731), AOM_ICDF(24737), AOM_ICDF(26557), AOM_ICDF(28061),
-          AOM_ICDF(29697), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5632), AOM_ICDF(8918), AOM_ICDF(11620), AOM_ICDF(13802),
-          AOM_ICDF(19950), AOM_ICDF(23764), AOM_ICDF(25734), AOM_ICDF(28537),
-          AOM_ICDF(31809), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(4480), AOM_ICDF(6580), AOM_ICDF(7808), AOM_ICDF(12281),
-          AOM_ICDF(19375), AOM_ICDF(20970), AOM_ICDF(22860), AOM_ICDF(24602),
-          AOM_ICDF(29929), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7040), AOM_ICDF(9553), AOM_ICDF(11457), AOM_ICDF(15102),
-          AOM_ICDF(20291), AOM_ICDF(21280), AOM_ICDF(22985), AOM_ICDF(24475),
-          AOM_ICDF(26613), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6528), AOM_ICDF(10423), AOM_ICDF(12605), AOM_ICDF(14621),
-          AOM_ICDF(19031), AOM_ICDF(21505), AOM_ICDF(24585), AOM_ICDF(27558),
-          AOM_ICDF(29532), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6016), AOM_ICDF(11659), AOM_ICDF(14463), AOM_ICDF(18867),
-          AOM_ICDF(23653), AOM_ICDF(24903), AOM_ICDF(27115), AOM_ICDF(29389),
-          AOM_ICDF(31382), AOM_ICDF(32768), 0 } },
-      { { AOM_ICDF(8192), AOM_ICDF(10016), AOM_ICDF(13304), AOM_ICDF(16362),
-          AOM_ICDF(21107), AOM_ICDF(25165), AOM_ICDF(26620), AOM_ICDF(28901),
-          AOM_ICDF(30910), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5888), AOM_ICDF(8723), AOM_ICDF(16237), AOM_ICDF(18318),
-          AOM_ICDF(22002), AOM_ICDF(25923), AOM_ICDF(27394), AOM_ICDF(29934),
-          AOM_ICDF(31428), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(4608), AOM_ICDF(7138), AOM_ICDF(9841), AOM_ICDF(18442),
-          AOM_ICDF(22447), AOM_ICDF(24618), AOM_ICDF(26337), AOM_ICDF(27945),
-          AOM_ICDF(30168), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6784), AOM_ICDF(8916), AOM_ICDF(12270), AOM_ICDF(14851),
-          AOM_ICDF(19886), AOM_ICDF(22759), AOM_ICDF(25105), AOM_ICDF(28368),
-          AOM_ICDF(29760), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5120), AOM_ICDF(7928), AOM_ICDF(11324), AOM_ICDF(13340),
-          AOM_ICDF(21205), AOM_ICDF(24224), AOM_ICDF(25926), AOM_ICDF(28518),
-          AOM_ICDF(30560), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(4480), AOM_ICDF(6580), AOM_ICDF(10058), AOM_ICDF(11237),
-          AOM_ICDF(16807), AOM_ICDF(25937), AOM_ICDF(27218), AOM_ICDF(30015),
-          AOM_ICDF(31348), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(4608), AOM_ICDF(6808), AOM_ICDF(9445), AOM_ICDF(12446),
-          AOM_ICDF(18461), AOM_ICDF(21835), AOM_ICDF(23244), AOM_ICDF(26109),
-          AOM_ICDF(30115), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5760), AOM_ICDF(7659), AOM_ICDF(10798), AOM_ICDF(14720),
-          AOM_ICDF(19157), AOM_ICDF(21955), AOM_ICDF(23645), AOM_ICDF(26460),
-          AOM_ICDF(28702), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5760), AOM_ICDF(8503), AOM_ICDF(11157), AOM_ICDF(13071),
-          AOM_ICDF(17594), AOM_ICDF(22047), AOM_ICDF(24099), AOM_ICDF(29077),
-          AOM_ICDF(30850), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(4864), AOM_ICDF(9660), AOM_ICDF(14264), AOM_ICDF(17105),
-          AOM_ICDF(21528), AOM_ICDF(24094), AOM_ICDF(26025), AOM_ICDF(28580),
-          AOM_ICDF(30559), AOM_ICDF(32768), 0 } },
-      { { AOM_ICDF(9600), AOM_ICDF(11139), AOM_ICDF(12998), AOM_ICDF(18660),
-          AOM_ICDF(22158), AOM_ICDF(23501), AOM_ICDF(24659), AOM_ICDF(25736),
-          AOM_ICDF(30296), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7168), AOM_ICDF(11068), AOM_ICDF(15984), AOM_ICDF(19969),
-          AOM_ICDF(23169), AOM_ICDF(24704), AOM_ICDF(26216), AOM_ICDF(27572),
-          AOM_ICDF(31368), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(4480), AOM_ICDF(6801), AOM_ICDF(8018), AOM_ICDF(20908),
-          AOM_ICDF(23071), AOM_ICDF(23583), AOM_ICDF(24301), AOM_ICDF(25062),
-          AOM_ICDF(29427), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7168), AOM_ICDF(10068), AOM_ICDF(11753), AOM_ICDF(15843),
-          AOM_ICDF(19742), AOM_ICDF(21358), AOM_ICDF(23809), AOM_ICDF(26189),
-          AOM_ICDF(29067), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6016), AOM_ICDF(9047), AOM_ICDF(10622), AOM_ICDF(13931),
-          AOM_ICDF(22462), AOM_ICDF(23858), AOM_ICDF(25911), AOM_ICDF(27277),
-          AOM_ICDF(29722), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5888), AOM_ICDF(7568), AOM_ICDF(9931), AOM_ICDF(13533),
-          AOM_ICDF(18431), AOM_ICDF(22063), AOM_ICDF(23777), AOM_ICDF(26025),
-          AOM_ICDF(30555), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(4352), AOM_ICDF(6239), AOM_ICDF(7379), AOM_ICDF(13739),
-          AOM_ICDF(16917), AOM_ICDF(18090), AOM_ICDF(18835), AOM_ICDF(19651),
-          AOM_ICDF(30360), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6528), AOM_ICDF(8988), AOM_ICDF(10288), AOM_ICDF(15534),
-          AOM_ICDF(19495), AOM_ICDF(20386), AOM_ICDF(21934), AOM_ICDF(23034),
-          AOM_ICDF(26988), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7040), AOM_ICDF(10055), AOM_ICDF(11652), AOM_ICDF(14757),
-          AOM_ICDF(19622), AOM_ICDF(21715), AOM_ICDF(23615), AOM_ICDF(26761),
-          AOM_ICDF(29483), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(4736), AOM_ICDF(10102), AOM_ICDF(12315), AOM_ICDF(19078),
-          AOM_ICDF(21348), AOM_ICDF(22621), AOM_ICDF(24246), AOM_ICDF(26044),
-          AOM_ICDF(29931), AOM_ICDF(32768), 0 } },
-      { { AOM_ICDF(10496), AOM_ICDF(12410), AOM_ICDF(14955), AOM_ICDF(19891),
-          AOM_ICDF(23137), AOM_ICDF(23792), AOM_ICDF(25159), AOM_ICDF(26378),
-          AOM_ICDF(28125), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7936), AOM_ICDF(12204), AOM_ICDF(17104), AOM_ICDF(20191),
-          AOM_ICDF(23468), AOM_ICDF(24630), AOM_ICDF(26156), AOM_ICDF(27628),
-          AOM_ICDF(28913), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6016), AOM_ICDF(8629), AOM_ICDF(10232), AOM_ICDF(23591),
-          AOM_ICDF(25349), AOM_ICDF(25637), AOM_ICDF(26306), AOM_ICDF(27063),
-          AOM_ICDF(28980), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(8704), AOM_ICDF(12088), AOM_ICDF(13461), AOM_ICDF(16646),
-          AOM_ICDF(20516), AOM_ICDF(21455), AOM_ICDF(24062), AOM_ICDF(26579),
-          AOM_ICDF(28368), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7296), AOM_ICDF(11177), AOM_ICDF(13117), AOM_ICDF(16196),
-          AOM_ICDF(23378), AOM_ICDF(24708), AOM_ICDF(26440), AOM_ICDF(27997),
-          AOM_ICDF(29078), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6272), AOM_ICDF(9377), AOM_ICDF(12575), AOM_ICDF(15616),
-          AOM_ICDF(20919), AOM_ICDF(23697), AOM_ICDF(26603), AOM_ICDF(27566),
-          AOM_ICDF(29903), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6528), AOM_ICDF(9091), AOM_ICDF(10478), AOM_ICDF(16445),
-          AOM_ICDF(21081), AOM_ICDF(22320), AOM_ICDF(23871), AOM_ICDF(25087),
-          AOM_ICDF(29258), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(8704), AOM_ICDF(11148), AOM_ICDF(12499), AOM_ICDF(17340),
-          AOM_ICDF(20656), AOM_ICDF(21288), AOM_ICDF(22588), AOM_ICDF(23701),
-          AOM_ICDF(24693), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7552), AOM_ICDF(11394), AOM_ICDF(12980), AOM_ICDF(15562),
-          AOM_ICDF(19942), AOM_ICDF(21792), AOM_ICDF(25093), AOM_ICDF(28211),
-          AOM_ICDF(28959), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5120), AOM_ICDF(11708), AOM_ICDF(13847), AOM_ICDF(19377),
-          AOM_ICDF(22421), AOM_ICDF(23160), AOM_ICDF(25449), AOM_ICDF(27136),
-          AOM_ICDF(29182), AOM_ICDF(32768), 0 } },
-      { { AOM_ICDF(9984), AOM_ICDF(12031), AOM_ICDF(15190), AOM_ICDF(18673),
-          AOM_ICDF(21422), AOM_ICDF(22812), AOM_ICDF(25690), AOM_ICDF(29118),
-          AOM_ICDF(30458), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6144), AOM_ICDF(9680), AOM_ICDF(17436), AOM_ICDF(19610),
-          AOM_ICDF(21820), AOM_ICDF(23485), AOM_ICDF(26313), AOM_ICDF(30826),
-          AOM_ICDF(31843), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6016), AOM_ICDF(8315), AOM_ICDF(10607), AOM_ICDF(19333),
-          AOM_ICDF(21572), AOM_ICDF(22553), AOM_ICDF(25266), AOM_ICDF(27288),
-          AOM_ICDF(28551), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7168), AOM_ICDF(9668), AOM_ICDF(12646), AOM_ICDF(16257),
-          AOM_ICDF(19648), AOM_ICDF(20899), AOM_ICDF(25304), AOM_ICDF(30465),
-          AOM_ICDF(31625), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6144), AOM_ICDF(9368), AOM_ICDF(11836), AOM_ICDF(14130),
-          AOM_ICDF(19153), AOM_ICDF(21157), AOM_ICDF(24876), AOM_ICDF(28452),
-          AOM_ICDF(29396), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5504), AOM_ICDF(8486), AOM_ICDF(11996), AOM_ICDF(14412),
-          AOM_ICDF(17968), AOM_ICDF(21814), AOM_ICDF(24424), AOM_ICDF(30682),
-          AOM_ICDF(32059), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5376), AOM_ICDF(7195), AOM_ICDF(9592), AOM_ICDF(13331),
-          AOM_ICDF(17569), AOM_ICDF(19460), AOM_ICDF(22371), AOM_ICDF(25458),
-          AOM_ICDF(28942), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7424), AOM_ICDF(9206), AOM_ICDF(11783), AOM_ICDF(16456),
-          AOM_ICDF(19253), AOM_ICDF(20390), AOM_ICDF(23775), AOM_ICDF(27007),
-          AOM_ICDF(28425), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5888), AOM_ICDF(8303), AOM_ICDF(11361), AOM_ICDF(13440),
-          AOM_ICDF(15848), AOM_ICDF(17549), AOM_ICDF(21532), AOM_ICDF(29564),
-          AOM_ICDF(30665), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(4608), AOM_ICDF(8788), AOM_ICDF(13284), AOM_ICDF(16621),
-          AOM_ICDF(18983), AOM_ICDF(20286), AOM_ICDF(24577), AOM_ICDF(28960),
-          AOM_ICDF(30314), AOM_ICDF(32768), 0 } },
-      { { AOM_ICDF(8320), AOM_ICDF(15005), AOM_ICDF(19168), AOM_ICDF(24282),
-          AOM_ICDF(26707), AOM_ICDF(27402), AOM_ICDF(28681), AOM_ICDF(29639),
-          AOM_ICDF(30629), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5632), AOM_ICDF(13900), AOM_ICDF(22376), AOM_ICDF(24867),
-          AOM_ICDF(26804), AOM_ICDF(27734), AOM_ICDF(29130), AOM_ICDF(30722),
-          AOM_ICDF(31465), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(4992), AOM_ICDF(9115), AOM_ICDF(11055), AOM_ICDF(24893),
-          AOM_ICDF(26316), AOM_ICDF(26661), AOM_ICDF(27663), AOM_ICDF(28301),
-          AOM_ICDF(29418), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(7424), AOM_ICDF(12077), AOM_ICDF(14987), AOM_ICDF(19596),
-          AOM_ICDF(22615), AOM_ICDF(23600), AOM_ICDF(26465), AOM_ICDF(28484),
-          AOM_ICDF(29789), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6272), AOM_ICDF(11447), AOM_ICDF(14362), AOM_ICDF(18204),
-          AOM_ICDF(23418), AOM_ICDF(24715), AOM_ICDF(26697), AOM_ICDF(28547),
-          AOM_ICDF(29520), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5248), AOM_ICDF(10946), AOM_ICDF(15379), AOM_ICDF(18167),
-          AOM_ICDF(22197), AOM_ICDF(25432), AOM_ICDF(27295), AOM_ICDF(30031),
-          AOM_ICDF(30576), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5120), AOM_ICDF(9008), AOM_ICDF(11607), AOM_ICDF(18210),
-          AOM_ICDF(22327), AOM_ICDF(23427), AOM_ICDF(24887), AOM_ICDF(26580),
-          AOM_ICDF(29892), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(6656), AOM_ICDF(10124), AOM_ICDF(12689), AOM_ICDF(19922),
-          AOM_ICDF(22480), AOM_ICDF(22807), AOM_ICDF(24441), AOM_ICDF(25579),
-          AOM_ICDF(26787), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5376), AOM_ICDF(10084), AOM_ICDF(13983), AOM_ICDF(17113),
-          AOM_ICDF(19996), AOM_ICDF(21614), AOM_ICDF(24403), AOM_ICDF(28651),
-          AOM_ICDF(29938), AOM_ICDF(32768), 0 },
-        { AOM_ICDF(5504), AOM_ICDF(14131), AOM_ICDF(17989), AOM_ICDF(23324),
-          AOM_ICDF(25513), AOM_ICDF(26071), AOM_ICDF(27850), AOM_ICDF(29464),
-          AOM_ICDF(30393), AOM_ICDF(32768), 0 } },
-#endif  // CONFIG_ALT_INTRA
     };
 
 static void init_mode_probs(FRAME_CONTEXT *fc) {
diff --git a/av1/common/enums.h b/av1/common/enums.h
index b017f17..2fe5b38 100644
--- a/av1/common/enums.h
+++ b/av1/common/enums.h
@@ -411,22 +411,20 @@
 // Note: All directional predictors must be between V_PRED and D63_PRED (both
 // inclusive).
 typedef enum ATTRIBUTE_PACKED {
-  DC_PRED,    // Average of above and left pixels
-  V_PRED,     // Vertical
-  H_PRED,     // Horizontal
-  D45_PRED,   // Directional 45  deg = round(arctan(1/1) * 180/pi)
-  D135_PRED,  // Directional 135 deg = 180 - 45
-  D117_PRED,  // Directional 117 deg = 180 - 63
-  D153_PRED,  // Directional 153 deg = 180 - 27
-  D207_PRED,  // Directional 207 deg = 180 + 27
-  D63_PRED,   // Directional 63  deg = round(arctan(2/1) * 180/pi)
-#if CONFIG_ALT_INTRA
+  DC_PRED,      // Average of above and left pixels
+  V_PRED,       // Vertical
+  H_PRED,       // Horizontal
+  D45_PRED,     // Directional 45  deg = round(arctan(1/1) * 180/pi)
+  D135_PRED,    // Directional 135 deg = 180 - 45
+  D117_PRED,    // Directional 117 deg = 180 - 63
+  D153_PRED,    // Directional 153 deg = 180 - 27
+  D207_PRED,    // Directional 207 deg = 180 + 27
+  D63_PRED,     // Directional 63  deg = round(arctan(2/1) * 180/pi)
   SMOOTH_PRED,  // Combination of horizontal and vertical interpolation
 #if CONFIG_SMOOTH_HV
   SMOOTH_V_PRED,  // Vertical interpolation
   SMOOTH_H_PRED,  // Horizontal interpolation
 #endif            // CONFIG_SMOOTH_HV
-#endif            // CONFIG_ALT_INTRA
   TM_PRED,        // True-motion
   NEARESTMV,
   NEARMV,
@@ -460,22 +458,20 @@
 // TODO(ltrudeau) Do we really want to pack this?
 // TODO(ltrudeau) Do we match with PREDICTION_MODE?
 typedef enum ATTRIBUTE_PACKED {
-  UV_DC_PRED,    // Average of above and left pixels
-  UV_V_PRED,     // Vertical
-  UV_H_PRED,     // Horizontal
-  UV_D45_PRED,   // Directional 45  deg = round(arctan(1/1) * 180/pi)
-  UV_D135_PRED,  // Directional 135 deg = 180 - 45
-  UV_D117_PRED,  // Directional 117 deg = 180 - 63
-  UV_D153_PRED,  // Directional 153 deg = 180 - 27
-  UV_D207_PRED,  // Directional 207 deg = 180 + 27
-  UV_D63_PRED,   // Directional 63  deg = round(arctan(2/1) * 180/pi)
-#if CONFIG_ALT_INTRA
+  UV_DC_PRED,      // Average of above and left pixels
+  UV_V_PRED,       // Vertical
+  UV_H_PRED,       // Horizontal
+  UV_D45_PRED,     // Directional 45  deg = round(arctan(1/1) * 180/pi)
+  UV_D135_PRED,    // Directional 135 deg = 180 - 45
+  UV_D117_PRED,    // Directional 117 deg = 180 - 63
+  UV_D153_PRED,    // Directional 153 deg = 180 - 27
+  UV_D207_PRED,    // Directional 207 deg = 180 + 27
+  UV_D63_PRED,     // Directional 63  deg = round(arctan(2/1) * 180/pi)
   UV_SMOOTH_PRED,  // Combination of horizontal and vertical interpolation
 #if CONFIG_SMOOTH_HV
   UV_SMOOTH_V_PRED,  // Vertical interpolation
   UV_SMOOTH_H_PRED,  // Horizontal interpolation
 #endif               // CONFIG_SMOOTH_HV
-#endif               // CONFIG_ALT_INTRA
   UV_TM_PRED,        // True-motion
   UV_CFL_PRED,       // Chroma-from-Luma
   UV_INTRA_MODES,
@@ -508,11 +504,7 @@
   II_DC_PRED = 0,
   II_V_PRED,
   II_H_PRED,
-#if CONFIG_ALT_INTRA
   II_SMOOTH_PRED,
-#else
-  II_TM_PRED,
-#endif  // CONFIG_ALT_INTRA
   INTERINTRA_MODES
 } INTERINTRA_MODE;
 #endif
diff --git a/av1/common/mvref_common.h b/av1/common/mvref_common.h
index 8caa745..906927d 100644
--- a/av1/common/mvref_common.h
+++ b/av1/common/mvref_common.h
@@ -51,13 +51,11 @@
   9,  // D153_PRED
   9,  // D207_PRED
   9,  // D63_PRED
-#if CONFIG_ALT_INTRA
   9,  // SMOOTH_PRED
 #if CONFIG_SMOOTH_HV
   9,    // SMOOTH_V_PRED
   9,    // SMOOTH_H_PRED
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
   9,    // TM_PRED
   0,    // NEARESTMV
   0,    // NEARMV
diff --git a/av1/common/reconinter.c b/av1/common/reconinter.c
index 308c669..6d07164 100644
--- a/av1/common/reconinter.c
+++ b/av1/common/reconinter.c
@@ -2938,7 +2938,6 @@
       }
       break;
 
-#if CONFIG_ALT_INTRA
     case II_SMOOTH_PRED:
       for (i = 0; i < bh; ++i) {
         for (j = 0; j < bw; ++j) {
@@ -2949,11 +2948,7 @@
         }
       }
       break;
-#endif
 
-#if !CONFIG_ALT_INTRA
-    case II_TM_PRED:
-#endif
     case II_DC_PRED:
     default:
       for (i = 0; i < bh; ++i) {
@@ -3017,7 +3012,6 @@
       }
       break;
 
-#if CONFIG_ALT_INTRA
     case II_SMOOTH_PRED:
       for (i = 0; i < bh; ++i) {
         for (j = 0; j < bw; ++j) {
@@ -3028,11 +3022,7 @@
         }
       }
       break;
-#endif
 
-#if !CONFIG_ALT_INTRA
-    case II_TM_PRED:
-#endif
     case II_DC_PRED:
     default:
       for (i = 0; i < bh; ++i) {
diff --git a/av1/common/reconintra.c b/av1/common/reconintra.c
index 0357b32..0f21bee 100644
--- a/av1/common/reconintra.c
+++ b/av1/common/reconintra.c
@@ -59,13 +59,11 @@
   NEED_LEFT | NEED_ABOVE | NEED_ABOVELEFT,  // D153
   NEED_LEFT | NEED_BOTTOMLEFT,              // D207
   NEED_ABOVE | NEED_ABOVERIGHT,             // D63
-#if CONFIG_ALT_INTRA
-  NEED_LEFT | NEED_ABOVE,  // SMOOTH
+  NEED_LEFT | NEED_ABOVE,                   // SMOOTH
 #if CONFIG_SMOOTH_HV
   NEED_LEFT | NEED_ABOVE,                   // SMOOTH_V
   NEED_LEFT | NEED_ABOVE,                   // SMOOTH_H
 #endif                                      // CONFIG_SMOOTH_HV
-#endif                                      // CONFIG_ALT_INTRA
   NEED_LEFT | NEED_ABOVE | NEED_ABOVELEFT,  // TM
 };
 
@@ -713,16 +711,12 @@
   INIT_ALL_SIZES(pred[D135_PRED], d135);
   INIT_ALL_SIZES(pred[D153_PRED], d153);
 
-#if CONFIG_ALT_INTRA
   INIT_ALL_SIZES(pred[TM_PRED], paeth);
   INIT_ALL_SIZES(pred[SMOOTH_PRED], smooth);
 #if CONFIG_SMOOTH_HV
   INIT_ALL_SIZES(pred[SMOOTH_V_PRED], smooth_v);
   INIT_ALL_SIZES(pred[SMOOTH_H_PRED], smooth_h);
 #endif  // CONFIG_SMOOTH_HV
-#else
-  INIT_ALL_SIZES(pred[TM_PRED], tm);
-#endif  // CONFIG_ALT_INTRA
 
   INIT_ALL_SIZES(dc_pred[0][0], dc_128);
   INIT_ALL_SIZES(dc_pred[0][1], dc_top);
@@ -739,16 +733,12 @@
   INIT_ALL_SIZES(pred_high[D135_PRED], highbd_d135);
   INIT_ALL_SIZES(pred_high[D153_PRED], highbd_d153);
 
-#if CONFIG_ALT_INTRA
   INIT_ALL_SIZES(pred_high[TM_PRED], highbd_paeth);
   INIT_ALL_SIZES(pred_high[SMOOTH_PRED], highbd_smooth);
 #if CONFIG_SMOOTH_HV
   INIT_ALL_SIZES(pred_high[SMOOTH_V_PRED], highbd_smooth_v);
   INIT_ALL_SIZES(pred_high[SMOOTH_H_PRED], highbd_smooth_h);
 #endif  // CONFIG_SMOOTH_HV
-#else
-  INIT_ALL_SIZES(pred_high[TM_PRED], highbd_tm);
-#endif  // CONFIG_ALT_INTRA
 
   INIT_ALL_SIZES(dc_pred_high[0][0], highbd_dc_128);
   INIT_ALL_SIZES(dc_pred_high[0][1], highbd_dc_top);
diff --git a/av1/common/reconintra.h b/av1/common/reconintra.h
index 67e5706..619a241 100644
--- a/av1/common/reconintra.h
+++ b/av1/common/reconintra.h
@@ -44,28 +44,13 @@
 #if CONFIG_EXT_INTER && CONFIG_INTERINTRA
 // Mapping of interintra to intra mode for use in the intra component
 static const PREDICTION_MODE interintra_to_intra_mode[INTERINTRA_MODES] = {
-  DC_PRED, V_PRED, H_PRED,
-#if CONFIG_ALT_INTRA
-  SMOOTH_PRED
-#else
-  TM_PRED
-#endif
+  DC_PRED, V_PRED, H_PRED, SMOOTH_PRED
 };
 
 // Mapping of intra mode to the interintra mode
 static const INTERINTRA_MODE intra_to_interintra_mode[INTRA_MODES] = {
-  II_DC_PRED,     II_V_PRED,     II_H_PRED, II_V_PRED,
-#if CONFIG_ALT_INTRA
-  II_SMOOTH_PRED,
-#else
-  II_TM_PRED,
-#endif
-  II_V_PRED,      II_H_PRED,     II_H_PRED, II_V_PRED,
-#if CONFIG_ALT_INTRA
-  II_SMOOTH_PRED, II_SMOOTH_PRED
-#else
-  II_TM_PRED
-#endif
+  II_DC_PRED, II_V_PRED, II_H_PRED, II_V_PRED,      II_SMOOTH_PRED, II_V_PRED,
+  II_H_PRED,  II_H_PRED, II_V_PRED, II_SMOOTH_PRED, II_SMOOTH_PRED
 };
 #endif  // CONFIG_EXT_INTER && CONFIG_INTERINTRA
 
diff --git a/av1/encoder/encodeframe.c b/av1/encoder/encodeframe.c
index 4237453..28130cc 100644
--- a/av1/encoder/encodeframe.c
+++ b/av1/encoder/encodeframe.c
@@ -697,13 +697,11 @@
         THR_D153_PRED /*D153_PRED*/,
         THR_D207_PRED /*D207_PRED*/,
         THR_D63_PRED /*D63_PRED*/,
-#if CONFIG_ALT_INTRA
         THR_SMOOTH, /*SMOOTH_PRED*/
 #if CONFIG_SMOOTH_HV
         THR_SMOOTH_V, /*SMOOTH_V_PRED*/
         THR_SMOOTH_H, /*SMOOTH_H_PRED*/
 #endif                // CONFIG_SMOOTH_HV
-#endif                // CONFIG_ALT_INTRA
         THR_TM /*TM_PRED*/,
       };
       ++mode_chosen_counts[kf_mode_index[mbmi->mode]];
diff --git a/av1/encoder/rd.h b/av1/encoder/rd.h
index dbafc7b..98f39bd 100644
--- a/av1/encoder/rd.h
+++ b/av1/encoder/rd.h
@@ -207,13 +207,11 @@
 
   THR_TM,
 
-#if CONFIG_ALT_INTRA
   THR_SMOOTH,
 #if CONFIG_SMOOTH_HV
   THR_SMOOTH_V,
   THR_SMOOTH_H,
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
 
 #if CONFIG_EXT_INTER
 
diff --git a/av1/encoder/rdopt.c b/av1/encoder/rdopt.c
index 7007980..dedb096 100644
--- a/av1/encoder/rdopt.c
+++ b/av1/encoder/rdopt.c
@@ -359,13 +359,11 @@
 
   { TM_PRED, { INTRA_FRAME, NONE_FRAME } },
 
-#if CONFIG_ALT_INTRA
   { SMOOTH_PRED, { INTRA_FRAME, NONE_FRAME } },
 #if CONFIG_SMOOTH_HV
   { SMOOTH_V_PRED, { INTRA_FRAME, NONE_FRAME } },
   { SMOOTH_H_PRED, { INTRA_FRAME, NONE_FRAME } },
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
 
 #if CONFIG_EXT_INTER
   { NEAR_NEARMV, { LAST_FRAME, ALTREF_FRAME } },
@@ -634,29 +632,22 @@
 };
 
 static const PREDICTION_MODE intra_rd_search_mode_order[INTRA_MODES] = {
-  DC_PRED,       H_PRED,        V_PRED,
-#if CONFIG_ALT_INTRA
-  SMOOTH_PRED,
-#endif  // CONFIG_ALT_INTRA
-  TM_PRED,
-#if CONFIG_ALT_INTRA && CONFIG_SMOOTH_HV
+  DC_PRED,       H_PRED,        V_PRED,    SMOOTH_PRED, TM_PRED,
+#if CONFIG_SMOOTH_HV
   SMOOTH_V_PRED, SMOOTH_H_PRED,
-#endif  // CONFIG_ALT_INTRA && CONFIG_SMOOTH_HV
-  D135_PRED,     D207_PRED,     D153_PRED, D63_PRED, D117_PRED, D45_PRED,
+#endif  // CONFIG_SMOOTH_HV
+  D135_PRED,     D207_PRED,     D153_PRED, D63_PRED,    D117_PRED, D45_PRED,
 };
 
 #if CONFIG_CFL
 static const UV_PREDICTION_MODE uv_rd_search_mode_order[UV_INTRA_MODES] = {
-  UV_DC_PRED,       UV_CFL_PRED,      UV_H_PRED,    UV_V_PRED,
-#if CONFIG_ALT_INTRA
-  UV_SMOOTH_PRED,
-#endif  // CONFIG_ALT_INTRA
-  UV_TM_PRED,
-#if CONFIG_ALT_INTRA && CONFIG_SMOOTH_HV
+  UV_DC_PRED,       UV_CFL_PRED,      UV_H_PRED,
+  UV_V_PRED,        UV_SMOOTH_PRED,   UV_TM_PRED,
+#if CONFIG_SMOOTH_HV
   UV_SMOOTH_V_PRED, UV_SMOOTH_H_PRED,
-#endif  // CONFIG_ALT_INTRA && CONFIG_SMOOTH_HV
-  UV_D135_PRED,     UV_D207_PRED,     UV_D153_PRED, UV_D63_PRED,
-  UV_D117_PRED,     UV_D45_PRED,
+#endif  // CONFIG_SMOOTH_HV
+  UV_D135_PRED,     UV_D207_PRED,     UV_D153_PRED,
+  UV_D63_PRED,      UV_D117_PRED,     UV_D45_PRED,
 };
 #else
 #define uv_rd_search_mode_order intra_rd_search_mode_order
@@ -4140,9 +4131,7 @@
 /* clang-format off */
 static const uint8_t mode_to_angle_bin[INTRA_MODES] = {
   0, 2, 6, 0, 4, 3, 5, 7, 1, 0,
-#if CONFIG_ALT_INTRA
   0,
-#endif  // CONFIG_ALT_INTRA
 };
 /* clang-format on */
 
diff --git a/av1/encoder/speed_features.h b/av1/encoder/speed_features.h
index ecfc310..1524c06 100644
--- a/av1/encoder/speed_features.h
+++ b/av1/encoder/speed_features.h
@@ -21,25 +21,20 @@
 enum {
   INTRA_ALL = (1 << DC_PRED) | (1 << V_PRED) | (1 << H_PRED) | (1 << D45_PRED) |
               (1 << D135_PRED) | (1 << D117_PRED) | (1 << D153_PRED) |
-              (1 << D207_PRED) | (1 << D63_PRED) |
-#if CONFIG_ALT_INTRA
-              (1 << SMOOTH_PRED) |
+              (1 << D207_PRED) | (1 << D63_PRED) | (1 << SMOOTH_PRED) |
 #if CONFIG_SMOOTH_HV
               (1 << SMOOTH_V_PRED) | (1 << SMOOTH_H_PRED) |
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
               (1 << TM_PRED),
 #if CONFIG_CFL
   UV_INTRA_ALL = (1 << UV_DC_PRED) | (1 << UV_V_PRED) | (1 << UV_H_PRED) |
                  (1 << UV_D45_PRED) | (1 << UV_D135_PRED) |
                  (1 << UV_D117_PRED) | (1 << UV_D153_PRED) |
                  (1 << UV_D207_PRED) | (1 << UV_D63_PRED) |
-#if CONFIG_ALT_INTRA
                  (1 << UV_SMOOTH_PRED) |
 #if CONFIG_SMOOTH_HV
                  (1 << UV_SMOOTH_V_PRED) | (1 << UV_SMOOTH_H_PRED) |
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                  (1 << UV_TM_PRED) | (1 << UV_CFL_PRED),
   UV_INTRA_DC = (1 << UV_DC_PRED),
   UV_INTRA_DC_CFL = (1 << UV_DC_PRED) | (1 << UV_CFL_PRED),
diff --git a/build/cmake/aom_config_defaults.cmake b/build/cmake/aom_config_defaults.cmake
index 3909cf4..5f6873f 100644
--- a/build/cmake/aom_config_defaults.cmake
+++ b/build/cmake/aom_config_defaults.cmake
@@ -108,7 +108,6 @@
 # AV1 experiment flags.
 set(CONFIG_ADAPT_SCAN 0 CACHE NUMBER "AV1 experiment flag.")
 set(CONFIG_ALTREF2 0 CACHE NUMBER "AV1 experiment flag.")
-set(CONFIG_ALT_INTRA 1 CACHE NUMBER "AV1 experiment flag.")
 set(CONFIG_ANS 0 CACHE NUMBER "AV1 experiment flag.")
 set(CONFIG_AOM_QM 1 CACHE NUMBER "AV1 experiment flag.")
 set(CONFIG_BGSPRITE 0 CACHE NUMBER "AV1 experiment flag.")
diff --git a/configure b/configure
index 24829d6..3dbd9d5 100755
--- a/configure
+++ b/configure
@@ -284,7 +284,6 @@
     q_adapt_probs
     bitstream_debug
     inter_stats_only
-    alt_intra
     palette_delta_encoding
     rawbits
     ec_smallmul
@@ -528,7 +527,6 @@
     # Enable low-bitdepth pixel pipeline by default
     soft_enable lowbitdepth
 
-    soft_enable alt_intra
     soft_enable palette_throughput
     soft_enable tempmv_signaling
 
@@ -547,7 +545,6 @@
     enabled ext_delta_q && soft_enable delta_q
     enabled txk_sel && soft_enable lv_map
     enabled compound_round && soft_enable convolve_round
-    enabled smooth_hv && soft_enable alt_intra
     enabled intra_edge && enable_feature ext_intra
     enabled chroma_2x2 && disable_feature chroma_sub8x8
     enabled dpcm_intra && enable_feature ext_tx
diff --git a/examples/inspect.c b/examples/inspect.c
index 1056af2..a9403cc 100644
--- a/examples/inspect.c
+++ b/examples/inspect.c
@@ -194,13 +194,11 @@
                                           ENUM(D153_PRED),
                                           ENUM(D207_PRED),
                                           ENUM(D63_PRED),
-#if CONFIG_ALT_INTRA
                                           ENUM(SMOOTH_PRED),
 #if CONFIG_SMOOTH_HV
                                           ENUM(SMOOTH_V_PRED),
                                           ENUM(SMOOTH_H_PRED),
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
                                           ENUM(TM_PRED),
                                           ENUM(NEARESTMV),
                                           ENUM(NEARMV),
@@ -225,13 +223,10 @@
   ENUM(UV_H_PRED),        ENUM(UV_D45_PRED),
   ENUM(UV_D135_PRED),     ENUM(UV_D117_PRED),
   ENUM(UV_D153_PRED),     ENUM(UV_D207_PRED),
-  ENUM(UV_D63_PRED),
-#if CONFIG_ALT_INTRA
-  ENUM(UV_SMOOTH_PRED),
+  ENUM(UV_D63_PRED),      ENUM(UV_SMOOTH_PRED),
 #if CONFIG_SMOOTH_HV
   ENUM(UV_SMOOTH_V_PRED), ENUM(UV_SMOOTH_H_PRED),
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
   ENUM(UV_TM_PRED),
 #if CONFIG_CFL
   ENUM(UV_CFL_PRED),
diff --git a/test/intrapred_test.cc b/test/intrapred_test.cc
index 5dd8c00..a963cdd 100644
--- a/test/intrapred_test.cc
+++ b/test/intrapred_test.cc
@@ -129,13 +129,6 @@
 const IntraPredFunc IntraPredTestVector8[] = {
   IntraPredFunc(&aom_highbd_dc_predictor_32x32_sse2,
                 &aom_highbd_dc_predictor_32x32_c, 32, 8),
-#if !CONFIG_ALT_INTRA
-  IntraPredFunc(&aom_highbd_tm_predictor_16x16_sse2,
-                &aom_highbd_tm_predictor_16x16_c, 16, 8),
-  IntraPredFunc(&aom_highbd_tm_predictor_32x32_sse2,
-                &aom_highbd_tm_predictor_32x32_c, 32, 8),
-#endif  // !CONFIG_ALT_INTRA
-
   IntraPredFunc(&aom_highbd_dc_predictor_4x4_sse2,
                 &aom_highbd_dc_predictor_4x4_c, 4, 8),
   IntraPredFunc(&aom_highbd_dc_predictor_8x8_sse2,
@@ -150,13 +143,6 @@
                 &aom_highbd_v_predictor_16x16_c, 16, 8),
   IntraPredFunc(&aom_highbd_v_predictor_32x32_sse2,
                 &aom_highbd_v_predictor_32x32_c, 32, 8)
-#if !CONFIG_ALT_INTRA
-      ,
-  IntraPredFunc(&aom_highbd_tm_predictor_4x4_sse2,
-                &aom_highbd_tm_predictor_4x4_c, 4, 8),
-  IntraPredFunc(&aom_highbd_tm_predictor_8x8_sse2,
-                &aom_highbd_tm_predictor_8x8_c, 8, 8)
-#endif  // !CONFIG_ALT_INTRA
 };
 
 INSTANTIATE_TEST_CASE_P(SSE2_TO_C_8, AV1IntraPredTest,
@@ -165,12 +151,6 @@
 const IntraPredFunc IntraPredTestVector10[] = {
   IntraPredFunc(&aom_highbd_dc_predictor_32x32_sse2,
                 &aom_highbd_dc_predictor_32x32_c, 32, 10),
-#if !CONFIG_ALT_INTRA
-  IntraPredFunc(&aom_highbd_tm_predictor_16x16_sse2,
-                &aom_highbd_tm_predictor_16x16_c, 16, 10),
-  IntraPredFunc(&aom_highbd_tm_predictor_32x32_sse2,
-                &aom_highbd_tm_predictor_32x32_c, 32, 10),
-#endif  // !CONFIG_ALT_INTRA
   IntraPredFunc(&aom_highbd_dc_predictor_4x4_sse2,
                 &aom_highbd_dc_predictor_4x4_c, 4, 10),
   IntraPredFunc(&aom_highbd_dc_predictor_8x8_sse2,
@@ -185,13 +165,6 @@
                 &aom_highbd_v_predictor_16x16_c, 16, 10),
   IntraPredFunc(&aom_highbd_v_predictor_32x32_sse2,
                 &aom_highbd_v_predictor_32x32_c, 32, 10)
-#if !CONFIG_ALT_INTRA
-      ,
-  IntraPredFunc(&aom_highbd_tm_predictor_4x4_sse2,
-                &aom_highbd_tm_predictor_4x4_c, 4, 10),
-  IntraPredFunc(&aom_highbd_tm_predictor_8x8_sse2,
-                &aom_highbd_tm_predictor_8x8_c, 8, 10)
-#endif  // !CONFIG_ALT_INTRA
 };
 
 INSTANTIATE_TEST_CASE_P(SSE2_TO_C_10, AV1IntraPredTest,
@@ -200,12 +173,6 @@
 const IntraPredFunc IntraPredTestVector12[] = {
   IntraPredFunc(&aom_highbd_dc_predictor_32x32_sse2,
                 &aom_highbd_dc_predictor_32x32_c, 32, 12),
-#if !CONFIG_ALT_INTRA
-  IntraPredFunc(&aom_highbd_tm_predictor_16x16_sse2,
-                &aom_highbd_tm_predictor_16x16_c, 16, 12),
-  IntraPredFunc(&aom_highbd_tm_predictor_32x32_sse2,
-                &aom_highbd_tm_predictor_32x32_c, 32, 12),
-#endif  // !CONFIG_ALT_INTRA
   IntraPredFunc(&aom_highbd_dc_predictor_4x4_sse2,
                 &aom_highbd_dc_predictor_4x4_c, 4, 12),
   IntraPredFunc(&aom_highbd_dc_predictor_8x8_sse2,
@@ -220,13 +187,6 @@
                 &aom_highbd_v_predictor_16x16_c, 16, 12),
   IntraPredFunc(&aom_highbd_v_predictor_32x32_sse2,
                 &aom_highbd_v_predictor_32x32_c, 32, 12)
-#if !CONFIG_ALT_INTRA
-      ,
-  IntraPredFunc(&aom_highbd_tm_predictor_4x4_sse2,
-                &aom_highbd_tm_predictor_4x4_c, 4, 12),
-  IntraPredFunc(&aom_highbd_tm_predictor_8x8_sse2,
-                &aom_highbd_tm_predictor_8x8_c, 8, 12)
-#endif  // !CONFIG_ALT_INTRA
 };
 
 INSTANTIATE_TEST_CASE_P(SSE2_TO_C_12, AV1IntraPredTest,
diff --git a/test/test_intra_pred_speed.cc b/test/test_intra_pred_speed.cc
index 70d8248..459fe0e 100644
--- a/test/test_intra_pred_speed.cc
+++ b/test/test_intra_pred_speed.cc
@@ -35,13 +35,10 @@
 const char *kAv1IntraPredNames[kNumAv1IntraFuncs] = {
   "DC_PRED",       "DC_LEFT_PRED",  "DC_TOP_PRED", "DC_128_PRED", "V_PRED",
   "H_PRED",        "D45_PRED",      "D135_PRED",   "D117_PRED",   "D153_PRED",
-  "D207_PRED",     "D63_PRED",      "TM_PRED",
-#if CONFIG_ALT_INTRA
-  "SMOOTH_PRED",
+  "D207_PRED",     "D63_PRED",      "TM_PRED",     "SMOOTH_PRED",
 #if CONFIG_SMOOTH_HV
   "SMOOTH_V_PRED", "SMOOTH_H_PRED",
 #endif  // CONFIG_SMOOTH_HV
-#endif  // CONFIG_ALT_INTRA
 };
 
 void TestIntraPred(const char name[], AvxPredFunc const *pred_funcs,
@@ -101,16 +98,12 @@
     "9117972ef64f91a58ff73e1731c81db2",
     "46d493dccf6e5356c6f3c0c73b7dd141",
     "b852f42e6c4991d415400332d567872f",
-#if CONFIG_ALT_INTRA
     "828c49a4248993cce4876fa26eab697f",
     "718c8cee9011f92ef31f77a9a7560010",
 #if CONFIG_SMOOTH_HV
     "b37eeadbbd9e3bdff023a5097b59213a",
     "d6fb9c659d82c78f0d0c891da6cba87f",
 #endif  // CONFIG_SMOOTH_HV
-#else
-    "309a618577b27c648f9c5ee45252bc8f",
-#endif  // CONFIG_ALT_INTRA
   };
   TestIntraPred("Intra4", pred_funcs, kAv1IntraPredNames, kNumAv1IntraFuncs,
                 kSignatures, 4, 4 * 4 * kNumAv1IntraFuncs);
@@ -130,16 +123,12 @@
     "8182bf60688b42205acd95e59e967157",
     "9d69fcaf12398e67242d3fcf5cf2267e",
     "7a09adb0fa6c2bf889a99dd816622feb",
-#if CONFIG_ALT_INTRA
     "f6ade499c626d38eb70661184b79bc57",
     "1ad5b106c79b792e514ba25e87139b5e",
 #if CONFIG_SMOOTH_HV
     "fe0d359b91a1d8141483d2e032f1b75f",
     "0cfd7603ced02829d1ce18b6795d73d0",
 #endif  // CONFIG_SMOOTH_HV
-#else
-    "815b75c8e0d91cc1ae766dc5d3e445a3",
-#endif  // CONFIG_ALT_INTRA
   };
   TestIntraPred("Intra8", pred_funcs, kAv1IntraPredNames, kNumAv1IntraFuncs,
                 kSignatures, 8, 8 * 8 * kNumAv1IntraFuncs);
@@ -159,16 +148,12 @@
     "3cc480297dbfeed01a1c2d78dd03d0c5",
     "fbd607f15da218c5390a5b183b634a10",
     "f7063ccbc29f87303d5c3d0555b08944",
-#if CONFIG_ALT_INTRA
     "7adcaaa3554eb71a81fc48cb9043984b",
     "c0acea4397c1b4d54a21bbcec5731dff",
 #if CONFIG_SMOOTH_HV
     "f15b8712f0f064e98a7d804d3074afa7",
     "01a09cdb8edd06d840c84643032fc02f",
 #endif  // CONFIG_SMOOTH_HV
-#else
-    "b8a41aa968ec108af447af4217cba91b",
-#endif  // CONFIG_ALT_INTRA
   };
   TestIntraPred("Intra16", pred_funcs, kAv1IntraPredNames, kNumAv1IntraFuncs,
                 kSignatures, 16, 16 * 16 * kNumAv1IntraFuncs);
@@ -188,16 +173,12 @@
     "d267e20ad9e5cd2915d1a47254d3d149",
     "3c45418137114cb6cef4c7a7baf4855c",
     "d520125ebd512c63c301bf67fea8e059",
-#if CONFIG_ALT_INTRA
     "297e8fbb5d33c29b12b228fa9d7c40a4",
     "31b9296d70dd82238c87173e6d5e65fd",
 #if CONFIG_SMOOTH_HV
     "f1041f77a34e86aaf30ea779ba84a2e8",
     "83e2b744a6a3d82321744442b1db945c",
 #endif  // CONFIG_SMOOTH_HV
-#else
-    "9e1370c6d42e08d357d9612c93a71cfc",
-#endif  // CONFIG_ALT_INTRA
   };
   TestIntraPred("Intra32", pred_funcs, kAv1IntraPredNames, kNumAv1IntraFuncs,
                 kSignatures, 32, 32 * 32 * kNumAv1IntraFuncs);
@@ -221,9 +202,6 @@
 // -----------------------------------------------------------------------------
 // 4x4
 
-#if CONFIG_ALT_INTRA
-#define tm_pred_func aom_paeth_predictor_4x4_c
-#define smooth_pred_func aom_smooth_predictor_4x4_c
 #if CONFIG_SMOOTH_HV
 #define smooth_v_pred_func aom_smooth_v_predictor_4x4_c
 #define smooth_h_pred_func aom_smooth_h_predictor_4x4_c
@@ -231,12 +209,6 @@
 #define smooth_v_pred_func NULL
 #define smooth_h_pred_func NULL
 #endif  // CONFIG_SMOOTH_HV
-#else
-#define tm_pred_func aom_tm_predictor_4x4_c
-#define smooth_pred_func NULL
-#define smooth_v_pred_func NULL
-#define smooth_h_pred_func NULL
-#endif  // CONFIG_ALT_INTRA
 
 INTRA_PRED_TEST(C, TestIntraPred4, aom_dc_predictor_4x4_c,
                 aom_dc_left_predictor_4x4_c, aom_dc_top_predictor_4x4_c,
@@ -244,28 +216,19 @@
                 aom_h_predictor_4x4_c, aom_d45e_predictor_4x4_c,
                 aom_d135_predictor_4x4_c, aom_d117_predictor_4x4_c,
                 aom_d153_predictor_4x4_c, aom_d207e_predictor_4x4_c,
-                aom_d63e_predictor_4x4_c, tm_pred_func, smooth_pred_func,
-                smooth_v_pred_func, smooth_h_pred_func)
+                aom_d63e_predictor_4x4_c, aom_paeth_predictor_4x4_c,
+                aom_smooth_predictor_4x4_c, smooth_v_pred_func,
+                smooth_h_pred_func)
 
-#undef tm_pred_func
-#undef smooth_pred_func
 #undef smooth_v_pred_func
 #undef smooth_h_pred_func
 
 #if HAVE_SSE2
-#if CONFIG_ALT_INTRA
-#define tm_pred_func NULL
-#else
-#define tm_pred_func aom_tm_predictor_4x4_sse2
-#endif  // CONFIG_ALT_INTRA
-
 INTRA_PRED_TEST(SSE2, TestIntraPred4, aom_dc_predictor_4x4_sse2,
                 aom_dc_left_predictor_4x4_sse2, aom_dc_top_predictor_4x4_sse2,
                 aom_dc_128_predictor_4x4_sse2, aom_v_predictor_4x4_sse2,
                 aom_h_predictor_4x4_sse2, NULL, NULL, NULL, NULL, NULL, NULL,
-                tm_pred_func, NULL, NULL, NULL)
-
-#undef tm_pred_func
+                NULL, NULL, NULL, NULL)
 #endif  // HAVE_SSE2
 
 #if HAVE_SSSE3
@@ -275,51 +238,30 @@
 #endif  // HAVE_SSSE3
 
 #if HAVE_DSPR2
-#if CONFIG_ALT_INTRA
-#define tm_pred_func NULL
-#else
-#define tm_pred_func aom_tm_predictor_4x4_dspr2
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(DSPR2, TestIntraPred4, aom_dc_predictor_4x4_dspr2, NULL, NULL,
                 NULL, NULL, aom_h_predictor_4x4_dspr2, NULL, NULL, NULL, NULL,
-                NULL, NULL, tm_pred_func, NULL, NULL, NULL)
-#undef tm_pred_func
+                NULL, NULL, NULL, NULL, NULL, NULL)
 #endif  // HAVE_DSPR2
 
 #if HAVE_NEON
-#if CONFIG_ALT_INTRA
-#define tm_pred_func NULL
-#else
-#define tm_pred_func aom_tm_predictor_4x4_neon
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(NEON, TestIntraPred4, aom_dc_predictor_4x4_neon,
                 aom_dc_left_predictor_4x4_neon, aom_dc_top_predictor_4x4_neon,
                 aom_dc_128_predictor_4x4_neon, aom_v_predictor_4x4_neon,
                 aom_h_predictor_4x4_neon, NULL, aom_d135_predictor_4x4_neon,
-                NULL, NULL, NULL, NULL, tm_pred_func, NULL, NULL, NULL)
-#undef tm_pred_func
+                NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
 #endif  // HAVE_NEON
 
 #if HAVE_MSA
-#if CONFIG_ALT_INTRA
-#define tm_pred_func NULL
-#else
-#define tm_pred_func aom_tm_predictor_4x4_msa
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(MSA, TestIntraPred4, aom_dc_predictor_4x4_msa,
                 aom_dc_left_predictor_4x4_msa, aom_dc_top_predictor_4x4_msa,
                 aom_dc_128_predictor_4x4_msa, aom_v_predictor_4x4_msa,
                 aom_h_predictor_4x4_msa, NULL, NULL, NULL, NULL, NULL, NULL,
-                tm_pred_func, NULL, NULL, NULL)
-#undef tm_pred_func
+                NULL, NULL, NULL, NULL)
 #endif  // HAVE_MSA
 
 // -----------------------------------------------------------------------------
 // 8x8
 
-#if CONFIG_ALT_INTRA
-#define tm_pred_func aom_paeth_predictor_8x8_c
-#define smooth_pred_func aom_smooth_predictor_8x8_c
 #if CONFIG_SMOOTH_HV
 #define smooth_v_pred_func aom_smooth_v_predictor_8x8_c
 #define smooth_h_pred_func aom_smooth_h_predictor_8x8_c
@@ -327,37 +269,24 @@
 #define smooth_v_pred_func NULL
 #define smooth_h_pred_func NULL
 #endif  // CONFIG_SMOOTH_HV
-#else
-#define tm_pred_func aom_tm_predictor_8x8_c
-#define smooth_pred_func NULL
-#define smooth_v_pred_func NULL
-#define smooth_h_pred_func NULL
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(C, TestIntraPred8, aom_dc_predictor_8x8_c,
                 aom_dc_left_predictor_8x8_c, aom_dc_top_predictor_8x8_c,
                 aom_dc_128_predictor_8x8_c, aom_v_predictor_8x8_c,
                 aom_h_predictor_8x8_c, aom_d45e_predictor_8x8_c,
                 aom_d135_predictor_8x8_c, aom_d117_predictor_8x8_c,
                 aom_d153_predictor_8x8_c, aom_d207e_predictor_8x8_c,
-                aom_d63e_predictor_8x8_c, tm_pred_func, smooth_pred_func,
-                smooth_v_pred_func, smooth_h_pred_func)
-#undef tm_pred_func
-#undef smooth_pred_func
+                aom_d63e_predictor_8x8_c, aom_paeth_predictor_8x8_c,
+                aom_smooth_predictor_8x8_c, smooth_v_pred_func,
+                smooth_h_pred_func)
 #undef smooth_v_pred_func
 #undef smooth_h_pred_func
 
 #if HAVE_SSE2
-#if CONFIG_ALT_INTRA
-#define tm_pred_func NULL
-#else
-#define tm_pred_func aom_tm_predictor_8x8_sse2
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(SSE2, TestIntraPred8, aom_dc_predictor_8x8_sse2,
                 aom_dc_left_predictor_8x8_sse2, aom_dc_top_predictor_8x8_sse2,
                 aom_dc_128_predictor_8x8_sse2, aom_v_predictor_8x8_sse2,
                 aom_h_predictor_8x8_sse2, NULL, NULL, NULL, NULL, NULL, NULL,
-                tm_pred_func, NULL, NULL, NULL)
-#undef tm_pred_func
+                NULL, NULL, NULL, NULL)
 #endif  // HAVE_SSE2
 
 #if HAVE_SSSE3
@@ -367,51 +296,30 @@
 #endif  // HAVE_SSSE3
 
 #if HAVE_DSPR2
-#if CONFIG_ALT_INTRA
-#define tm_pred_func NULL
-#else
-#define tm_pred_func aom_tm_predictor_8x8_dspr2
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(DSPR2, TestIntraPred8, aom_dc_predictor_8x8_dspr2, NULL, NULL,
                 NULL, NULL, aom_h_predictor_8x8_dspr2, NULL, NULL, NULL, NULL,
-                NULL, NULL, tm_pred_func, NULL, NULL, NULL)
-#undef tm_pred_func
+                NULL, NULL, NULL, NULL, NULL, NULL)
 #endif  // HAVE_DSPR2
 
 #if HAVE_NEON
-#if CONFIG_ALT_INTRA
-#define tm_pred_func NULL
-#else
-#define tm_pred_func aom_tm_predictor_8x8_neon
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(NEON, TestIntraPred8, aom_dc_predictor_8x8_neon,
                 aom_dc_left_predictor_8x8_neon, aom_dc_top_predictor_8x8_neon,
                 aom_dc_128_predictor_8x8_neon, aom_v_predictor_8x8_neon,
                 aom_h_predictor_8x8_neon, NULL, NULL, NULL, NULL, NULL, NULL,
-                tm_pred_func, NULL, NULL, NULL)
-#undef tm_pred_func
+                NULL, NULL, NULL, NULL)
 #endif  // HAVE_NEON
 
 #if HAVE_MSA
-#if CONFIG_ALT_INTRA
-#define tm_pred_func NULL
-#else
-#define tm_pred_func aom_tm_predictor_8x8_msa
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(MSA, TestIntraPred8, aom_dc_predictor_8x8_msa,
                 aom_dc_left_predictor_8x8_msa, aom_dc_top_predictor_8x8_msa,
                 aom_dc_128_predictor_8x8_msa, aom_v_predictor_8x8_msa,
                 aom_h_predictor_8x8_msa, NULL, NULL, NULL, NULL, NULL, NULL,
-                tm_pred_func, NULL, NULL, NULL)
-#undef tm_pred_func
+                NULL, NULL, NULL, NULL)
 #endif  // HAVE_MSA
 
 // -----------------------------------------------------------------------------
 // 16x16
 
-#if CONFIG_ALT_INTRA
-#define tm_pred_func aom_paeth_predictor_16x16_c
-#define smooth_pred_func aom_smooth_predictor_16x16_c
 #if CONFIG_SMOOTH_HV
 #define smooth_v_pred_func aom_smooth_v_predictor_16x16_c
 #define smooth_h_pred_func aom_smooth_h_predictor_16x16_c
@@ -419,38 +327,25 @@
 #define smooth_v_pred_func NULL
 #define smooth_h_pred_func NULL
 #endif  // CONFIG_SMOOTH_HV
-#else
-#define tm_pred_func aom_tm_predictor_16x16_c
-#define smooth_pred_func NULL
-#define smooth_v_pred_func NULL
-#define smooth_h_pred_func NULL
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(C, TestIntraPred16, aom_dc_predictor_16x16_c,
                 aom_dc_left_predictor_16x16_c, aom_dc_top_predictor_16x16_c,
                 aom_dc_128_predictor_16x16_c, aom_v_predictor_16x16_c,
                 aom_h_predictor_16x16_c, aom_d45e_predictor_16x16_c,
                 aom_d135_predictor_16x16_c, aom_d117_predictor_16x16_c,
                 aom_d153_predictor_16x16_c, aom_d207e_predictor_16x16_c,
-                aom_d63e_predictor_16x16_c, tm_pred_func, smooth_pred_func,
-                smooth_v_pred_func, smooth_h_pred_func)
-#undef tm_pred_func
-#undef smooth_pred_func
+                aom_d63e_predictor_16x16_c, aom_paeth_predictor_16x16_c,
+                aom_smooth_predictor_16x16_c, smooth_v_pred_func,
+                smooth_h_pred_func)
 #undef smooth_v_pred_func
 #undef smooth_h_pred_func
 
 #if HAVE_SSE2
-#if CONFIG_ALT_INTRA
-#define tm_pred_func NULL
-#else
-#define tm_pred_func aom_tm_predictor_16x16_sse2
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(SSE2, TestIntraPred16, aom_dc_predictor_16x16_sse2,
                 aom_dc_left_predictor_16x16_sse2,
                 aom_dc_top_predictor_16x16_sse2,
                 aom_dc_128_predictor_16x16_sse2, aom_v_predictor_16x16_sse2,
                 aom_h_predictor_16x16_sse2, NULL, NULL, NULL, NULL, NULL, NULL,
-                tm_pred_func, NULL, NULL, NULL)
-#undef tm_pred_func
+                NULL, NULL, NULL, NULL)
 #endif  // HAVE_SSE2
 
 #if HAVE_SSSE3
@@ -466,40 +361,25 @@
 #endif  // HAVE_DSPR2
 
 #if HAVE_NEON
-#if CONFIG_ALT_INTRA
-#define tm_pred_func NULL
-#else
-#define tm_pred_func aom_tm_predictor_16x16_neon
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(NEON, TestIntraPred16, aom_dc_predictor_16x16_neon,
                 aom_dc_left_predictor_16x16_neon,
                 aom_dc_top_predictor_16x16_neon,
                 aom_dc_128_predictor_16x16_neon, aom_v_predictor_16x16_neon,
                 aom_h_predictor_16x16_neon, NULL, NULL, NULL, NULL, NULL, NULL,
-                tm_pred_func, NULL, NULL, NULL)
-#undef tm_pred_func
+                NULL, NULL, NULL, NULL)
 #endif  // HAVE_NEON
 
 #if HAVE_MSA
-#if CONFIG_ALT_INTRA
-#define tm_pred_func NULL
-#else
-#define tm_pred_func aom_tm_predictor_16x16_msa
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(MSA, TestIntraPred16, aom_dc_predictor_16x16_msa,
                 aom_dc_left_predictor_16x16_msa, aom_dc_top_predictor_16x16_msa,
                 aom_dc_128_predictor_16x16_msa, aom_v_predictor_16x16_msa,
                 aom_h_predictor_16x16_msa, NULL, NULL, NULL, NULL, NULL, NULL,
-                tm_pred_func, NULL, NULL, NULL)
-#undef tm_pred_func
+                NULL, NULL, NULL, NULL)
 #endif  // HAVE_MSA
 
 // -----------------------------------------------------------------------------
 // 32x32
 
-#if CONFIG_ALT_INTRA
-#define tm_pred_func aom_paeth_predictor_32x32_c
-#define smooth_pred_func aom_smooth_predictor_32x32_c
 #if CONFIG_SMOOTH_HV
 #define smooth_v_pred_func aom_smooth_v_predictor_32x32_c
 #define smooth_h_pred_func aom_smooth_h_predictor_32x32_c
@@ -507,38 +387,25 @@
 #define smooth_v_pred_func NULL
 #define smooth_h_pred_func NULL
 #endif  // CONFIG_SMOOTH_HV
-#else
-#define tm_pred_func aom_tm_predictor_32x32_c
-#define smooth_pred_func NULL
-#define smooth_v_pred_func NULL
-#define smooth_h_pred_func NULL
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(C, TestIntraPred32, aom_dc_predictor_32x32_c,
                 aom_dc_left_predictor_32x32_c, aom_dc_top_predictor_32x32_c,
                 aom_dc_128_predictor_32x32_c, aom_v_predictor_32x32_c,
                 aom_h_predictor_32x32_c, aom_d45e_predictor_32x32_c,
                 aom_d135_predictor_32x32_c, aom_d117_predictor_32x32_c,
                 aom_d153_predictor_32x32_c, aom_d207e_predictor_32x32_c,
-                aom_d63e_predictor_32x32_c, tm_pred_func, smooth_pred_func,
-                smooth_v_pred_func, smooth_h_pred_func)
-#undef tm_pred_func
-#undef smooth_pred_func
+                aom_d63e_predictor_32x32_c, aom_paeth_predictor_32x32_c,
+                aom_smooth_predictor_32x32_c, smooth_v_pred_func,
+                smooth_h_pred_func)
 #undef smooth_v_pred_func
 #undef smooth_h_pred_func
 
 #if HAVE_SSE2
-#if CONFIG_ALT_INTRA
-#define tm_pred_func NULL
-#else
-#define tm_pred_func aom_tm_predictor_32x32_sse2
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(SSE2, TestIntraPred32, aom_dc_predictor_32x32_sse2,
                 aom_dc_left_predictor_32x32_sse2,
                 aom_dc_top_predictor_32x32_sse2,
                 aom_dc_128_predictor_32x32_sse2, aom_v_predictor_32x32_sse2,
                 aom_h_predictor_32x32_sse2, NULL, NULL, NULL, NULL, NULL, NULL,
-                tm_pred_func, NULL, NULL, NULL)
-#undef tm_pred_func
+                NULL, NULL, NULL, NULL)
 #endif  // HAVE_SSE2
 
 #if HAVE_SSSE3
@@ -548,32 +415,20 @@
 #endif  // HAVE_SSSE3
 
 #if HAVE_NEON
-#if CONFIG_ALT_INTRA
-#define tm_pred_func NULL
-#else
-#define tm_pred_func aom_tm_predictor_32x32_neon
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(NEON, TestIntraPred32, aom_dc_predictor_32x32_neon,
                 aom_dc_left_predictor_32x32_neon,
                 aom_dc_top_predictor_32x32_neon,
                 aom_dc_128_predictor_32x32_neon, aom_v_predictor_32x32_neon,
                 aom_h_predictor_32x32_neon, NULL, NULL, NULL, NULL, NULL, NULL,
-                tm_pred_func, NULL, NULL, NULL)
-#undef tm_pred_func
+                NULL, NULL, NULL, NULL)
 #endif  // HAVE_NEON
 
 #if HAVE_MSA
-#if CONFIG_ALT_INTRA
-#define tm_pred_func NULL
-#else
-#define tm_pred_func aom_tm_predictor_32x32_msa
-#endif  // CONFIG_ALT_INTRA
 INTRA_PRED_TEST(MSA, TestIntraPred32, aom_dc_predictor_32x32_msa,
                 aom_dc_left_predictor_32x32_msa, aom_dc_top_predictor_32x32_msa,
                 aom_dc_128_predictor_32x32_msa, aom_v_predictor_32x32_msa,
                 aom_h_predictor_32x32_msa, NULL, NULL, NULL, NULL, NULL, NULL,
-                tm_pred_func, NULL, NULL, NULL)
-#undef tm_pred_func
+                NULL, NULL, NULL, NULL)
 #endif  // HAVE_MSA
 
 #include "test/test_libaom.cc"
diff --git a/tools/aom_entropy_optimizer.c b/tools/aom_entropy_optimizer.c
index b892cc1..8557c3d 100644
--- a/tools/aom_entropy_optimizer.c
+++ b/tools/aom_entropy_optimizer.c
@@ -28,7 +28,6 @@
 #include "./aom_config.h"
 #include "av1/common/entropymode.h"
 
-#if CONFIG_ALT_INTRA
 #if CONFIG_SMOOTH_HV
 const aom_tree_index av1_intra_mode_tree[TREE_SIZE(INTRA_MODES)] = {
   -DC_PRED,
@@ -70,19 +69,6 @@
   -D207_PRED, -SMOOTH_PRED, /* 9 = D207_NODE */
 };
 #endif  // CONFIG_SMOOTH_HV
-#else
-const aom_tree_index av1_intra_mode_tree[TREE_SIZE(INTRA_MODES)] = {
-  -DC_PRED,   2,          /* 0 = DC_NODE */
-  -TM_PRED,   4,          /* 1 = TM_NODE */
-  -V_PRED,    6,          /* 2 = V_NODE */
-  8,          12,         /* 3 = COM_NODE */
-  -H_PRED,    10,         /* 4 = H_NODE */
-  -D135_PRED, -D117_PRED, /* 5 = D135_NODE */
-  -D45_PRED,  14,         /* 6 = D45_NODE */
-  -D63_PRED,  16,         /* 7 = D63_NODE */
-  -D153_PRED, -D207_PRED  /* 8 = D153_NODE */
-};
-#endif  // CONFIG_ALT_INTRA
 
 #define SPACES_PER_TAB 2