)]}'
{
  "commit": "9f4164335928afb9b17a9f762d8cf540ebfc6834",
  "tree": "49e0438273c4eccd8506991344d4e3c538df467c",
  "parents": [
    "64336ec42bfad8fc8fc7c1d40f472bc0c97060f7"
  ],
  "author": {
    "name": "Frank Galligan",
    "email": "fgalligan@google.com",
    "time": "Sat Oct 31 09:54:05 2026 -0700"
  },
  "committer": {
    "name": "Frank Galligan",
    "email": "fgalligan@google.com",
    "time": "Wed Nov 11 11:44:28 2026 -0800"
  },
  "message": "av1: Optimize ssim_rdmult and intra_mode_search\n\nAvoid calling pow(x, 1.0) in av1_set_ssim_rdmult for blocks \u003c\u003d 16x16,\nskip inter-only buffer allocations in allintra mode, copy only the\nactive portion of WinnerModeStats in store_winner_mode_stats, hoist\nallowed_mode_mask in av1_rd_pick_intra_sby_mode, and broadcast cached\nCfL DC prediction rows from scalar registers.\n\nBenchmarking results (incremental vs prev CL / cumulative vs baseline):\n- Stock avifenc still-image (Default 1T): -1.67% / -25.98% encode time\n- Stock avifenc still-image (Default 8T): -2.47% / -21.16% encode time\n- 48-image multi-rate corpus (Full Suite 1T): -1.18% / -26.10% time\n- Bit-exact output (1T and 8T)\n\nTAG\u003dagy\nCONV\u003db929a630-a6cd-45a0-979c-1767c30178ee\nChange-Id: I22ee84baa4fa3b6fd5aa84f4ae6400a9c9dd5ef8\n",
  "tree_diff": [
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