| commit | e9fde265f7a80fb237664a6ce2024ee9905d2608 | [log] [tgz] |
|---|---|---|
| author | Yi Luo <luoyi@google.com> | Fri Oct 07 15:02:33 2016 -0700 |
| committer | Yi Luo <luoyi@google.com> | Fri Oct 14 12:22:35 2016 -0700 |
| tree | 78cff185465536f1b584dd1b895c755dcaddb6f0 | |
| parent | fbabcad67c1b277608b6bee26816d9b4746d7a88 [diff] |
Zero high 128b YMM registers to avoid SSE-AVX transition penalties Documents: - https://software.intel.com/en-us/articles/intel-avx-state-transitions-migrating-sse-code-to-avx - https://software.intel.com/sites/default/files/m/d/4/1/d/8/11MC12_Avoiding_2BAVX-SSE_2BTransition_2BPenalties_2Brh_2Bfinal.pdf Change-Id: I90f85fcb15a7a2c49ee068300be6ffe9c68d371c