Exclude hbd functions in aom_dsp from HBD flag.
1% reduction on binary size.
All hbd functions in aom_dsp_rtcd_defs.pl have been excluded.
BUG=aomedia:2397
Change-Id: I8d97e91774e6938891f22bdd6da436fcd4549fbb
diff --git a/aom_dsp/aom_dsp_rtcd_defs.pl b/aom_dsp/aom_dsp_rtcd_defs.pl
index c00f763..eedb925 100755
--- a/aom_dsp/aom_dsp_rtcd_defs.pl
+++ b/aom_dsp/aom_dsp_rtcd_defs.pl
@@ -482,11 +482,11 @@
if (aom_config("CONFIG_AV1_ENCODER") eq "yes"){
add_proto qw/void aom_fdct8x8/, "const int16_t *input, tran_low_t *output, int stride";
specialize qw/aom_fdct8x8 sse2/, "$ssse3_x86_64";
-
# High bit depth
- add_proto qw/void aom_highbd_fdct8x8/, "const int16_t *input, tran_low_t *output, int stride";
- specialize qw/aom_highbd_fdct8x8 sse2/;
-
+ if (aom_config("CONFIG_AV1_HIGHBITDEPTH") eq "yes") {
+ add_proto qw/void aom_highbd_fdct8x8/, "const int16_t *input, tran_low_t *output, int stride";
+ specialize qw/aom_highbd_fdct8x8 sse2/;
+ }
# FFT/IFFT (float) only used for denoising (and noise power spectral density estimation)
add_proto qw/void aom_fft2x2_float/, "const float *input, float *temp, float *output";
@@ -572,14 +572,16 @@
specialize "aom_blend_a64_hmask", qw/sse4_1 neon/;
specialize "aom_blend_a64_vmask", qw/sse4_1 neon/;
-add_proto qw/void aom_highbd_blend_a64_mask/, "uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, const uint8_t *mask, uint32_t mask_stride, int w, int h, int subw, int subh, int bd";
-add_proto qw/void aom_highbd_blend_a64_hmask/, "uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, const uint8_t *mask, int w, int h, int bd";
-add_proto qw/void aom_highbd_blend_a64_vmask/, "uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, const uint8_t *mask, int w, int h, int bd";
-add_proto qw/void aom_highbd_blend_a64_d16_mask/, "uint8_t *dst, uint32_t dst_stride, const CONV_BUF_TYPE *src0, uint32_t src0_stride, const CONV_BUF_TYPE *src1, uint32_t src1_stride, const uint8_t *mask, uint32_t mask_stride, int w, int h, int subw, int subh, ConvolveParams *conv_params, const int bd";
-specialize "aom_highbd_blend_a64_mask", qw/sse4_1/;
-specialize "aom_highbd_blend_a64_hmask", qw/sse4_1/;
-specialize "aom_highbd_blend_a64_vmask", qw/sse4_1/;
-specialize "aom_highbd_blend_a64_d16_mask", qw/sse4_1 avx2/;
+if (aom_config("CONFIG_AV1_HIGHBITDEPTH") eq "yes") {
+ add_proto qw/void aom_highbd_blend_a64_mask/, "uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, const uint8_t *mask, uint32_t mask_stride, int w, int h, int subw, int subh, int bd";
+ add_proto qw/void aom_highbd_blend_a64_hmask/, "uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, const uint8_t *mask, int w, int h, int bd";
+ add_proto qw/void aom_highbd_blend_a64_vmask/, "uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, const uint8_t *mask, int w, int h, int bd";
+ add_proto qw/void aom_highbd_blend_a64_d16_mask/, "uint8_t *dst, uint32_t dst_stride, const CONV_BUF_TYPE *src0, uint32_t src0_stride, const CONV_BUF_TYPE *src1, uint32_t src1_stride, const uint8_t *mask, uint32_t mask_stride, int w, int h, int subw, int subh, ConvolveParams *conv_params, const int bd";
+ specialize "aom_highbd_blend_a64_mask", qw/sse4_1/;
+ specialize "aom_highbd_blend_a64_hmask", qw/sse4_1/;
+ specialize "aom_highbd_blend_a64_vmask", qw/sse4_1/;
+ specialize "aom_highbd_blend_a64_d16_mask", qw/sse4_1 avx2/;
+}
if (aom_config("CONFIG_AV1_ENCODER") eq "yes") {
#
@@ -773,13 +775,13 @@
specialize "aom_masked_sad${w}x${h}", qw/ssse3 avx2/;
}
-
+ if (aom_config("CONFIG_AV1_HIGHBITDEPTH") eq "yes") {
foreach (@block_sizes) {
($w, $h) = @$_;
add_proto qw/unsigned int/, "aom_highbd_masked_sad${w}x${h}", "const uint8_t *src8, int src_stride, const uint8_t *ref8, int ref_stride, const uint8_t *second_pred8, const uint8_t *msk, int msk_stride, int invert_mask";
specialize "aom_highbd_masked_sad${w}x${h}", qw/ssse3 avx2/;
}
-
+ }
#
# OBMC SAD
@@ -792,7 +794,7 @@
}
}
-
+ if (aom_config("CONFIG_AV1_HIGHBITDEPTH") eq "yes") {
foreach (@block_sizes) {
($w, $h) = @$_;
add_proto qw/unsigned int/, "aom_highbd_obmc_sad${w}x${h}", "const uint8_t *pre, int pre_stride, const int32_t *wsrc, const int32_t *mask";
@@ -800,7 +802,7 @@
specialize "aom_highbd_obmc_sad${w}x${h}", qw/sse4_1 avx2/;
}
}
-
+ }
#
# Multi-block SAD, comparing a reference to N independent blocks
@@ -903,15 +905,16 @@
add_proto qw/void aom_hadamard_32x32/, "const int16_t *src_diff, ptrdiff_t src_stride, tran_low_t *coeff";
specialize qw/aom_hadamard_32x32 avx2 sse2/;
- add_proto qw/void aom_highbd_hadamard_8x8/, "const int16_t *src_diff, ptrdiff_t src_stride, tran_low_t *coeff";
- specialize qw/aom_highbd_hadamard_8x8 avx2/;
+ if (aom_config("CONFIG_AV1_HIGHBITDEPTH") eq "yes") {
+ add_proto qw/void aom_highbd_hadamard_8x8/, "const int16_t *src_diff, ptrdiff_t src_stride, tran_low_t *coeff";
+ specialize qw/aom_highbd_hadamard_8x8 avx2/;
- add_proto qw/void aom_highbd_hadamard_16x16/, "const int16_t *src_diff, ptrdiff_t src_stride, tran_low_t *coeff";
- specialize qw/aom_highbd_hadamard_16x16 avx2/;
+ add_proto qw/void aom_highbd_hadamard_16x16/, "const int16_t *src_diff, ptrdiff_t src_stride, tran_low_t *coeff";
+ specialize qw/aom_highbd_hadamard_16x16 avx2/;
- add_proto qw/void aom_highbd_hadamard_32x32/, "const int16_t *src_diff, ptrdiff_t src_stride, tran_low_t *coeff";
- specialize qw/aom_highbd_hadamard_32x32 avx2/;
-
+ add_proto qw/void aom_highbd_hadamard_32x32/, "const int16_t *src_diff, ptrdiff_t src_stride, tran_low_t *coeff";
+ specialize qw/aom_highbd_hadamard_32x32 avx2/;
+ }
add_proto qw/int aom_satd/, "const tran_low_t *coeff, int length";
specialize qw/aom_satd avx2/;
@@ -925,8 +928,9 @@
add_proto qw/void aom_ssim_parms_16x16/, "const uint8_t *s, int sp, const uint8_t *r, int rp, uint32_t *sum_s, uint32_t *sum_r, uint32_t *sum_sq_s, uint32_t *sum_sq_r, uint32_t *sum_sxr";
specialize qw/aom_ssim_parms_16x16/, "$sse2_x86_64";
- add_proto qw/void aom_highbd_ssim_parms_8x8/, "const uint16_t *s, int sp, const uint16_t *r, int rp, uint32_t *sum_s, uint32_t *sum_r, uint32_t *sum_sq_s, uint32_t *sum_sq_r, uint32_t *sum_sxr";
-
+ if (aom_config("CONFIG_AV1_HIGHBITDEPTH") eq "yes") {
+ add_proto qw/void aom_highbd_ssim_parms_8x8/, "const uint16_t *s, int sp, const uint16_t *r, int rp, uint32_t *sum_s, uint32_t *sum_r, uint32_t *sum_sq_s, uint32_t *sum_sq_r, uint32_t *sum_sxr";
+ }
}
} # CONFIG_AV1_ENCODER
diff --git a/aom_dsp/avg.c b/aom_dsp/avg.c
index fcffc73..6cb92d5 100644
--- a/aom_dsp/avg.c
+++ b/aom_dsp/avg.c
@@ -170,6 +170,7 @@
}
}
+#if CONFIG_AV1_HIGHBITDEPTH
static void hadamard_highbd_col8_first_pass(const int16_t *src_diff,
ptrdiff_t src_stride,
int16_t *coeff) {
@@ -325,6 +326,7 @@
++coeff;
}
}
+#endif // CONFIG_AV1_HIGHBITDEPTH
// coeff: 16 bits, dynamic range [-32640, 32640].
// length: value range {16, 64, 256, 1024}.
diff --git a/aom_dsp/blend_a64_hmask.c b/aom_dsp/blend_a64_hmask.c
index 0554b43..e9e38ef 100644
--- a/aom_dsp/blend_a64_hmask.c
+++ b/aom_dsp/blend_a64_hmask.c
@@ -40,6 +40,7 @@
}
}
+#if CONFIG_AV1_HIGHBITDEPTH
void aom_highbd_blend_a64_hmask_c(uint8_t *dst_8, uint32_t dst_stride,
const uint8_t *src0_8, uint32_t src0_stride,
const uint8_t *src1_8, uint32_t src1_stride,
@@ -67,3 +68,4 @@
}
}
}
+#endif
diff --git a/aom_dsp/blend_a64_mask.c b/aom_dsp/blend_a64_mask.c
index 79956c3..32f2dc6 100644
--- a/aom_dsp/blend_a64_mask.c
+++ b/aom_dsp/blend_a64_mask.c
@@ -120,6 +120,7 @@
}
}
+#if CONFIG_AV1_HIGHBITDEPTH
void aom_highbd_blend_a64_d16_mask_c(
uint8_t *dst_8, uint32_t dst_stride, const CONV_BUF_TYPE *src0,
uint32_t src0_stride, const CONV_BUF_TYPE *src1, uint32_t src1_stride,
@@ -219,6 +220,7 @@
}
}
}
+#endif // CONFIG_AV1_HIGHBITDEPTH
// Blending with alpha mask. Mask values come from the range [0, 64],
// as described for AOM_BLEND_A64 in aom_dsp/blend.h. src0 or src1 can
@@ -281,6 +283,7 @@
}
}
+#if CONFIG_AV1_HIGHBITDEPTH
void aom_highbd_blend_a64_mask_c(uint8_t *dst_8, uint32_t dst_stride,
const uint8_t *src0_8, uint32_t src0_stride,
const uint8_t *src1_8, uint32_t src1_stride,
@@ -343,3 +346,4 @@
}
}
}
+#endif // CONFIG_AV1_HIGHBITDEPTH
diff --git a/aom_dsp/blend_a64_vmask.c b/aom_dsp/blend_a64_vmask.c
index 4f222e1..c938bb3 100644
--- a/aom_dsp/blend_a64_vmask.c
+++ b/aom_dsp/blend_a64_vmask.c
@@ -41,6 +41,7 @@
}
}
+#if CONFIG_AV1_HIGHBITDEPTH
void aom_highbd_blend_a64_vmask_c(uint8_t *dst_8, uint32_t dst_stride,
const uint8_t *src0_8, uint32_t src0_stride,
const uint8_t *src1_8, uint32_t src1_stride,
@@ -69,3 +70,4 @@
}
}
}
+#endif
diff --git a/aom_dsp/fwd_txfm.c b/aom_dsp/fwd_txfm.c
index e50f951..92f9cff 100644
--- a/aom_dsp/fwd_txfm.c
+++ b/aom_dsp/fwd_txfm.c
@@ -97,7 +97,9 @@
}
}
+#if CONFIG_AV1_HIGHBITDEPTH
void aom_highbd_fdct8x8_c(const int16_t *input, tran_low_t *final_output,
int stride) {
aom_fdct8x8_c(input, final_output, stride);
}
+#endif
diff --git a/aom_dsp/sad_av1.c b/aom_dsp/sad_av1.c
index c176001..10c6ac7 100644
--- a/aom_dsp/sad_av1.c
+++ b/aom_dsp/sad_av1.c
@@ -75,10 +75,10 @@
MASKSADMxN(32, 8)
MASKSADMxN(16, 64)
MASKSADMxN(64, 16)
+/* clang-format on */
- /* clang-format on */
-
- static INLINE
+#if CONFIG_AV1_HIGHBITDEPTH
+ static INLINE
unsigned int highbd_masked_sad(const uint8_t *src8, int src_stride,
const uint8_t *a8, int a_stride,
const uint8_t *b8, int b_stride,
@@ -141,6 +141,7 @@
HIGHBD_MASKSADMXN(32, 8)
HIGHBD_MASKSADMXN(16, 64)
HIGHBD_MASKSADMXN(64, 16)
+#endif // CONFIG_AV1_HIGHBITDEPTH
// pre: predictor being evaluated
// wsrc: target weighted prediction (has been *4096 to keep precision)
@@ -193,9 +194,10 @@
OBMCSADMxN(32, 8)
OBMCSADMxN(16, 64)
OBMCSADMxN(64, 16)
- /* clang-format on */
+/* clang-format on */
- static INLINE
+#if CONFIG_AV1_HIGHBITDEPTH
+ static INLINE
unsigned int highbd_obmc_sad(const uint8_t *pre8, int pre_stride,
const int32_t *wsrc, const int32_t *mask,
int width, int height) {
@@ -246,3 +248,4 @@
HIGHBD_OBMCSADMXN(16, 64)
HIGHBD_OBMCSADMXN(64, 16)
/* clang-format on */
+#endif // CONFIG_AV1_HIGHBITDEPTH
diff --git a/aom_dsp/ssim.c b/aom_dsp/ssim.c
index 681770b..95b8888 100644
--- a/aom_dsp/ssim.c
+++ b/aom_dsp/ssim.c
@@ -49,6 +49,7 @@
}
}
+#if CONFIG_AV1_HIGHBITDEPTH
void aom_highbd_ssim_parms_8x8_c(const uint16_t *s, int sp, const uint16_t *r,
int rp, uint32_t *sum_s, uint32_t *sum_r,
uint32_t *sum_sq_s, uint32_t *sum_sq_r,
@@ -64,6 +65,7 @@
}
}
}
+#endif
static const int64_t cc1 = 26634; // (64^2*(.01*255)^2
static const int64_t cc2 = 239708; // (64^2*(.03*255)^2
diff --git a/aom_dsp/x86/avg_intrin_avx2.c b/aom_dsp/x86/avg_intrin_avx2.c
index f9bcdf2..21fc729 100644
--- a/aom_dsp/x86/avg_intrin_avx2.c
+++ b/aom_dsp/x86/avg_intrin_avx2.c
@@ -224,6 +224,7 @@
}
}
+#if CONFIG_AV1_HIGHBITDEPTH
static void highbd_hadamard_col8_avx2(__m256i *in, int iter) {
__m256i a0 = in[0];
__m256i a1 = in[1];
@@ -424,6 +425,7 @@
t_coeff += 8;
}
}
+#endif // CONFIG_AV1_HIGHBITDEPTH
int aom_satd_avx2(const tran_low_t *coeff, int length) {
__m256i accum = _mm256_setzero_si256();
diff --git a/aom_dsp/x86/blend_a64_hmask_sse4.c b/aom_dsp/x86/blend_a64_hmask_sse4.c
index 4f5e3f8..e0289abe 100644
--- a/aom_dsp/x86/blend_a64_hmask_sse4.c
+++ b/aom_dsp/x86/blend_a64_hmask_sse4.c
@@ -24,6 +24,7 @@
src1_stride, mask, 0, w, h, 0, 0);
}
+#if CONFIG_AV1_HIGHBITDEPTH
void aom_highbd_blend_a64_hmask_sse4_1(
uint8_t *dst_8, uint32_t dst_stride, const uint8_t *src0_8,
uint32_t src0_stride, const uint8_t *src1_8, uint32_t src1_stride,
@@ -32,3 +33,4 @@
src1_8, src1_stride, mask, 0, w, h, 0, 0,
bd);
}
+#endif
diff --git a/aom_dsp/x86/blend_a64_mask_avx2.c b/aom_dsp/x86/blend_a64_mask_avx2.c
index f38c43f..95383d2 100644
--- a/aom_dsp/x86/blend_a64_mask_avx2.c
+++ b/aom_dsp/x86/blend_a64_mask_avx2.c
@@ -899,6 +899,7 @@
}
}
+#if CONFIG_AV1_HIGHBITDEPTH
//////////////////////////////////////////////////////////////////////////////
// aom_highbd_blend_a64_d16_mask_avx2()
//////////////////////////////////////////////////////////////////////////////
@@ -1370,3 +1371,4 @@
subh, conv_params, bd);
}
}
+#endif // CONFIG_AV1_HIGHBITDEPTH
diff --git a/aom_dsp/x86/blend_a64_mask_sse4.c b/aom_dsp/x86/blend_a64_mask_sse4.c
index a9b47af..4a368ef 100644
--- a/aom_dsp/x86/blend_a64_mask_sse4.c
+++ b/aom_dsp/x86/blend_a64_mask_sse4.c
@@ -423,6 +423,7 @@
}
}
+#if CONFIG_AV1_HIGHBITDEPTH
//////////////////////////////////////////////////////////////////////////////
// No sub-sampling
//////////////////////////////////////////////////////////////////////////////
@@ -812,7 +813,6 @@
//////////////////////////////////////////////////////////////////////////////
// Dispatch
//////////////////////////////////////////////////////////////////////////////
-
void aom_highbd_blend_a64_mask_sse4_1(uint8_t *dst_8, uint32_t dst_stride,
const uint8_t *src0_8,
uint32_t src0_stride,
@@ -870,6 +870,7 @@
mask_stride, w, h);
}
}
+#endif // CONFIG_AV1_HIGHBITDEPTH
static INLINE void blend_a64_d16_mask_w16_sse41(
uint8_t *dst, const CONV_BUF_TYPE *src0, const CONV_BUF_TYPE *src1,
@@ -1111,7 +1112,7 @@
//////////////////////////////////////////////////////////////////////////////
// aom_highbd_blend_a64_d16_mask_sse4_1()
//////////////////////////////////////////////////////////////////////////////
-
+#if CONFIG_AV1_HIGHBITDEPTH
static INLINE void highbd_blend_a64_d16_mask_w4_sse4_1(
uint16_t *dst, int dst_stride, const CONV_BUF_TYPE *src0, int src0_stride,
const CONV_BUF_TYPE *src1, int src1_stride, const __m128i *mask0a,
@@ -1556,3 +1557,4 @@
subh, conv_params, bd);
}
}
+#endif // CONFIG_AV1_HIGHBITDEPTH
diff --git a/aom_dsp/x86/blend_a64_vmask_sse4.c b/aom_dsp/x86/blend_a64_vmask_sse4.c
index 0649102..75fb1c5 100644
--- a/aom_dsp/x86/blend_a64_vmask_sse4.c
+++ b/aom_dsp/x86/blend_a64_vmask_sse4.c
@@ -143,6 +143,7 @@
h);
}
+#if CONFIG_AV1_HIGHBITDEPTH
//////////////////////////////////////////////////////////////////////////////
// Implementation - No sub-sampling
//////////////////////////////////////////////////////////////////////////////
@@ -281,3 +282,4 @@
src1_stride, mask, w, h);
}
}
+#endif // CONFIG_AV1_HIGHBITDEPTH
diff --git a/aom_dsp/x86/fwd_txfm_sse2.c b/aom_dsp/x86/fwd_txfm_sse2.c
index 6b7c11b..11c7d88 100644
--- a/aom_dsp/x86/fwd_txfm_sse2.c
+++ b/aom_dsp/x86/fwd_txfm_sse2.c
@@ -22,8 +22,12 @@
#include "aom_dsp/x86/fwd_txfm_impl_sse2.h"
#undef FDCT8x8_2D
+#if CONFIG_AV1_HIGHBITDEPTH
+
#undef DCT_HIGH_BIT_DEPTH
#define DCT_HIGH_BIT_DEPTH 1
#define FDCT8x8_2D aom_highbd_fdct8x8_sse2
#include "aom_dsp/x86/fwd_txfm_impl_sse2.h" // NOLINT
#undef FDCT8x8_2D
+
+#endif
diff --git a/av1/common/reconinter.c b/av1/common/reconinter.c
index a5d1f34..4532f9b 100644
--- a/av1/common/reconinter.c
+++ b/av1/common/reconinter.c
@@ -570,6 +570,7 @@
const int subh = (2 << mi_size_high_log2[sb_type]) == h;
const int subw = (2 << mi_size_wide_log2[sb_type]) == w;
const uint8_t *mask = av1_get_compound_type_mask(comp_data, sb_type);
+#if CONFIG_AV1_HIGHBITDEPTH
if (is_cur_buf_hbd(xd)) {
aom_highbd_blend_a64_d16_mask(dst, dst_stride, src0, src0_stride, src1,
src1_stride, mask, block_size_wide[sb_type],
@@ -579,6 +580,12 @@
src1_stride, mask, block_size_wide[sb_type], w,
h, subw, subh, conv_params);
}
+#else
+ (void)xd;
+ aom_lowbd_blend_a64_d16_mask(dst, dst_stride, src0, src0_stride, src1,
+ src1_stride, mask, block_size_wide[sb_type], w,
+ h, subw, subh, conv_params);
+#endif
}
void av1_make_masked_inter_predictor(
@@ -816,7 +823,6 @@
(void)above_mi;
struct obmc_inter_pred_ctxt *ctxt = (struct obmc_inter_pred_ctxt *)fun_ctxt;
const BLOCK_SIZE bsize = xd->mi[0]->sb_type;
- const int is_hbd = is_cur_buf_hbd(xd);
const int overlap =
AOMMIN(block_size_high[bsize], block_size_high[BLOCK_64X64]) >> 1;
@@ -833,13 +839,18 @@
const int tmp_stride = ctxt->adjacent_stride[plane];
const uint8_t *const tmp = &ctxt->adjacent[plane][plane_col];
const uint8_t *const mask = av1_get_obmc_mask(bh);
-
+#if CONFIG_AV1_HIGHBITDEPTH
+ const int is_hbd = is_cur_buf_hbd(xd);
if (is_hbd)
aom_highbd_blend_a64_vmask(dst, dst_stride, dst, dst_stride, tmp,
tmp_stride, mask, bw, bh, xd->bd);
else
aom_blend_a64_vmask(dst, dst_stride, dst, dst_stride, tmp, tmp_stride,
mask, bw, bh);
+#else
+ aom_blend_a64_vmask(dst, dst_stride, dst, dst_stride, tmp, tmp_stride, mask,
+ bw, bh);
+#endif
}
}
@@ -853,7 +864,6 @@
const BLOCK_SIZE bsize = xd->mi[0]->sb_type;
const int overlap =
AOMMIN(block_size_wide[bsize], block_size_wide[BLOCK_64X64]) >> 1;
- const int is_hbd = is_cur_buf_hbd(xd);
for (int plane = 0; plane < num_planes; ++plane) {
const struct macroblockd_plane *pd = &xd->plane[plane];
@@ -869,12 +879,18 @@
const uint8_t *const tmp = &ctxt->adjacent[plane][plane_row * tmp_stride];
const uint8_t *const mask = av1_get_obmc_mask(bw);
+#if CONFIG_AV1_HIGHBITDEPTH
+ const int is_hbd = is_cur_buf_hbd(xd);
if (is_hbd)
aom_highbd_blend_a64_hmask(dst, dst_stride, dst, dst_stride, tmp,
tmp_stride, mask, bw, bh, xd->bd);
else
aom_blend_a64_hmask(dst, dst_stride, dst, dst_stride, tmp, tmp_stride,
mask, bw, bh);
+#else
+ aom_blend_a64_hmask(dst, dst_stride, dst, dst_stride, tmp, tmp_stride, mask,
+ bw, bh);
+#endif
}
}
@@ -1065,6 +1081,7 @@
interstride, mask, bw, bw, bh, 0, 0);
}
+#if CONFIG_AV1_HIGHBITDEPTH
static AOM_INLINE void combine_interintra_highbd(
INTERINTRA_MODE mode, int8_t use_wedge_interintra, int8_t wedge_index,
int8_t wedge_sign, BLOCK_SIZE bsize, BLOCK_SIZE plane_bsize,
@@ -1092,6 +1109,7 @@
interpred8, interstride, mask, bw, bw, bh, 0, 0,
bd);
}
+#endif
void av1_build_intra_predictors_for_interintra(const AV1_COMMON *cm,
MACROBLOCKD *xd,
@@ -1120,6 +1138,7 @@
const int ssx = xd->plane[plane].subsampling_x;
const int ssy = xd->plane[plane].subsampling_y;
const BLOCK_SIZE plane_bsize = get_plane_block_size(bsize, ssx, ssy);
+#if CONFIG_AV1_HIGHBITDEPTH
if (is_cur_buf_hbd(xd)) {
combine_interintra_highbd(
xd->mi[0]->interintra_mode, xd->mi[0]->use_wedge_interintra,
@@ -1128,6 +1147,7 @@
inter_pred, inter_stride, intra_pred, intra_stride, xd->bd);
return;
}
+#endif
combine_interintra(
xd->mi[0]->interintra_mode, xd->mi[0]->use_wedge_interintra,
xd->mi[0]->interintra_wedge_index, INTERINTRA_WEDGE_SIGN, bsize,
diff --git a/av1/encoder/reconinter_enc.c b/av1/encoder/reconinter_enc.c
index 6cfd2e0..2424ade 100644
--- a/av1/encoder/reconinter_enc.c
+++ b/av1/encoder/reconinter_enc.c
@@ -524,6 +524,7 @@
mask, block_size_wide[sb_type], w, h, subw, subh);
}
+#if CONFIG_AV1_HIGHBITDEPTH
static void build_masked_compound_highbd(
uint8_t *dst_8, int dst_stride, const uint8_t *src0_8, int src0_stride,
const uint8_t *src1_8, int src1_stride,
@@ -540,6 +541,7 @@
src1_stride, mask, block_size_wide[sb_type], w, h,
subw, subh, bd);
}
+#endif
static void build_wedge_inter_predictor_from_buf(
MACROBLOCKD *xd, int plane, int x, int y, int w, int h, uint8_t *ext_dst0,
@@ -566,7 +568,7 @@
ext_dst_stride0, ext_dst1, ext_dst_stride1, h, w);
}
}
-
+#if CONFIG_AV1_HIGHBITDEPTH
if (is_hbd) {
build_masked_compound_highbd(
dst, dst_buf->stride, CONVERT_TO_BYTEPTR(ext_dst0), ext_dst_stride0,
@@ -577,6 +579,11 @@
ext_dst1, ext_dst_stride1, comp_data, mbmi->sb_type,
h, w);
}
+#else
+ build_masked_compound(dst, dst_buf->stride, ext_dst0, ext_dst_stride0,
+ ext_dst1, ext_dst_stride1, comp_data, mbmi->sb_type,
+ h, w);
+#endif
} else {
#if CONFIG_AV1_HIGHBITDEPTH
if (is_hbd) {
diff --git a/av1/encoder/tpl_model.c b/av1/encoder/tpl_model.c
index 9cb49b3..efaf5b0 100644
--- a/av1/encoder/tpl_model.c
+++ b/av1/encoder/tpl_model.c
@@ -66,6 +66,7 @@
static AOM_INLINE void wht_fwd_txfm(int16_t *src_diff, int bw,
tran_low_t *coeff, TX_SIZE tx_size,
int is_hbd) {
+#if CONFIG_AV1_HIGHBITDEPTH
if (is_hbd) {
switch (tx_size) {
case TX_8X8: aom_highbd_hadamard_8x8(src_diff, bw, coeff); break;
@@ -81,6 +82,15 @@
default: assert(0);
}
}
+#else
+ (void)is_hbd;
+ switch (tx_size) {
+ case TX_8X8: aom_hadamard_8x8(src_diff, bw, coeff); break;
+ case TX_16X16: aom_hadamard_16x16(src_diff, bw, coeff); break;
+ case TX_32X32: aom_hadamard_32x32(src_diff, bw, coeff); break;
+ default: assert(0);
+ }
+#endif
}
static uint32_t motion_estimation(AV1_COMP *cpi, MACROBLOCK *x,
diff --git a/test/blend_a64_mask_1d_test.cc b/test/blend_a64_mask_1d_test.cc
index f8844ee..3a3e1b9 100644
--- a/test/blend_a64_mask_1d_test.cc
+++ b/test/blend_a64_mask_1d_test.cc
@@ -218,7 +218,7 @@
//////////////////////////////////////////////////////////////////////////////
// High bit-depth version
//////////////////////////////////////////////////////////////////////////////
-
+#if CONFIG_AV1_HIGHBITDEPTH
typedef void (*FHBD)(uint8_t *dst, uint32_t dst_stride, const uint8_t *src0,
uint32_t src0_stride, const uint8_t *src1,
uint32_t src1_stride, const uint8_t *mask, int w, int h,
@@ -336,4 +336,5 @@
TestFuncsHBD(highbd_blend_a64_vmask_ref,
aom_highbd_blend_a64_vmask_sse4_1)));
#endif // HAVE_SSE4_1
+#endif // CONFIG_AV1_HIGHBITDEPTH
} // namespace
diff --git a/test/blend_a64_mask_test.cc b/test/blend_a64_mask_test.cc
index 7592533..4d9ed36 100644
--- a/test/blend_a64_mask_test.cc
+++ b/test/blend_a64_mask_test.cc
@@ -365,7 +365,7 @@
//////////////////////////////////////////////////////////////////////////////
// High bit-depth version
//////////////////////////////////////////////////////////////////////////////
-
+#if CONFIG_AV1_HIGHBITDEPTH
typedef void (*FHBD)(uint8_t *dst, uint32_t dst_stride, const uint8_t *src0,
uint32_t src0_stride, const uint8_t *src1,
uint32_t src1_stride, const uint8_t *mask,
@@ -616,4 +616,5 @@
aom_highbd_blend_a64_mask_avx2)));
#endif // HAVE_AVX2
#endif
+#endif // CONFIG_AV1_HIGHBITDEPTH
} // namespace
diff --git a/test/masked_sad_test.cc b/test/masked_sad_test.cc
index 311f187..c8b5db1 100644
--- a/test/masked_sad_test.cc
+++ b/test/masked_sad_test.cc
@@ -115,6 +115,7 @@
TEST_P(MaskedSADTest, DISABLED_Speed) { runMaskedSADTest(2000000); }
+#if CONFIG_AV1_HIGHBITDEPTH
typedef unsigned int (*HighbdMaskedSADFunc)(const uint8_t *src, int src_stride,
const uint8_t *ref, int ref_stride,
const uint8_t *second_pred,
@@ -206,6 +207,7 @@
TEST_P(HighbdMaskedSADTest, OperationCheck) { runHighbdMaskedSADTest(1); }
TEST_P(HighbdMaskedSADTest, DISABLED_Speed) { runHighbdMaskedSADTest(1000000); }
+#endif // CONFIG_AV1_HIGHBITDEPTH
using ::testing::make_tuple;
@@ -237,6 +239,7 @@
INSTANTIATE_TEST_CASE_P(SSSE3, MaskedSADTest, ::testing::ValuesIn(msad_test));
+#if CONFIG_AV1_HIGHBITDEPTH
const HighbdMaskedSADParam hbd_msad_test[] = {
make_tuple(&aom_highbd_masked_sad4x4_ssse3, &aom_highbd_masked_sad4x4_c),
make_tuple(&aom_highbd_masked_sad4x8_ssse3, &aom_highbd_masked_sad4x8_c),
@@ -267,6 +270,7 @@
INSTANTIATE_TEST_CASE_P(SSSE3, HighbdMaskedSADTest,
::testing::ValuesIn(hbd_msad_test));
+#endif // CONFIG_AV1_HIGHBITDEPTH
#endif // HAVE_SSSE3
#if HAVE_AVX2
@@ -298,6 +302,7 @@
INSTANTIATE_TEST_CASE_P(AVX2, MaskedSADTest,
::testing::ValuesIn(msad_avx2_test));
+#if CONFIG_AV1_HIGHBITDEPTH
const HighbdMaskedSADParam hbd_msad_avx2_test[] = {
make_tuple(&aom_highbd_masked_sad4x4_avx2, &aom_highbd_masked_sad4x4_ssse3),
make_tuple(&aom_highbd_masked_sad4x8_avx2, &aom_highbd_masked_sad4x8_ssse3),
@@ -337,6 +342,7 @@
INSTANTIATE_TEST_CASE_P(AVX2, HighbdMaskedSADTest,
::testing::ValuesIn(hbd_msad_avx2_test));
+#endif // CONFIG_AV1_HIGHBITDEPTH
#endif // HAVE_AVX2
} // namespace
diff --git a/test/obmc_sad_test.cc b/test/obmc_sad_test.cc
index 5c7d99e..75d7cda 100644
--- a/test/obmc_sad_test.cc
+++ b/test/obmc_sad_test.cc
@@ -145,6 +145,7 @@
INSTANTIATE_TEST_CASE_P(AVX2, ObmcSadTest, ::testing::ValuesIn(avx2_functions));
#endif // HAVE_AVX2
+#if CONFIG_AV1_HIGHBITDEPTH
////////////////////////////////////////////////////////////////////////////////
// High bit-depth
////////////////////////////////////////////////////////////////////////////////
@@ -262,4 +263,5 @@
INSTANTIATE_TEST_CASE_P(AVX2, ObmcSadHBDTest,
::testing::ValuesIn(avx2_functions_hbd));
#endif // HAVE_AVX2
+#endif // CONFIG_AV1_HIGHBITDEPTH
} // namespace
