)]}'
{
  "commit": "d01ff5945dde6077ffbbf29ed9cd7ac78d501fa0",
  "tree": "c6f9aa3da811bf4cea3d66a169873b6d59fea1ba",
  "parents": [
    "6f295fd0936ba0ed5231eba17f5004ea73472177"
  ],
  "author": {
    "name": "Ruiling Song",
    "email": "ruiling.song@intel.com",
    "time": "Fri Sep 13 17:00:28 2019 +0800"
  },
  "committer": {
    "name": "Yunqing Wang",
    "email": "yunqingwang@google.com",
    "time": "Thu Sep 26 14:59:22 2019 +0000"
  },
  "message": "Minor improvement to warp_affine_avx2\n\nThis patch basically includes two minor improvement:\n\n1.) Through inserting the 128bit data to high half of ymm,\n    we are reducing register pressure, this would avoid\n    register spill/fill for gcc, and also save some unpacking\n    instructions.\n\n2.) The \u0027(unsigned)\u0027 convert is telling the compiler that we\n    know the array offset is non-negative, thus one \u0027movslq\u0027\n    instruction could be avoided for array offset calculation.\n\nProfiling below command:\n./aomenc 1080p_park_joy.y4m --cpu-used\u003d3 --cq-level\u003d32 --limit\u003d50 --passes\u003d1 -o parkjoy.webm\n\nBefore the patch:\n     5.81%     5.80%  aomenc   aomenc            [.] av1_warp_affine_avx2\n            |\n             --5.79%--av1_warp_plane\n                       av1_warp_affine_avx2\nWith the patch:\n     5.53%     5.52%  aomenc   aomenc            [.] av1_warp_affine_avx2\n            |\n             --5.51%--av1_warp_plane\n                       av1_warp_affine_avx2\n\nChange-Id: Ic245e4da3f0f39f95f69c16fffce01fdd9fd9117\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b5fbb4c9d37078bf048d0755d4c8b51596c4c056",
      "old_mode": 33188,
      "old_path": "av1/common/x86/warp_plane_avx2.c",
      "new_id": "53a928d76b1a1d9f621ffdaf765351c40c3daf63",
      "new_mode": 33188,
      "new_path": "av1/common/x86/warp_plane_avx2.c"
    }
  ]
}