commit fcf5fa2723524fe2beabd2b0ac1d4409a2284405
author Zoe Liu <zoeliu@google.com> Mon Jun 26 16:00:38 2017 -0700
committer Zoe Liu <zoeliu@google.com> Wed Jul 12 00:20:35 2017 +0000
tree 7afe2e2695de320f7b6046b55676ba4f097753b3
parent 9c52192b10b054559edb6e34af9a946e2868f2d7

Further work on ext-comp-refs for ref frame coding

(1) Work with var-refs to remove redundant bits in ref frame
    coding;
(2) Add a new uni-directional compound reference pair:
    (LAST_FRAME, LAST3_FRAME);
(3) Redesign the contexts for encoding uni-directional reference frame
    pairs;
(4) Use aom_entropy_optimizer to collect stats for all the default
    probability setups related to the coding of reference frames.

Compared against the baseline (default enabled tools excluding ext-tx
and global-motion for encoder speed concern) with one-sided-compound,
the coding gain of ext-comp-refs + var-refs - one-sided-compound is:

lowres: avg_psnr -0.385%; ovr_psnr -0.378% ssim -0.344%
midres: avg_psnr -0.466%; ovr_psnr -0.447% ssim -0.513%

AWCY - High Latency:
   PSNR | PSNR Cb | PSNR Cr | PSNR HVS |    SSIM | MS SSIM | CIEDE 2000
-0.2758 | -0.1526 | -0.0965 |  -0.2581 | -0.2492 | -0.2534 |    -0.2118

AWCY - Low Latency:
   PSNR | PSNR Cb | PSNR Cr | PSNR HVS |    SSIM | MS SSIM | CIEDE 2000
-1.0467 | -1.4500 | -0.9732 |  -0.9928 | -1.0407 | -1.0180 |    -1.0049

Compared against the baseline (default enabled tools excluding ext-tx
and global-motion for encoder speed concern) without
one-sided-compound, the coding gain of
ext-comp-refs + var-refs - one-sided-compound is:

lowres: avg_psnr -0.875%; ovr_psnr -0.877% ssim -0.895%
midres: avg_psnr -0.824%; ovr_psnr -0.802% ssim -0.843%

Change-Id: I8de774c9a74c20632ea93ccb0c17779fa94431cb

av1/encoder/rd.c

diff --git a/av1/encoder/rd.c b/av1/encoder/rd.c
index 2fafa4d..1c9ed43 100644
--- a/av1/encoder/rd.c
+++ b/av1/encoder/rd.c
@@ -1061,6 +1061,7 @@
 
 #if CONFIG_EXT_COMP_REFS
   rd->thresh_mult[THR_COMP_NEAREST_NEARESTLL2] += 1000;
+  rd->thresh_mult[THR_COMP_NEAREST_NEARESTLL3] += 1000;
   rd->thresh_mult[THR_COMP_NEAREST_NEARESTLG] += 1000;
   rd->thresh_mult[THR_COMP_NEAREST_NEARESTBA] += 1000;
 #endif  // CONFIG_EXT_COMP_REFS
@@ -1081,6 +1082,7 @@
   rd->thresh_mult[THR_COMP_NEARESTGB] += 1000;
 #if CONFIG_EXT_COMP_REFS
   rd->thresh_mult[THR_COMP_NEARESTLL2] += 1000;
+  rd->thresh_mult[THR_COMP_NEARESTLL3] += 1000;
   rd->thresh_mult[THR_COMP_NEARESTLG] += 1000;
   rd->thresh_mult[THR_COMP_NEARESTBA] += 1000;
 #endif  // CONFIG_EXT_COMP_REFS
@@ -1158,8 +1160,6 @@
   rd->thresh_mult[THR_COMP_ZERO_ZEROGB] += 2500;
 
 #if CONFIG_EXT_COMP_REFS
-  rd->thresh_mult[THR_COMP_NEAREST_NEARLL2] += 1200;
-  rd->thresh_mult[THR_COMP_NEAR_NEARESTLL2] += 1200;
   rd->thresh_mult[THR_COMP_NEAR_NEARLL2] += 1200;
   rd->thresh_mult[THR_COMP_NEAREST_NEWLL2] += 1500;
   rd->thresh_mult[THR_COMP_NEW_NEARESTLL2] += 1500;
@@ -1168,8 +1168,14 @@
   rd->thresh_mult[THR_COMP_NEW_NEWLL2] += 2000;
   rd->thresh_mult[THR_COMP_ZERO_ZEROLL2] += 2500;
 
-  rd->thresh_mult[THR_COMP_NEAREST_NEARLG] += 1200;
-  rd->thresh_mult[THR_COMP_NEAR_NEARESTLG] += 1200;
+  rd->thresh_mult[THR_COMP_NEAR_NEARLL3] += 1200;
+  rd->thresh_mult[THR_COMP_NEAREST_NEWLL3] += 1500;
+  rd->thresh_mult[THR_COMP_NEW_NEARESTLL3] += 1500;
+  rd->thresh_mult[THR_COMP_NEAR_NEWLL3] += 1700;
+  rd->thresh_mult[THR_COMP_NEW_NEARLL3] += 1700;
+  rd->thresh_mult[THR_COMP_NEW_NEWLL3] += 2000;
+  rd->thresh_mult[THR_COMP_ZERO_ZEROLL3] += 2500;
+
   rd->thresh_mult[THR_COMP_NEAR_NEARLG] += 1200;
   rd->thresh_mult[THR_COMP_NEAREST_NEWLG] += 1500;
   rd->thresh_mult[THR_COMP_NEW_NEARESTLG] += 1500;
@@ -1178,8 +1184,6 @@
   rd->thresh_mult[THR_COMP_NEW_NEWLG] += 2000;
   rd->thresh_mult[THR_COMP_ZERO_ZEROLG] += 2500;
 
-  rd->thresh_mult[THR_COMP_NEAREST_NEARBA] += 1200;
-  rd->thresh_mult[THR_COMP_NEAR_NEARESTBA] += 1200;
   rd->thresh_mult[THR_COMP_NEAR_NEARBA] += 1200;
   rd->thresh_mult[THR_COMP_NEAREST_NEWBA] += 1500;
   rd->thresh_mult[THR_COMP_NEW_NEARESTBA] += 1500;
@@ -1216,6 +1220,8 @@
 #if CONFIG_EXT_COMP_REFS
   rd->thresh_mult[THR_COMP_NEARLL2] += 1500;
   rd->thresh_mult[THR_COMP_NEWLL2] += 2000;
+  rd->thresh_mult[THR_COMP_NEARLL3] += 1500;
+  rd->thresh_mult[THR_COMP_NEWLL3] += 2000;
   rd->thresh_mult[THR_COMP_NEARLG] += 1500;
   rd->thresh_mult[THR_COMP_NEWLG] += 2000;
   rd->thresh_mult[THR_COMP_NEARBA] += 1500;
@@ -1238,6 +1244,7 @@
 
 #if CONFIG_EXT_COMP_REFS
   rd->thresh_mult[THR_COMP_ZEROLL2] += 2500;
+  rd->thresh_mult[THR_COMP_ZEROLL3] += 2500;
   rd->thresh_mult[THR_COMP_ZEROLG] += 2500;
   rd->thresh_mult[THR_COMP_ZEROBA] += 2500;
 #endif  // CONFIG_EXT_COMP_REFS