commit d0ee6c77562d22a013776f2bfc6273fade0f74ea
author James Zern <jzern@google.com> Mon Apr 24 17:36:25 2023 -0700
committer James Zern <jzern@google.com> Mon Apr 24 19:26:53 2023 -0700
tree 0598a3ac085a8bf6ff04113e2d896f0ead8f26db
parent 18ee55b05444315979a109a10fe4aab152998e04

warp_plane_neon: fix vector initializers w/Windows Arm64

Don't assume the NEON types are backed by a vector type and use
intrinsics to initialize registers; no change in assembly.

Bug: b/277255390
Change-Id: Idbba1b2add0c046d777f5728bede850f8f32595e

av1/common/arm/warp_plane_neon.c

diff --git a/av1/common/arm/warp_plane_neon.c b/av1/common/arm/warp_plane_neon.c
index 03b6db8..b4d3148 100644
--- a/av1/common/arm/warp_plane_neon.c
+++ b/av1/common/arm/warp_plane_neon.c
@@ -222,8 +222,7 @@
                                           int16x8_t *tmp_dst, int sx, int alpha,
                                           int k, const int offset_bits_horiz,
                                           const int reduce_bits_horiz) {
-  const uint8x16_t mask = { 255, 0, 255, 0, 255, 0, 255, 0,
-                            255, 0, 255, 0, 255, 0, 255, 0 };
+  const uint8x16_t mask = vreinterpretq_u8_u16(vdupq_n_u16(0x00ff));
   const int32x4_t add_const = vdupq_n_s32((int32_t)(1 << offset_bits_horiz));
   const int16x8_t shift = vdupq_n_s16(-(int16_t)reduce_bits_horiz);
 
@@ -488,9 +487,9 @@
   int32x4_t res_lo, res_hi;
   int16x8_t result_final;
   uint8x16_t src_1, src_2, src_3, src_4;
-  uint8x16_t indx_vec = {
-    0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-  };
+  static const uint8_t k0To15[16] = { 0, 1, 2,  3,  4,  5,  6,  7,
+                                      8, 9, 10, 11, 12, 13, 14, 15 };
+  uint8x16_t indx_vec = vld1q_u8(k0To15);
   uint8x16_t cmp_vec;
 
   const int reduce_bits_horiz = conv_params->round_0;