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aomedia / avm / 3e629b96922d8ea9ce7a001c3df05cc6335c008a / . / av1 / common / av1_fwd_txfm2d_cfg.h
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Yaowu Xuc27fc142016-08-22 16:08:15 -0700[diff] [blame]1/*
Yaowu Xubde4ac82016-11-28 15:26:06 -0800[diff] [blame]2 * Copyright (c) 2016, Alliance for Open Media. All rights reserved
Yaowu Xuc27fc142016-08-22 16:08:15 -0700[diff] [blame]3 *
Yaowu Xubde4ac82016-11-28 15:26:06 -0800[diff] [blame]4 * This source code is subject to the terms of the BSD 2 Clause License and
5 * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
6 * was not distributed with this source code in the LICENSE file, you can
7 * obtain it at www.aomedia.org/license/software. If the Alliance for Open
8 * Media Patent License 1.0 was not distributed with this source code in the
9 * PATENTS file, you can obtain it at www.aomedia.org/license/patent.
Yaowu Xuc27fc142016-08-22 16:08:15 -0700[diff] [blame]10 */
11
Yaowu Xuf883b422016-08-30 14:01:10 -0700[diff] [blame]12#ifndef AV1_FWD_TXFM2D_CFG_H_
13#define AV1_FWD_TXFM2D_CFG_H_
Yaowu Xuc27fc142016-08-22 16:08:15 -0700[diff] [blame]14#include "av1/common/enums.h"
Yaowu Xuf883b422016-08-30 14:01:10 -0700[diff] [blame]15#include "av1/common/av1_fwd_txfm1d.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -0700[diff] [blame]16// ---------------- config fwd_dct_dct_4 ----------------
17static const int8_t fwd_shift_dct_dct_4[3] = { 2, 0, 0 };
18static const int8_t fwd_stage_range_col_dct_dct_4[4] = { 15, 16, 17, 17 };
19static const int8_t fwd_stage_range_row_dct_dct_4[4] = { 17, 18, 18, 18 };
20static const int8_t fwd_cos_bit_col_dct_dct_4[4] = { 13, 13, 13, 13 };
21static const int8_t fwd_cos_bit_row_dct_dct_4[4] = { 13, 13, 13, 13 };
22
23static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_dct_4 = {
24 4, // .txfm_size
25 4, // .stage_num_col
26 4, // .stage_num_row
27 // 0, // .log_scale
28 fwd_shift_dct_dct_4, // .shift
29 fwd_stage_range_col_dct_dct_4, // .stage_range_col
30 fwd_stage_range_row_dct_dct_4, // .stage_range_row
31 fwd_cos_bit_col_dct_dct_4, // .cos_bit_col
32 fwd_cos_bit_row_dct_dct_4, // .cos_bit_row
33 TXFM_TYPE_DCT4, // .txfm_type_col
34 TXFM_TYPE_DCT4
35}; // .txfm_type_row
36
37// ---------------- config fwd_dct_dct_8 ----------------
38static const int8_t fwd_shift_dct_dct_8[3] = { 2, -1, 0 };
39static const int8_t fwd_stage_range_col_dct_dct_8[6] = {
40 15, 16, 17, 18, 18, 18
41};
42static const int8_t fwd_stage_range_row_dct_dct_8[6] = {
43 17, 18, 19, 19, 19, 19
44};
45static const int8_t fwd_cos_bit_col_dct_dct_8[6] = { 13, 13, 13, 13, 13, 13 };
46static const int8_t fwd_cos_bit_row_dct_dct_8[6] = { 13, 13, 13, 13, 13, 13 };
47
48static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_dct_8 = {
49 8, // .txfm_size
50 6, // .stage_num_col
51 6, // .stage_num_row
52 // 0, // .log_scale
53 fwd_shift_dct_dct_8, // .shift
54 fwd_stage_range_col_dct_dct_8, // .stage_range_col
55 fwd_stage_range_row_dct_dct_8, // .stage_range_row
56 fwd_cos_bit_col_dct_dct_8, // .cos_bit_col
57 fwd_cos_bit_row_dct_dct_8, // .cos_bit_row
58 TXFM_TYPE_DCT8, // .txfm_type_col
59 TXFM_TYPE_DCT8
60}; // .txfm_type_row
61
62// ---------------- config fwd_dct_dct_16 ----------------
63static const int8_t fwd_shift_dct_dct_16[3] = { 2, -2, 0 };
64static const int8_t fwd_stage_range_col_dct_dct_16[8] = { 15, 16, 17, 18,
65 19, 19, 19, 19 };
66static const int8_t fwd_stage_range_row_dct_dct_16[8] = { 17, 18, 19, 20,
67 20, 20, 20, 20 };
68static const int8_t fwd_cos_bit_col_dct_dct_16[8] = { 13, 13, 13, 13,
69 13, 13, 13, 13 };
70static const int8_t fwd_cos_bit_row_dct_dct_16[8] = { 12, 12, 12, 12,
71 12, 12, 12, 12 };
72
73static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_dct_16 = {
74 16, // .txfm_size
75 8, // .stage_num_col
76 8, // .stage_num_row
77 // 0, // .log_scale
78 fwd_shift_dct_dct_16, // .shift
79 fwd_stage_range_col_dct_dct_16, // .stage_range_col
80 fwd_stage_range_row_dct_dct_16, // .stage_range_row
81 fwd_cos_bit_col_dct_dct_16, // .cos_bit_col
82 fwd_cos_bit_row_dct_dct_16, // .cos_bit_row
83 TXFM_TYPE_DCT16, // .txfm_type_col
84 TXFM_TYPE_DCT16
85}; // .txfm_type_row
86
87// ---------------- config fwd_dct_dct_32 ----------------
88static const int8_t fwd_shift_dct_dct_32[3] = { 2, -4, 0 };
89static const int8_t fwd_stage_range_col_dct_dct_32[10] = { 15, 16, 17, 18, 19,
90 20, 20, 20, 20, 20 };
91static const int8_t fwd_stage_range_row_dct_dct_32[10] = { 16, 17, 18, 19, 20,
92 20, 20, 20, 20, 20 };
93static const int8_t fwd_cos_bit_col_dct_dct_32[10] = { 12, 12, 12, 12, 12,
94 12, 12, 12, 12, 12 };
95static const int8_t fwd_cos_bit_row_dct_dct_32[10] = { 12, 12, 12, 12, 12,
96 12, 12, 12, 12, 12 };
97
98static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_dct_32 = {
99 32, // .txfm_size
100 10, // .stage_num_col
101 10, // .stage_num_row
102 // 1, // .log_scale
103 fwd_shift_dct_dct_32, // .shift
104 fwd_stage_range_col_dct_dct_32, // .stage_range_col
105 fwd_stage_range_row_dct_dct_32, // .stage_range_row
106 fwd_cos_bit_col_dct_dct_32, // .cos_bit_col
107 fwd_cos_bit_row_dct_dct_32, // .cos_bit_row
108 TXFM_TYPE_DCT32, // .txfm_type_col
109 TXFM_TYPE_DCT32
110}; // .txfm_type_row
111
112// ---------------- config fwd_dct_dct_64 ----------------
Debargha Mukherjee67d13472016-11-01 14:37:39 -0700[diff] [blame]113static const int8_t fwd_shift_dct_dct_64[3] = { 0, -2, -2 };
Yaowu Xuc27fc142016-08-22 16:08:15 -0700[diff] [blame]114static const int8_t fwd_stage_range_col_dct_dct_64[12] = {
115 13, 14, 15, 16, 17, 18, 19, 19, 19, 19, 19, 19
116};
117static const int8_t fwd_stage_range_row_dct_dct_64[12] = {
118 17, 18, 19, 20, 21, 22, 22, 22, 22, 22, 22, 22
119};
120static const int8_t fwd_cos_bit_col_dct_dct_64[12] = { 15, 15, 15, 15, 15, 14,
121 13, 13, 13, 13, 13, 13 };
122static const int8_t fwd_cos_bit_row_dct_dct_64[12] = { 15, 14, 13, 12, 11, 10,
123 10, 10, 10, 10, 10, 10 };
124
125static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_dct_64 = {
126 64, // .txfm_size
127 12, // .stage_num_col
128 12, // .stage_num_row
129 fwd_shift_dct_dct_64, // .shift
130 fwd_stage_range_col_dct_dct_64, // .stage_range_col
131 fwd_stage_range_row_dct_dct_64, // .stage_range_row
132 fwd_cos_bit_col_dct_dct_64, // .cos_bit_col
133 fwd_cos_bit_row_dct_dct_64, // .cos_bit_row
134 TXFM_TYPE_DCT64, // .txfm_type_col
135 TXFM_TYPE_DCT64
136}; // .txfm_type_row
137
138// ---------------- config fwd_dct_adst_4 ----------------
139static const int8_t fwd_shift_dct_adst_4[3] = { 2, 0, 0 };
140static const int8_t fwd_stage_range_col_dct_adst_4[4] = { 15, 16, 17, 17 };
141static const int8_t fwd_stage_range_row_dct_adst_4[6] = {
142 17, 17, 17, 18, 18, 18
143};
144static const int8_t fwd_cos_bit_col_dct_adst_4[4] = { 13, 13, 13, 13 };
145static const int8_t fwd_cos_bit_row_dct_adst_4[6] = { 13, 13, 13, 13, 13, 13 };
146
147static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_adst_4 = {
148 4, // .txfm_size
149 4, // .stage_num_col
150 6, // .stage_num_row
151 // 0, // .log_scale
152 fwd_shift_dct_adst_4, // .shift
153 fwd_stage_range_col_dct_adst_4, // .stage_range_col
154 fwd_stage_range_row_dct_adst_4, // .stage_range_row
155 fwd_cos_bit_col_dct_adst_4, // .cos_bit_col
156 fwd_cos_bit_row_dct_adst_4, // .cos_bit_row
157 TXFM_TYPE_DCT4, // .txfm_type_col
158 TXFM_TYPE_ADST4
159}; // .txfm_type_row
160
161// ---------------- config fwd_dct_adst_8 ----------------
162static const int8_t fwd_shift_dct_adst_8[3] = { 2, -1, 0 };
163static const int8_t fwd_stage_range_col_dct_adst_8[6] = {
164 15, 16, 17, 18, 18, 18
165};
166static const int8_t fwd_stage_range_row_dct_adst_8[8] = { 17, 17, 17, 18,
167 18, 19, 19, 19 };
168static const int8_t fwd_cos_bit_col_dct_adst_8[6] = { 13, 13, 13, 13, 13, 13 };
169static const int8_t fwd_cos_bit_row_dct_adst_8[8] = { 13, 13, 13, 13,
170 13, 13, 13, 13 };
171
172static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_adst_8 = {
173 8, // .txfm_size
174 6, // .stage_num_col
175 8, // .stage_num_row
176 // 0, // .log_scale
177 fwd_shift_dct_adst_8, // .shift
178 fwd_stage_range_col_dct_adst_8, // .stage_range_col
179 fwd_stage_range_row_dct_adst_8, // .stage_range_row
180 fwd_cos_bit_col_dct_adst_8, // .cos_bit_col
181 fwd_cos_bit_row_dct_adst_8, // .cos_bit_row
182 TXFM_TYPE_DCT8, // .txfm_type_col
183 TXFM_TYPE_ADST8
184}; // .txfm_type_row
185
186// ---------------- config fwd_dct_adst_16 ----------------
187static const int8_t fwd_shift_dct_adst_16[3] = { 2, -2, 0 };
188static const int8_t fwd_stage_range_col_dct_adst_16[8] = { 15, 16, 17, 18,
189 19, 19, 19, 19 };
190static const int8_t fwd_stage_range_row_dct_adst_16[10] = {
191 17, 17, 17, 18, 18, 19, 19, 20, 20, 20
192};
193static const int8_t fwd_cos_bit_col_dct_adst_16[8] = { 13, 13, 13, 13,
194 13, 13, 13, 13 };
195static const int8_t fwd_cos_bit_row_dct_adst_16[10] = { 12, 12, 12, 12, 12,
196 12, 12, 12, 12, 12 };
197
198static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_adst_16 = {
199 16, // .txfm_size
200 8, // .stage_num_col
201 10, // .stage_num_row
202 // 0, // .log_scale
203 fwd_shift_dct_adst_16, // .shift
204 fwd_stage_range_col_dct_adst_16, // .stage_range_col
205 fwd_stage_range_row_dct_adst_16, // .stage_range_row
206 fwd_cos_bit_col_dct_adst_16, // .cos_bit_col
207 fwd_cos_bit_row_dct_adst_16, // .cos_bit_row
208 TXFM_TYPE_DCT16, // .txfm_type_col
209 TXFM_TYPE_ADST16
210}; // .txfm_type_row
211
212// ---------------- config fwd_dct_adst_32 ----------------
213static const int8_t fwd_shift_dct_adst_32[3] = { 2, -4, 0 };
214static const int8_t fwd_stage_range_col_dct_adst_32[10] = {
215 15, 16, 17, 18, 19, 20, 20, 20, 20, 20
216};
217static const int8_t fwd_stage_range_row_dct_adst_32[12] = {
218 16, 16, 16, 17, 17, 18, 18, 19, 19, 20, 20, 20
219};
220static const int8_t fwd_cos_bit_col_dct_adst_32[10] = { 12, 12, 12, 12, 12,
221 12, 12, 12, 12, 12 };
222static const int8_t fwd_cos_bit_row_dct_adst_32[12] = {
223 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12
224};
225
226static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_adst_32 = {
227 32, // .txfm_size
228 10, // .stage_num_col
229 12, // .stage_num_row
230 // 1, // .log_scale
231 fwd_shift_dct_adst_32, // .shift
232 fwd_stage_range_col_dct_adst_32, // .stage_range_col
233 fwd_stage_range_row_dct_adst_32, // .stage_range_row
234 fwd_cos_bit_col_dct_adst_32, // .cos_bit_col
235 fwd_cos_bit_row_dct_adst_32, // .cos_bit_row
236 TXFM_TYPE_DCT32, // .txfm_type_col
237 TXFM_TYPE_ADST32
238}; // .txfm_type_row
239// ---------------- config fwd_adst_adst_4 ----------------
240static const int8_t fwd_shift_adst_adst_4[3] = { 2, 0, 0 };
241static const int8_t fwd_stage_range_col_adst_adst_4[6] = { 15, 15, 16,
242 17, 17, 17 };
243static const int8_t fwd_stage_range_row_adst_adst_4[6] = { 17, 17, 17,
244 18, 18, 18 };
245static const int8_t fwd_cos_bit_col_adst_adst_4[6] = { 13, 13, 13, 13, 13, 13 };
246static const int8_t fwd_cos_bit_row_adst_adst_4[6] = { 13, 13, 13, 13, 13, 13 };
247
248static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_adst_4 = {
249 4, // .txfm_size
250 6, // .stage_num_col
251 6, // .stage_num_row
252 // 0, // .log_scale
253 fwd_shift_adst_adst_4, // .shift
254 fwd_stage_range_col_adst_adst_4, // .stage_range_col
255 fwd_stage_range_row_adst_adst_4, // .stage_range_row
256 fwd_cos_bit_col_adst_adst_4, // .cos_bit_col
257 fwd_cos_bit_row_adst_adst_4, // .cos_bit_row
258 TXFM_TYPE_ADST4, // .txfm_type_col
259 TXFM_TYPE_ADST4
260}; // .txfm_type_row
261
262// ---------------- config fwd_adst_adst_8 ----------------
263static const int8_t fwd_shift_adst_adst_8[3] = { 2, -1, 0 };
264static const int8_t fwd_stage_range_col_adst_adst_8[8] = { 15, 15, 16, 17,
265 17, 18, 18, 18 };
266static const int8_t fwd_stage_range_row_adst_adst_8[8] = { 17, 17, 17, 18,
267 18, 19, 19, 19 };
268static const int8_t fwd_cos_bit_col_adst_adst_8[8] = { 13, 13, 13, 13,
269 13, 13, 13, 13 };
270static const int8_t fwd_cos_bit_row_adst_adst_8[8] = { 13, 13, 13, 13,
271 13, 13, 13, 13 };
272
273static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_adst_8 = {
274 8, // .txfm_size
275 8, // .stage_num_col
276 8, // .stage_num_row
277 // 0, // .log_scale
278 fwd_shift_adst_adst_8, // .shift
279 fwd_stage_range_col_adst_adst_8, // .stage_range_col
280 fwd_stage_range_row_adst_adst_8, // .stage_range_row
281 fwd_cos_bit_col_adst_adst_8, // .cos_bit_col
282 fwd_cos_bit_row_adst_adst_8, // .cos_bit_row
283 TXFM_TYPE_ADST8, // .txfm_type_col
284 TXFM_TYPE_ADST8
285}; // .txfm_type_row
286
287// ---------------- config fwd_adst_adst_16 ----------------
288static const int8_t fwd_shift_adst_adst_16[3] = { 2, -2, 0 };
289static const int8_t fwd_stage_range_col_adst_adst_16[10] = {
290 15, 15, 16, 17, 17, 18, 18, 19, 19, 19
291};
292static const int8_t fwd_stage_range_row_adst_adst_16[10] = {
293 17, 17, 17, 18, 18, 19, 19, 20, 20, 20
294};
295static const int8_t fwd_cos_bit_col_adst_adst_16[10] = { 13, 13, 13, 13, 13,
296 13, 13, 13, 13, 13 };
297static const int8_t fwd_cos_bit_row_adst_adst_16[10] = { 12, 12, 12, 12, 12,
298 12, 12, 12, 12, 12 };
299
300static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_adst_16 = {
301 16, // .txfm_size
302 10, // .stage_num_col
303 10, // .stage_num_row
304 // 0, // .log_scale
305 fwd_shift_adst_adst_16, // .shift
306 fwd_stage_range_col_adst_adst_16, // .stage_range_col
307 fwd_stage_range_row_adst_adst_16, // .stage_range_row
308 fwd_cos_bit_col_adst_adst_16, // .cos_bit_col
309 fwd_cos_bit_row_adst_adst_16, // .cos_bit_row
310 TXFM_TYPE_ADST16, // .txfm_type_col
311 TXFM_TYPE_ADST16
312}; // .txfm_type_row
313
314// ---------------- config fwd_adst_adst_32 ----------------
315static const int8_t fwd_shift_adst_adst_32[3] = { 2, -4, 0 };
316static const int8_t fwd_stage_range_col_adst_adst_32[12] = {
317 15, 15, 16, 17, 17, 18, 18, 19, 19, 20, 20, 20
318};
319static const int8_t fwd_stage_range_row_adst_adst_32[12] = {
320 16, 16, 16, 17, 17, 18, 18, 19, 19, 20, 20, 20
321};
322static const int8_t fwd_cos_bit_col_adst_adst_32[12] = {
323 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12
324};
325static const int8_t fwd_cos_bit_row_adst_adst_32[12] = {
326 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12
327};
328
329static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_adst_32 = {
330 32, // .txfm_size
331 12, // .stage_num_col
332 12, // .stage_num_row
333 // 1, // .log_scale
334 fwd_shift_adst_adst_32, // .shift
335 fwd_stage_range_col_adst_adst_32, // .stage_range_col
336 fwd_stage_range_row_adst_adst_32, // .stage_range_row
337 fwd_cos_bit_col_adst_adst_32, // .cos_bit_col
338 fwd_cos_bit_row_adst_adst_32, // .cos_bit_row
339 TXFM_TYPE_ADST32, // .txfm_type_col
340 TXFM_TYPE_ADST32
341}; // .txfm_type_row
342
343// ---------------- config fwd_adst_dct_4 ----------------
344static const int8_t fwd_shift_adst_dct_4[3] = { 2, 0, 0 };
345static const int8_t fwd_stage_range_col_adst_dct_4[6] = {
346 15, 15, 16, 17, 17, 17
347};
348static const int8_t fwd_stage_range_row_adst_dct_4[4] = { 17, 18, 18, 18 };
349static const int8_t fwd_cos_bit_col_adst_dct_4[6] = { 13, 13, 13, 13, 13, 13 };
350static const int8_t fwd_cos_bit_row_adst_dct_4[4] = { 13, 13, 13, 13 };
351
352static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_dct_4 = {
353 4, // .txfm_size
354 6, // .stage_num_col
355 4, // .stage_num_row
356 // 0, // .log_scale
357 fwd_shift_adst_dct_4, // .shift
358 fwd_stage_range_col_adst_dct_4, // .stage_range_col
359 fwd_stage_range_row_adst_dct_4, // .stage_range_row
360 fwd_cos_bit_col_adst_dct_4, // .cos_bit_col
361 fwd_cos_bit_row_adst_dct_4, // .cos_bit_row
362 TXFM_TYPE_ADST4, // .txfm_type_col
363 TXFM_TYPE_DCT4
364}; // .txfm_type_row
365
366// ---------------- config fwd_adst_dct_8 ----------------
367static const int8_t fwd_shift_adst_dct_8[3] = { 2, -1, 0 };
368static const int8_t fwd_stage_range_col_adst_dct_8[8] = { 15, 15, 16, 17,
369 17, 18, 18, 18 };
370static const int8_t fwd_stage_range_row_adst_dct_8[6] = {
371 17, 18, 19, 19, 19, 19
372};
373static const int8_t fwd_cos_bit_col_adst_dct_8[8] = { 13, 13, 13, 13,
374 13, 13, 13, 13 };
375static const int8_t fwd_cos_bit_row_adst_dct_8[6] = { 13, 13, 13, 13, 13, 13 };
376
377static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_dct_8 = {
378 8, // .txfm_size
379 8, // .stage_num_col
380 6, // .stage_num_row
381 // 0, // .log_scale
382 fwd_shift_adst_dct_8, // .shift
383 fwd_stage_range_col_adst_dct_8, // .stage_range_col
384 fwd_stage_range_row_adst_dct_8, // .stage_range_row
385 fwd_cos_bit_col_adst_dct_8, // .cos_bit_col
386 fwd_cos_bit_row_adst_dct_8, // .cos_bit_row
387 TXFM_TYPE_ADST8, // .txfm_type_col
388 TXFM_TYPE_DCT8
389}; // .txfm_type_row
390
391// ---------------- config fwd_adst_dct_16 ----------------
392static const int8_t fwd_shift_adst_dct_16[3] = { 2, -2, 0 };
393static const int8_t fwd_stage_range_col_adst_dct_16[10] = {
394 15, 15, 16, 17, 17, 18, 18, 19, 19, 19
395};
396static const int8_t fwd_stage_range_row_adst_dct_16[8] = { 17, 18, 19, 20,
397 20, 20, 20, 20 };
398static const int8_t fwd_cos_bit_col_adst_dct_16[10] = { 13, 13, 13, 13, 13,
399 13, 13, 13, 13, 13 };
400static const int8_t fwd_cos_bit_row_adst_dct_16[8] = { 12, 12, 12, 12,
401 12, 12, 12, 12 };
402
403static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_dct_16 = {
404 16, // .txfm_size
405 10, // .stage_num_col
406 8, // .stage_num_row
407 // 0, // .log_scale
408 fwd_shift_adst_dct_16, // .shift
409 fwd_stage_range_col_adst_dct_16, // .stage_range_col
410 fwd_stage_range_row_adst_dct_16, // .stage_range_row
411 fwd_cos_bit_col_adst_dct_16, // .cos_bit_col
412 fwd_cos_bit_row_adst_dct_16, // .cos_bit_row
413 TXFM_TYPE_ADST16, // .txfm_type_col
414 TXFM_TYPE_DCT16
415}; // .txfm_type_row
416
417// ---------------- config fwd_adst_dct_32 ----------------
418static const int8_t fwd_shift_adst_dct_32[3] = { 2, -4, 0 };
419static const int8_t fwd_stage_range_col_adst_dct_32[12] = {
420 15, 15, 16, 17, 17, 18, 18, 19, 19, 20, 20, 20
421};
422static const int8_t fwd_stage_range_row_adst_dct_32[10] = {
423 16, 17, 18, 19, 20, 20, 20, 20, 20, 20
424};
425static const int8_t fwd_cos_bit_col_adst_dct_32[12] = {
426 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12
427};
428static const int8_t fwd_cos_bit_row_adst_dct_32[10] = { 12, 12, 12, 12, 12,
429 12, 12, 12, 12, 12 };
430
431static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_dct_32 = {
432 32, // .txfm_size
433 12, // .stage_num_col
434 10, // .stage_num_row
435 // 1, // .log_scale
436 fwd_shift_adst_dct_32, // .shift
437 fwd_stage_range_col_adst_dct_32, // .stage_range_col
438 fwd_stage_range_row_adst_dct_32, // .stage_range_row
439 fwd_cos_bit_col_adst_dct_32, // .cos_bit_col
440 fwd_cos_bit_row_adst_dct_32, // .cos_bit_row
441 TXFM_TYPE_ADST32, // .txfm_type_col
442 TXFM_TYPE_DCT32
443}; // .txfm_type_row
Yaowu Xuf883b422016-08-30 14:01:10 -0700[diff] [blame]444#endif // AV1_FWD_TXFM2D_CFG_H_