blob: 4225c3d4c04eb5fa8d1f5afcb67a0b8443f68d9d [file] [log] [blame]
Tom Fineganc6e296e2017-04-21 11:13:15 -07001##
2## Copyright (c) 2017, Alliance for Open Media. All rights reserved
3##
4## This source code is subject to the terms of the BSD 2 Clause License and
5## the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
6## was not distributed with this source code in the LICENSE file, you can
7## obtain it at www.aomedia.org/license/software. If the Alliance for Open
8## Media Patent License 1.0 was not distributed with this source code in the
9## PATENTS file, you can obtain it at www.aomedia.org/license/patent.
10##
Tom Finegane3bae4a2017-10-12 09:06:31 -070011
12
Tom Fineganc6e296e2017-04-21 11:13:15 -070013if ("${AOM_TARGET_CPU}" STREQUAL "arm64")
14 set(ARCH_ARM 1)
Tom Fineganc6e296e2017-04-21 11:13:15 -070015 set(RTCD_ARCH_ARM "yes")
Tom Finegane3bae4a2017-10-12 09:06:31 -070016
17 if (ENABLE_NEON)
18 set(HAVE_NEON 1)
19 set(RTCD_HAVE_NEON "yes")
20 else ()
21 set(HAVE_NEON 0)
22 set(AOM_RTCD_FLAGS ${AOM_RTCD_FLAGS} --disable-neon)
23 endif ()
Tom Fineganc6e296e2017-04-21 11:13:15 -070024elseif ("${AOM_TARGET_CPU}" MATCHES "^armv7")
25 set(ARCH_ARM 1)
Tom Fineganc6e296e2017-04-21 11:13:15 -070026 set(RTCD_ARCH_ARM "yes")
Tom Finegane3bae4a2017-10-12 09:06:31 -070027
28 if (ENABLE_NEON)
29 set(HAVE_NEON 1)
30 set(RTCD_HAVE_NEON "yes")
31 else ()
32 set(HAVE_NEON 0)
33 set(AOM_RTCD_FLAGS ${AOM_RTCD_FLAGS} --disable-neon)
34 endif ()
35
36 if (ENABLE_NEON_ASM)
37 set(HAVE_NEON_ASM 1)
38 set(RTCD_HAVE_NEON_ASM "yes")
39 else ()
40 set(HAVE_NEON_ASM 0)
41 endif ()
42 set(AOM_RTCD_FLAGS ${AOM_RTCD_FLAGS} --disable-neon_asm)
Tom Fineganc6e296e2017-04-21 11:13:15 -070043elseif ("${AOM_TARGET_CPU}" MATCHES "^mips")
44 set(ARCH_MIPS 1)
Tom Finegane3bae4a2017-10-12 09:06:31 -070045 set(RTCD_ARCH_MIPS "yes")
Tom Fineganc6e296e2017-04-21 11:13:15 -070046
47 if ("${AOM_TARGET_CPU}" STREQUAL "mips32")
48 set(HAVE_MIPS32 1)
Tom Finegane3bae4a2017-10-12 09:06:31 -070049 set(RTCD_HAVE_MIPS32 "yes")
Tom Fineganc6e296e2017-04-21 11:13:15 -070050 elseif ("${AOM_TARGET_CPU}" STREQUAL "mips64")
51 set(HAVE_MIPS64 1)
Tom Finegane3bae4a2017-10-12 09:06:31 -070052 set(RTCD_HAVE_MIPS64 "yes")
Tom Fineganc6e296e2017-04-21 11:13:15 -070053 endif ()
54
Tom Finegane3bae4a2017-10-12 09:06:31 -070055 # HAVE_DSPR2 is set by mips toolchain files.
56 if (ENABLE_DSPR2 AND HAVE_DSPR2)
Tom Fineganc6e296e2017-04-21 11:13:15 -070057 set(RTCD_HAVE_DSPR2 "yes")
Tom Finegane3bae4a2017-10-12 09:06:31 -070058 else ()
59 set(HAVE_DSPR2 0)
60 set(AOM_RTCD_FLAGS ${AOM_RTCD_FLAGS} --disable-dspr2)
Tom Fineganc6e296e2017-04-21 11:13:15 -070061 endif ()
62
Tom Finegane3bae4a2017-10-12 09:06:31 -070063 # HAVE_MSA is set by mips toolchain files.
64 if (ENABLE_MSA AND HAVE_MSA)
Tom Fineganc6e296e2017-04-21 11:13:15 -070065 set(RTCD_HAVE_MSA "yes")
Tom Finegane3bae4a2017-10-12 09:06:31 -070066 else ()
67 set(HAVE_MSA 0)
68 set(AOM_RTCD_FLAGS ${AOM_RTCD_FLAGS} --disable-msa)
Tom Fineganc6e296e2017-04-21 11:13:15 -070069 endif ()
70elseif ("${AOM_TARGET_CPU}" MATCHES "^x86")
71 if ("${AOM_TARGET_CPU}" STREQUAL "x86")
72 set(ARCH_X86 1)
73 set(RTCD_ARCH_X86 "yes")
74 elseif ("${AOM_TARGET_CPU}" STREQUAL "x86_64")
75 set(ARCH_X86_64 1)
76 set(RTCD_ARCH_X86_64 "yes")
77 endif ()
78
Tom Finegane3bae4a2017-10-12 09:06:31 -070079 set(X86_FLAVORS "MMX;SSE;SSE2;SSE3;SSSE3;SSE4_1;AVX;AVX2")
80 foreach (flavor ${X86_FLAVORS})
81 if (ENABLE_${flavor} AND NOT disable_remaining_flavors)
82 set(HAVE_${flavor} 1)
83 set(RTCD_HAVE_${flavor} "yes")
84 else ()
85 set(disable_remaining_flavors 1)
86 set(HAVE_${flavor} 0)
87 string(TOLOWER ${flavor} flavor)
88 set(AOM_RTCD_FLAGS ${AOM_RTCD_FLAGS} --disable-${flavor})
89 endif ()
90 endforeach ()
Tom Fineganc6e296e2017-04-21 11:13:15 -070091endif ()
92
93foreach (config_var ${AOM_CONFIG_VARS})
94 if (${${config_var}})
95 set(RTCD_${config_var} yes)
96 endif ()
97endforeach ()