Xing Jin | 0a165c4 | 2018-07-18 17:53:37 +0800 | [diff] [blame] | 1 | /* |
Lester Lu | 6bc30d6 | 2021-12-16 19:13:21 +0000 | [diff] [blame^] | 2 | * Copyright (c) 2021, Alliance for Open Media. All rights reserved |
Xing Jin | 0a165c4 | 2018-07-18 17:53:37 +0800 | [diff] [blame] | 3 | * |
Lester Lu | 6bc30d6 | 2021-12-16 19:13:21 +0000 | [diff] [blame^] | 4 | * This source code is subject to the terms of the BSD 3-Clause Clear License |
| 5 | * and the Alliance for Open Media Patent License 1.0. If the BSD 3-Clause Clear |
| 6 | * License was not distributed with this source code in the LICENSE file, you |
| 7 | * can obtain it at aomedia.org/license/software-license/bsd-3-c-c/. If the |
| 8 | * Alliance for Open Media Patent License 1.0 was not distributed with this |
| 9 | * source code in the PATENTS file, you can obtain it at |
| 10 | * aomedia.org/license/patent-license/. |
Xing Jin | 0a165c4 | 2018-07-18 17:53:37 +0800 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #include <smmintrin.h> // SSE4.1 |
| 14 | #include <immintrin.h> // AVX2 |
| 15 | |
| 16 | #include <assert.h> |
| 17 | |
| 18 | #include "aom/aom_integer.h" |
| 19 | #include "aom_ports/mem.h" |
| 20 | #include "aom_dsp/aom_dsp_common.h" |
| 21 | |
| 22 | #include "aom_dsp/x86/synonyms.h" |
| 23 | #include "aom_dsp/x86/synonyms_avx2.h" |
Xing Jin | de2b711 | 2018-08-08 19:44:15 +0800 | [diff] [blame] | 24 | #include "aom_dsp/x86/blend_sse4.h" |
Xing Jin | 0a165c4 | 2018-07-18 17:53:37 +0800 | [diff] [blame] | 25 | #include "aom_dsp/x86/blend_mask_sse4.h" |
| 26 | |
| 27 | #include "config/aom_dsp_rtcd.h" |
| 28 | |
| 29 | static INLINE void blend_a64_d16_mask_w16_avx2( |
| 30 | uint8_t *dst, const CONV_BUF_TYPE *src0, const CONV_BUF_TYPE *src1, |
| 31 | const __m256i *m0, const __m256i *v_round_offset, const __m256i *v_maxval, |
| 32 | int shift) { |
| 33 | const __m256i max_minus_m0 = _mm256_sub_epi16(*v_maxval, *m0); |
| 34 | const __m256i s0_0 = yy_loadu_256(src0); |
| 35 | const __m256i s1_0 = yy_loadu_256(src1); |
| 36 | __m256i res0_lo = _mm256_madd_epi16(_mm256_unpacklo_epi16(s0_0, s1_0), |
| 37 | _mm256_unpacklo_epi16(*m0, max_minus_m0)); |
| 38 | __m256i res0_hi = _mm256_madd_epi16(_mm256_unpackhi_epi16(s0_0, s1_0), |
| 39 | _mm256_unpackhi_epi16(*m0, max_minus_m0)); |
| 40 | res0_lo = |
| 41 | _mm256_srai_epi32(_mm256_sub_epi32(res0_lo, *v_round_offset), shift); |
| 42 | res0_hi = |
| 43 | _mm256_srai_epi32(_mm256_sub_epi32(res0_hi, *v_round_offset), shift); |
| 44 | const __m256i res0 = _mm256_packs_epi32(res0_lo, res0_hi); |
| 45 | __m256i res = _mm256_packus_epi16(res0, res0); |
| 46 | res = _mm256_permute4x64_epi64(res, 0xd8); |
| 47 | _mm_storeu_si128((__m128i *)(dst), _mm256_castsi256_si128(res)); |
| 48 | } |
| 49 | |
| 50 | static INLINE void blend_a64_d16_mask_w32_avx2( |
| 51 | uint8_t *dst, const CONV_BUF_TYPE *src0, const CONV_BUF_TYPE *src1, |
| 52 | const __m256i *m0, const __m256i *m1, const __m256i *v_round_offset, |
| 53 | const __m256i *v_maxval, int shift) { |
| 54 | const __m256i max_minus_m0 = _mm256_sub_epi16(*v_maxval, *m0); |
| 55 | const __m256i max_minus_m1 = _mm256_sub_epi16(*v_maxval, *m1); |
| 56 | const __m256i s0_0 = yy_loadu_256(src0); |
| 57 | const __m256i s0_1 = yy_loadu_256(src0 + 16); |
| 58 | const __m256i s1_0 = yy_loadu_256(src1); |
| 59 | const __m256i s1_1 = yy_loadu_256(src1 + 16); |
| 60 | __m256i res0_lo = _mm256_madd_epi16(_mm256_unpacklo_epi16(s0_0, s1_0), |
| 61 | _mm256_unpacklo_epi16(*m0, max_minus_m0)); |
| 62 | __m256i res0_hi = _mm256_madd_epi16(_mm256_unpackhi_epi16(s0_0, s1_0), |
| 63 | _mm256_unpackhi_epi16(*m0, max_minus_m0)); |
| 64 | __m256i res1_lo = _mm256_madd_epi16(_mm256_unpacklo_epi16(s0_1, s1_1), |
| 65 | _mm256_unpacklo_epi16(*m1, max_minus_m1)); |
| 66 | __m256i res1_hi = _mm256_madd_epi16(_mm256_unpackhi_epi16(s0_1, s1_1), |
| 67 | _mm256_unpackhi_epi16(*m1, max_minus_m1)); |
| 68 | res0_lo = |
| 69 | _mm256_srai_epi32(_mm256_sub_epi32(res0_lo, *v_round_offset), shift); |
| 70 | res0_hi = |
| 71 | _mm256_srai_epi32(_mm256_sub_epi32(res0_hi, *v_round_offset), shift); |
| 72 | res1_lo = |
| 73 | _mm256_srai_epi32(_mm256_sub_epi32(res1_lo, *v_round_offset), shift); |
| 74 | res1_hi = |
| 75 | _mm256_srai_epi32(_mm256_sub_epi32(res1_hi, *v_round_offset), shift); |
| 76 | const __m256i res0 = _mm256_packs_epi32(res0_lo, res0_hi); |
| 77 | const __m256i res1 = _mm256_packs_epi32(res1_lo, res1_hi); |
| 78 | __m256i res = _mm256_packus_epi16(res0, res1); |
| 79 | res = _mm256_permute4x64_epi64(res, 0xd8); |
| 80 | _mm256_storeu_si256((__m256i *)(dst), res); |
| 81 | } |
| 82 | |
| 83 | static INLINE void lowbd_blend_a64_d16_mask_subw0_subh0_w16_avx2( |
| 84 | uint8_t *dst, uint32_t dst_stride, const CONV_BUF_TYPE *src0, |
| 85 | uint32_t src0_stride, const CONV_BUF_TYPE *src1, uint32_t src1_stride, |
| 86 | const uint8_t *mask, uint32_t mask_stride, int h, |
| 87 | const __m256i *round_offset, int shift) { |
| 88 | const __m256i v_maxval = _mm256_set1_epi16(AOM_BLEND_A64_MAX_ALPHA); |
| 89 | for (int i = 0; i < h; ++i) { |
| 90 | const __m128i m = xx_loadu_128(mask); |
| 91 | const __m256i m0 = _mm256_cvtepu8_epi16(m); |
| 92 | |
| 93 | blend_a64_d16_mask_w16_avx2(dst, src0, src1, &m0, round_offset, &v_maxval, |
| 94 | shift); |
| 95 | mask += mask_stride; |
| 96 | dst += dst_stride; |
| 97 | src0 += src0_stride; |
| 98 | src1 += src1_stride; |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | static INLINE void lowbd_blend_a64_d16_mask_subw0_subh0_w32_avx2( |
| 103 | uint8_t *dst, uint32_t dst_stride, const CONV_BUF_TYPE *src0, |
| 104 | uint32_t src0_stride, const CONV_BUF_TYPE *src1, uint32_t src1_stride, |
| 105 | const uint8_t *mask, uint32_t mask_stride, int h, int w, |
| 106 | const __m256i *round_offset, int shift) { |
| 107 | const __m256i v_maxval = _mm256_set1_epi16(AOM_BLEND_A64_MAX_ALPHA); |
| 108 | for (int i = 0; i < h; ++i) { |
| 109 | for (int j = 0; j < w; j += 32) { |
| 110 | const __m256i m = yy_loadu_256(mask + j); |
| 111 | const __m256i m0 = _mm256_cvtepu8_epi16(_mm256_castsi256_si128(m)); |
| 112 | const __m256i m1 = _mm256_cvtepu8_epi16(_mm256_extracti128_si256(m, 1)); |
| 113 | |
| 114 | blend_a64_d16_mask_w32_avx2(dst + j, src0 + j, src1 + j, &m0, &m1, |
| 115 | round_offset, &v_maxval, shift); |
| 116 | } |
| 117 | mask += mask_stride; |
| 118 | dst += dst_stride; |
| 119 | src0 += src0_stride; |
| 120 | src1 += src1_stride; |
| 121 | } |
| 122 | } |
| 123 | |
| 124 | static INLINE void lowbd_blend_a64_d16_mask_subw1_subh1_w16_avx2( |
| 125 | uint8_t *dst, uint32_t dst_stride, const CONV_BUF_TYPE *src0, |
| 126 | uint32_t src0_stride, const CONV_BUF_TYPE *src1, uint32_t src1_stride, |
| 127 | const uint8_t *mask, uint32_t mask_stride, int h, |
| 128 | const __m256i *round_offset, int shift) { |
| 129 | const __m256i v_maxval = _mm256_set1_epi16(AOM_BLEND_A64_MAX_ALPHA); |
| 130 | const __m256i one_b = _mm256_set1_epi8(1); |
| 131 | const __m256i two_w = _mm256_set1_epi16(2); |
| 132 | for (int i = 0; i < h; ++i) { |
| 133 | const __m256i m_i00 = yy_loadu_256(mask); |
| 134 | const __m256i m_i10 = yy_loadu_256(mask + mask_stride); |
| 135 | |
| 136 | const __m256i m0_ac = _mm256_adds_epu8(m_i00, m_i10); |
| 137 | const __m256i m0_acbd = _mm256_maddubs_epi16(m0_ac, one_b); |
| 138 | const __m256i m0 = _mm256_srli_epi16(_mm256_add_epi16(m0_acbd, two_w), 2); |
| 139 | |
| 140 | blend_a64_d16_mask_w16_avx2(dst, src0, src1, &m0, round_offset, &v_maxval, |
| 141 | shift); |
| 142 | mask += mask_stride << 1; |
| 143 | dst += dst_stride; |
| 144 | src0 += src0_stride; |
| 145 | src1 += src1_stride; |
| 146 | } |
| 147 | } |
| 148 | |
| 149 | static INLINE void lowbd_blend_a64_d16_mask_subw1_subh1_w32_avx2( |
| 150 | uint8_t *dst, uint32_t dst_stride, const CONV_BUF_TYPE *src0, |
| 151 | uint32_t src0_stride, const CONV_BUF_TYPE *src1, uint32_t src1_stride, |
| 152 | const uint8_t *mask, uint32_t mask_stride, int h, int w, |
| 153 | const __m256i *round_offset, int shift) { |
| 154 | const __m256i v_maxval = _mm256_set1_epi16(AOM_BLEND_A64_MAX_ALPHA); |
| 155 | const __m256i one_b = _mm256_set1_epi8(1); |
| 156 | const __m256i two_w = _mm256_set1_epi16(2); |
| 157 | for (int i = 0; i < h; ++i) { |
| 158 | for (int j = 0; j < w; j += 32) { |
| 159 | const __m256i m_i00 = yy_loadu_256(mask + 2 * j); |
| 160 | const __m256i m_i01 = yy_loadu_256(mask + 2 * j + 32); |
| 161 | const __m256i m_i10 = yy_loadu_256(mask + mask_stride + 2 * j); |
| 162 | const __m256i m_i11 = yy_loadu_256(mask + mask_stride + 2 * j + 32); |
| 163 | |
| 164 | const __m256i m0_ac = _mm256_adds_epu8(m_i00, m_i10); |
| 165 | const __m256i m1_ac = _mm256_adds_epu8(m_i01, m_i11); |
| 166 | const __m256i m0_acbd = _mm256_maddubs_epi16(m0_ac, one_b); |
| 167 | const __m256i m1_acbd = _mm256_maddubs_epi16(m1_ac, one_b); |
| 168 | const __m256i m0 = _mm256_srli_epi16(_mm256_add_epi16(m0_acbd, two_w), 2); |
| 169 | const __m256i m1 = _mm256_srli_epi16(_mm256_add_epi16(m1_acbd, two_w), 2); |
| 170 | |
| 171 | blend_a64_d16_mask_w32_avx2(dst + j, src0 + j, src1 + j, &m0, &m1, |
| 172 | round_offset, &v_maxval, shift); |
| 173 | } |
| 174 | mask += mask_stride << 1; |
| 175 | dst += dst_stride; |
| 176 | src0 += src0_stride; |
| 177 | src1 += src1_stride; |
| 178 | } |
| 179 | } |
| 180 | |
| 181 | static INLINE void lowbd_blend_a64_d16_mask_subw1_subh0_w16_avx2( |
| 182 | uint8_t *dst, uint32_t dst_stride, const CONV_BUF_TYPE *src0, |
| 183 | uint32_t src0_stride, const CONV_BUF_TYPE *src1, uint32_t src1_stride, |
| 184 | const uint8_t *mask, uint32_t mask_stride, int h, int w, |
| 185 | const __m256i *round_offset, int shift) { |
| 186 | const __m256i v_maxval = _mm256_set1_epi16(AOM_BLEND_A64_MAX_ALPHA); |
| 187 | const __m256i one_b = _mm256_set1_epi8(1); |
| 188 | const __m256i zeros = _mm256_setzero_si256(); |
| 189 | for (int i = 0; i < h; ++i) { |
| 190 | for (int j = 0; j < w; j += 16) { |
| 191 | const __m256i m_i00 = yy_loadu_256(mask + 2 * j); |
| 192 | const __m256i m0_ac = _mm256_maddubs_epi16(m_i00, one_b); |
| 193 | const __m256i m0 = _mm256_avg_epu16(m0_ac, zeros); |
| 194 | |
| 195 | blend_a64_d16_mask_w16_avx2(dst + j, src0 + j, src1 + j, &m0, |
| 196 | round_offset, &v_maxval, shift); |
| 197 | } |
| 198 | mask += mask_stride; |
| 199 | dst += dst_stride; |
| 200 | src0 += src0_stride; |
| 201 | src1 += src1_stride; |
| 202 | } |
| 203 | } |
| 204 | |
| 205 | static INLINE void lowbd_blend_a64_d16_mask_subw1_subh0_w32_avx2( |
| 206 | uint8_t *dst, uint32_t dst_stride, const CONV_BUF_TYPE *src0, |
| 207 | uint32_t src0_stride, const CONV_BUF_TYPE *src1, uint32_t src1_stride, |
| 208 | const uint8_t *mask, uint32_t mask_stride, int h, int w, |
| 209 | const __m256i *round_offset, int shift) { |
| 210 | const __m256i v_maxval = _mm256_set1_epi16(AOM_BLEND_A64_MAX_ALPHA); |
| 211 | const __m256i one_b = _mm256_set1_epi8(1); |
| 212 | const __m256i zeros = _mm256_setzero_si256(); |
| 213 | for (int i = 0; i < h; ++i) { |
| 214 | for (int j = 0; j < w; j += 32) { |
| 215 | const __m256i m_i00 = yy_loadu_256(mask + 2 * j); |
| 216 | const __m256i m_i01 = yy_loadu_256(mask + 2 * j + 32); |
| 217 | const __m256i m0_ac = _mm256_maddubs_epi16(m_i00, one_b); |
| 218 | const __m256i m1_ac = _mm256_maddubs_epi16(m_i01, one_b); |
| 219 | const __m256i m0 = _mm256_avg_epu16(m0_ac, zeros); |
| 220 | const __m256i m1 = _mm256_avg_epu16(m1_ac, zeros); |
| 221 | |
| 222 | blend_a64_d16_mask_w32_avx2(dst + j, src0 + j, src1 + j, &m0, &m1, |
| 223 | round_offset, &v_maxval, shift); |
| 224 | } |
| 225 | mask += mask_stride; |
| 226 | dst += dst_stride; |
| 227 | src0 += src0_stride; |
| 228 | src1 += src1_stride; |
| 229 | } |
| 230 | } |
| 231 | |
| 232 | static INLINE void lowbd_blend_a64_d16_mask_subw0_subh1_w16_avx2( |
| 233 | uint8_t *dst, uint32_t dst_stride, const CONV_BUF_TYPE *src0, |
| 234 | uint32_t src0_stride, const CONV_BUF_TYPE *src1, uint32_t src1_stride, |
| 235 | const uint8_t *mask, uint32_t mask_stride, int h, int w, |
| 236 | const __m256i *round_offset, int shift) { |
| 237 | const __m256i v_maxval = _mm256_set1_epi16(AOM_BLEND_A64_MAX_ALPHA); |
| 238 | const __m128i zeros = _mm_setzero_si128(); |
| 239 | for (int i = 0; i < h; ++i) { |
| 240 | for (int j = 0; j < w; j += 16) { |
| 241 | const __m128i m_i00 = xx_loadu_128(mask + j); |
| 242 | const __m128i m_i10 = xx_loadu_128(mask + mask_stride + j); |
| 243 | |
| 244 | const __m128i m_ac = _mm_avg_epu8(_mm_adds_epu8(m_i00, m_i10), zeros); |
| 245 | const __m256i m0 = _mm256_cvtepu8_epi16(m_ac); |
| 246 | |
| 247 | blend_a64_d16_mask_w16_avx2(dst + j, src0 + j, src1 + j, &m0, |
| 248 | round_offset, &v_maxval, shift); |
| 249 | } |
| 250 | mask += mask_stride << 1; |
| 251 | dst += dst_stride; |
| 252 | src0 += src0_stride; |
| 253 | src1 += src1_stride; |
| 254 | } |
| 255 | } |
| 256 | |
| 257 | static INLINE void lowbd_blend_a64_d16_mask_subw0_subh1_w32_avx2( |
| 258 | uint8_t *dst, uint32_t dst_stride, const CONV_BUF_TYPE *src0, |
| 259 | uint32_t src0_stride, const CONV_BUF_TYPE *src1, uint32_t src1_stride, |
| 260 | const uint8_t *mask, uint32_t mask_stride, int h, int w, |
| 261 | const __m256i *round_offset, int shift) { |
| 262 | const __m256i v_maxval = _mm256_set1_epi16(AOM_BLEND_A64_MAX_ALPHA); |
| 263 | const __m256i zeros = _mm256_setzero_si256(); |
| 264 | for (int i = 0; i < h; ++i) { |
| 265 | for (int j = 0; j < w; j += 32) { |
| 266 | const __m256i m_i00 = yy_loadu_256(mask + j); |
| 267 | const __m256i m_i10 = yy_loadu_256(mask + mask_stride + j); |
| 268 | |
| 269 | const __m256i m_ac = |
| 270 | _mm256_avg_epu8(_mm256_adds_epu8(m_i00, m_i10), zeros); |
| 271 | const __m256i m0 = _mm256_cvtepu8_epi16(_mm256_castsi256_si128(m_ac)); |
| 272 | const __m256i m1 = |
| 273 | _mm256_cvtepu8_epi16(_mm256_extracti128_si256(m_ac, 1)); |
| 274 | |
| 275 | blend_a64_d16_mask_w32_avx2(dst + j, src0 + j, src1 + j, &m0, &m1, |
| 276 | round_offset, &v_maxval, shift); |
| 277 | } |
| 278 | mask += mask_stride << 1; |
| 279 | dst += dst_stride; |
| 280 | src0 += src0_stride; |
| 281 | src1 += src1_stride; |
| 282 | } |
| 283 | } |
| 284 | |
| 285 | void aom_lowbd_blend_a64_d16_mask_avx2( |
| 286 | uint8_t *dst, uint32_t dst_stride, const CONV_BUF_TYPE *src0, |
| 287 | uint32_t src0_stride, const CONV_BUF_TYPE *src1, uint32_t src1_stride, |
| 288 | const uint8_t *mask, uint32_t mask_stride, int w, int h, int subw, int subh, |
| 289 | ConvolveParams *conv_params) { |
| 290 | const int bd = 8; |
| 291 | const int round_bits = |
| 292 | 2 * FILTER_BITS - conv_params->round_0 - conv_params->round_1; |
| 293 | |
| 294 | const int round_offset = |
| 295 | ((1 << (round_bits + bd)) + (1 << (round_bits + bd - 1)) - |
| 296 | (1 << (round_bits - 1))) |
| 297 | << AOM_BLEND_A64_ROUND_BITS; |
| 298 | |
| 299 | const int shift = round_bits + AOM_BLEND_A64_ROUND_BITS; |
| 300 | assert(IMPLIES((void *)src0 == dst, src0_stride == dst_stride)); |
| 301 | assert(IMPLIES((void *)src1 == dst, src1_stride == dst_stride)); |
| 302 | |
| 303 | assert(h >= 4); |
| 304 | assert(w >= 4); |
| 305 | assert(IS_POWER_OF_TWO(h)); |
| 306 | assert(IS_POWER_OF_TWO(w)); |
| 307 | const __m128i v_round_offset = _mm_set1_epi32(round_offset); |
| 308 | const __m256i y_round_offset = _mm256_set1_epi32(round_offset); |
| 309 | |
| 310 | if (subw == 0 && subh == 0) { |
| 311 | switch (w) { |
| 312 | case 4: |
| 313 | aom_lowbd_blend_a64_d16_mask_subw0_subh0_w4_sse4_1( |
| 314 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 315 | mask_stride, h, &v_round_offset, shift); |
| 316 | break; |
| 317 | case 8: |
| 318 | aom_lowbd_blend_a64_d16_mask_subw0_subh0_w8_sse4_1( |
| 319 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 320 | mask_stride, h, &v_round_offset, shift); |
| 321 | break; |
| 322 | case 16: |
| 323 | lowbd_blend_a64_d16_mask_subw0_subh0_w16_avx2( |
| 324 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 325 | mask_stride, h, &y_round_offset, shift); |
| 326 | break; |
| 327 | default: |
| 328 | lowbd_blend_a64_d16_mask_subw0_subh0_w32_avx2( |
| 329 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 330 | mask_stride, h, w, &y_round_offset, shift); |
| 331 | break; |
| 332 | } |
| 333 | } else if (subw == 1 && subh == 1) { |
| 334 | switch (w) { |
| 335 | case 4: |
| 336 | aom_lowbd_blend_a64_d16_mask_subw1_subh1_w4_sse4_1( |
| 337 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 338 | mask_stride, h, &v_round_offset, shift); |
| 339 | break; |
| 340 | case 8: |
| 341 | aom_lowbd_blend_a64_d16_mask_subw1_subh1_w8_sse4_1( |
| 342 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 343 | mask_stride, h, &v_round_offset, shift); |
| 344 | break; |
| 345 | case 16: |
| 346 | lowbd_blend_a64_d16_mask_subw1_subh1_w16_avx2( |
| 347 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 348 | mask_stride, h, &y_round_offset, shift); |
| 349 | break; |
| 350 | default: |
| 351 | lowbd_blend_a64_d16_mask_subw1_subh1_w32_avx2( |
| 352 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 353 | mask_stride, h, w, &y_round_offset, shift); |
| 354 | break; |
| 355 | } |
| 356 | } else if (subw == 1 && subh == 0) { |
| 357 | switch (w) { |
| 358 | case 4: |
| 359 | aom_lowbd_blend_a64_d16_mask_subw1_subh0_w4_sse4_1( |
| 360 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 361 | mask_stride, h, &v_round_offset, shift); |
| 362 | break; |
| 363 | case 8: |
| 364 | aom_lowbd_blend_a64_d16_mask_subw1_subh0_w8_sse4_1( |
| 365 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 366 | mask_stride, h, &v_round_offset, shift); |
| 367 | break; |
| 368 | case 16: |
| 369 | lowbd_blend_a64_d16_mask_subw1_subh0_w16_avx2( |
| 370 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 371 | mask_stride, h, w, &y_round_offset, shift); |
| 372 | break; |
| 373 | default: |
| 374 | lowbd_blend_a64_d16_mask_subw1_subh0_w32_avx2( |
| 375 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 376 | mask_stride, h, w, &y_round_offset, shift); |
| 377 | break; |
| 378 | } |
| 379 | } else { |
| 380 | switch (w) { |
| 381 | case 4: |
| 382 | aom_lowbd_blend_a64_d16_mask_subw0_subh1_w4_sse4_1( |
| 383 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 384 | mask_stride, h, &v_round_offset, shift); |
| 385 | break; |
| 386 | case 8: |
| 387 | aom_lowbd_blend_a64_d16_mask_subw0_subh1_w8_sse4_1( |
| 388 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 389 | mask_stride, h, &v_round_offset, shift); |
| 390 | break; |
| 391 | case 16: |
| 392 | lowbd_blend_a64_d16_mask_subw0_subh1_w16_avx2( |
| 393 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 394 | mask_stride, h, w, &y_round_offset, shift); |
| 395 | break; |
| 396 | default: |
| 397 | lowbd_blend_a64_d16_mask_subw0_subh1_w32_avx2( |
| 398 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 399 | mask_stride, h, w, &y_round_offset, shift); |
| 400 | break; |
| 401 | } |
| 402 | } |
| 403 | } |
Xing Jin | de2b711 | 2018-08-08 19:44:15 +0800 | [diff] [blame] | 404 | |
| 405 | static INLINE __m256i blend_16_u8_avx2(const uint8_t *src0, const uint8_t *src1, |
| 406 | const __m256i *v_m0_b, |
| 407 | const __m256i *v_m1_b, |
| 408 | const int32_t bits) { |
| 409 | const __m256i v_s0_b = _mm256_castsi128_si256(xx_loadu_128(src0)); |
| 410 | const __m256i v_s1_b = _mm256_castsi128_si256(xx_loadu_128(src1)); |
| 411 | const __m256i v_s0_s_b = _mm256_permute4x64_epi64(v_s0_b, 0xd8); |
| 412 | const __m256i v_s1_s_b = _mm256_permute4x64_epi64(v_s1_b, 0xd8); |
| 413 | |
| 414 | const __m256i v_p0_w = |
| 415 | _mm256_maddubs_epi16(_mm256_unpacklo_epi8(v_s0_s_b, v_s1_s_b), |
| 416 | _mm256_unpacklo_epi8(*v_m0_b, *v_m1_b)); |
| 417 | |
| 418 | const __m256i v_res0_w = yy_roundn_epu16(v_p0_w, bits); |
| 419 | const __m256i v_res_b = _mm256_packus_epi16(v_res0_w, v_res0_w); |
| 420 | const __m256i v_res = _mm256_permute4x64_epi64(v_res_b, 0xd8); |
| 421 | return v_res; |
| 422 | } |
| 423 | |
| 424 | static INLINE __m256i blend_32_u8_avx2(const uint8_t *src0, const uint8_t *src1, |
| 425 | const __m256i *v_m0_b, |
| 426 | const __m256i *v_m1_b, |
| 427 | const int32_t bits) { |
| 428 | const __m256i v_s0_b = yy_loadu_256(src0); |
| 429 | const __m256i v_s1_b = yy_loadu_256(src1); |
| 430 | |
| 431 | const __m256i v_p0_w = |
| 432 | _mm256_maddubs_epi16(_mm256_unpacklo_epi8(v_s0_b, v_s1_b), |
| 433 | _mm256_unpacklo_epi8(*v_m0_b, *v_m1_b)); |
| 434 | const __m256i v_p1_w = |
| 435 | _mm256_maddubs_epi16(_mm256_unpackhi_epi8(v_s0_b, v_s1_b), |
| 436 | _mm256_unpackhi_epi8(*v_m0_b, *v_m1_b)); |
| 437 | |
| 438 | const __m256i v_res0_w = yy_roundn_epu16(v_p0_w, bits); |
| 439 | const __m256i v_res1_w = yy_roundn_epu16(v_p1_w, bits); |
| 440 | const __m256i v_res = _mm256_packus_epi16(v_res0_w, v_res1_w); |
| 441 | return v_res; |
| 442 | } |
| 443 | |
| 444 | static INLINE void blend_a64_mask_sx_sy_w16_avx2( |
| 445 | uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, |
| 446 | uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, |
| 447 | const uint8_t *mask, uint32_t mask_stride, int h) { |
| 448 | const __m256i v_zmask_b = _mm256_set1_epi16(0xFF); |
| 449 | const __m256i v_maxval_b = _mm256_set1_epi8(AOM_BLEND_A64_MAX_ALPHA); |
| 450 | do { |
| 451 | const __m256i v_ral_b = yy_loadu_256(mask); |
| 452 | const __m256i v_rbl_b = yy_loadu_256(mask + mask_stride); |
| 453 | const __m256i v_rvsl_b = _mm256_add_epi8(v_ral_b, v_rbl_b); |
| 454 | const __m256i v_rvsal_w = _mm256_and_si256(v_rvsl_b, v_zmask_b); |
| 455 | const __m256i v_rvsbl_w = |
| 456 | _mm256_and_si256(_mm256_srli_si256(v_rvsl_b, 1), v_zmask_b); |
| 457 | const __m256i v_rsl_w = _mm256_add_epi16(v_rvsal_w, v_rvsbl_w); |
| 458 | |
| 459 | const __m256i v_m0_w = yy_roundn_epu16(v_rsl_w, 2); |
| 460 | const __m256i v_m0_b = _mm256_packus_epi16(v_m0_w, v_m0_w); |
| 461 | const __m256i v_m1_b = _mm256_sub_epi8(v_maxval_b, v_m0_b); |
| 462 | |
| 463 | const __m256i y_res_b = blend_16_u8_avx2(src0, src1, &v_m0_b, &v_m1_b, |
| 464 | AOM_BLEND_A64_ROUND_BITS); |
| 465 | |
| 466 | xx_storeu_128(dst, _mm256_castsi256_si128(y_res_b)); |
| 467 | dst += dst_stride; |
| 468 | src0 += src0_stride; |
| 469 | src1 += src1_stride; |
| 470 | mask += 2 * mask_stride; |
| 471 | } while (--h); |
| 472 | } |
| 473 | |
| 474 | static INLINE void blend_a64_mask_sx_sy_w32n_avx2( |
| 475 | uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, |
| 476 | uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, |
| 477 | const uint8_t *mask, uint32_t mask_stride, int w, int h) { |
| 478 | const __m256i v_maxval_b = _mm256_set1_epi8(AOM_BLEND_A64_MAX_ALPHA); |
| 479 | const __m256i v_zmask_b = _mm256_set1_epi16(0xFF); |
| 480 | do { |
| 481 | int c; |
| 482 | for (c = 0; c < w; c += 32) { |
| 483 | const __m256i v_ral_b = yy_loadu_256(mask + 2 * c); |
| 484 | const __m256i v_rah_b = yy_loadu_256(mask + 2 * c + 32); |
| 485 | const __m256i v_rbl_b = yy_loadu_256(mask + mask_stride + 2 * c); |
| 486 | const __m256i v_rbh_b = yy_loadu_256(mask + mask_stride + 2 * c + 32); |
| 487 | const __m256i v_rvsl_b = _mm256_add_epi8(v_ral_b, v_rbl_b); |
| 488 | const __m256i v_rvsh_b = _mm256_add_epi8(v_rah_b, v_rbh_b); |
| 489 | const __m256i v_rvsal_w = _mm256_and_si256(v_rvsl_b, v_zmask_b); |
| 490 | const __m256i v_rvsah_w = _mm256_and_si256(v_rvsh_b, v_zmask_b); |
| 491 | const __m256i v_rvsbl_w = |
| 492 | _mm256_and_si256(_mm256_srli_si256(v_rvsl_b, 1), v_zmask_b); |
| 493 | const __m256i v_rvsbh_w = |
| 494 | _mm256_and_si256(_mm256_srli_si256(v_rvsh_b, 1), v_zmask_b); |
| 495 | const __m256i v_rsl_w = _mm256_add_epi16(v_rvsal_w, v_rvsbl_w); |
| 496 | const __m256i v_rsh_w = _mm256_add_epi16(v_rvsah_w, v_rvsbh_w); |
| 497 | |
| 498 | const __m256i v_m0l_w = yy_roundn_epu16(v_rsl_w, 2); |
| 499 | const __m256i v_m0h_w = yy_roundn_epu16(v_rsh_w, 2); |
| 500 | const __m256i v_m0_b = |
| 501 | _mm256_permute4x64_epi64(_mm256_packus_epi16(v_m0l_w, v_m0h_w), 0xd8); |
| 502 | const __m256i v_m1_b = _mm256_sub_epi8(v_maxval_b, v_m0_b); |
| 503 | |
| 504 | const __m256i v_res_b = blend_32_u8_avx2( |
| 505 | src0 + c, src1 + c, &v_m0_b, &v_m1_b, AOM_BLEND_A64_ROUND_BITS); |
| 506 | |
| 507 | yy_storeu_256(dst + c, v_res_b); |
| 508 | } |
| 509 | dst += dst_stride; |
| 510 | src0 += src0_stride; |
| 511 | src1 += src1_stride; |
| 512 | mask += 2 * mask_stride; |
| 513 | } while (--h); |
| 514 | } |
| 515 | |
| 516 | static INLINE void blend_a64_mask_sx_sy_avx2( |
| 517 | uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, |
| 518 | uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, |
| 519 | const uint8_t *mask, uint32_t mask_stride, int w, int h) { |
| 520 | const __m128i v_shuffle_b = xx_loadu_128(g_blend_a64_mask_shuffle); |
| 521 | const __m128i v_maxval_b = _mm_set1_epi8(AOM_BLEND_A64_MAX_ALPHA); |
| 522 | const __m128i _r = _mm_set1_epi16(1 << (15 - AOM_BLEND_A64_ROUND_BITS)); |
| 523 | switch (w) { |
| 524 | case 4: |
| 525 | do { |
| 526 | const __m128i v_ra_b = xx_loadl_64(mask); |
| 527 | const __m128i v_rb_b = xx_loadl_64(mask + mask_stride); |
| 528 | const __m128i v_rvs_b = _mm_add_epi8(v_ra_b, v_rb_b); |
| 529 | const __m128i v_r_s_b = _mm_shuffle_epi8(v_rvs_b, v_shuffle_b); |
| 530 | const __m128i v_r0_s_w = _mm_cvtepu8_epi16(v_r_s_b); |
| 531 | const __m128i v_r1_s_w = _mm_cvtepu8_epi16(_mm_srli_si128(v_r_s_b, 8)); |
| 532 | const __m128i v_rs_w = _mm_add_epi16(v_r0_s_w, v_r1_s_w); |
| 533 | const __m128i v_m0_w = xx_roundn_epu16(v_rs_w, 2); |
| 534 | const __m128i v_m0_b = _mm_packus_epi16(v_m0_w, v_m0_w); |
| 535 | const __m128i v_m1_b = _mm_sub_epi8(v_maxval_b, v_m0_b); |
| 536 | |
| 537 | const __m128i v_res_b = blend_4_u8(src0, src1, &v_m0_b, &v_m1_b, &_r); |
| 538 | |
| 539 | xx_storel_32(dst, v_res_b); |
| 540 | |
| 541 | dst += dst_stride; |
| 542 | src0 += src0_stride; |
| 543 | src1 += src1_stride; |
| 544 | mask += 2 * mask_stride; |
| 545 | } while (--h); |
| 546 | break; |
| 547 | case 8: |
| 548 | do { |
| 549 | const __m128i v_ra_b = xx_loadu_128(mask); |
| 550 | const __m128i v_rb_b = xx_loadu_128(mask + mask_stride); |
| 551 | const __m128i v_rvs_b = _mm_add_epi8(v_ra_b, v_rb_b); |
| 552 | const __m128i v_r_s_b = _mm_shuffle_epi8(v_rvs_b, v_shuffle_b); |
| 553 | const __m128i v_r0_s_w = _mm_cvtepu8_epi16(v_r_s_b); |
| 554 | const __m128i v_r1_s_w = _mm_cvtepu8_epi16(_mm_srli_si128(v_r_s_b, 8)); |
| 555 | const __m128i v_rs_w = _mm_add_epi16(v_r0_s_w, v_r1_s_w); |
| 556 | const __m128i v_m0_w = xx_roundn_epu16(v_rs_w, 2); |
| 557 | const __m128i v_m0_b = _mm_packus_epi16(v_m0_w, v_m0_w); |
| 558 | const __m128i v_m1_b = _mm_sub_epi8(v_maxval_b, v_m0_b); |
| 559 | |
| 560 | const __m128i v_res_b = blend_8_u8(src0, src1, &v_m0_b, &v_m1_b, &_r); |
| 561 | |
| 562 | xx_storel_64(dst, v_res_b); |
| 563 | |
| 564 | dst += dst_stride; |
| 565 | src0 += src0_stride; |
| 566 | src1 += src1_stride; |
| 567 | mask += 2 * mask_stride; |
| 568 | } while (--h); |
| 569 | break; |
| 570 | case 16: |
| 571 | blend_a64_mask_sx_sy_w16_avx2(dst, dst_stride, src0, src0_stride, src1, |
| 572 | src1_stride, mask, mask_stride, h); |
| 573 | break; |
| 574 | default: |
| 575 | blend_a64_mask_sx_sy_w32n_avx2(dst, dst_stride, src0, src0_stride, src1, |
| 576 | src1_stride, mask, mask_stride, w, h); |
| 577 | break; |
| 578 | } |
| 579 | } |
| 580 | |
| 581 | static INLINE void blend_a64_mask_sx_w16_avx2( |
| 582 | uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, |
| 583 | uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, |
| 584 | const uint8_t *mask, uint32_t mask_stride, int h) { |
| 585 | const __m256i v_maxval_b = _mm256_set1_epi8(AOM_BLEND_A64_MAX_ALPHA); |
| 586 | const __m256i v_zmask_b = _mm256_set1_epi16(0xff); |
| 587 | do { |
| 588 | const __m256i v_rl_b = yy_loadu_256(mask); |
| 589 | const __m256i v_al_b = |
| 590 | _mm256_avg_epu8(v_rl_b, _mm256_srli_si256(v_rl_b, 1)); |
| 591 | |
| 592 | const __m256i v_m0_w = _mm256_and_si256(v_al_b, v_zmask_b); |
| 593 | const __m256i v_m0_b = _mm256_packus_epi16(v_m0_w, _mm256_setzero_si256()); |
| 594 | const __m256i v_m1_b = _mm256_sub_epi8(v_maxval_b, v_m0_b); |
| 595 | |
| 596 | const __m256i v_res_b = blend_16_u8_avx2(src0, src1, &v_m0_b, &v_m1_b, |
| 597 | AOM_BLEND_A64_ROUND_BITS); |
| 598 | |
| 599 | xx_storeu_128(dst, _mm256_castsi256_si128(v_res_b)); |
| 600 | dst += dst_stride; |
| 601 | src0 += src0_stride; |
| 602 | src1 += src1_stride; |
| 603 | mask += mask_stride; |
| 604 | } while (--h); |
| 605 | } |
| 606 | |
| 607 | static INLINE void blend_a64_mask_sx_w32n_avx2( |
| 608 | uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, |
| 609 | uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, |
| 610 | const uint8_t *mask, uint32_t mask_stride, int w, int h) { |
| 611 | const __m256i v_shuffle_b = yy_loadu_256(g_blend_a64_mask_shuffle); |
| 612 | const __m256i v_maxval_b = _mm256_set1_epi8(AOM_BLEND_A64_MAX_ALPHA); |
| 613 | do { |
| 614 | int c; |
| 615 | for (c = 0; c < w; c += 32) { |
| 616 | const __m256i v_r0_b = yy_loadu_256(mask + 2 * c); |
| 617 | const __m256i v_r1_b = yy_loadu_256(mask + 2 * c + 32); |
| 618 | const __m256i v_r0_s_b = _mm256_shuffle_epi8(v_r0_b, v_shuffle_b); |
| 619 | const __m256i v_r1_s_b = _mm256_shuffle_epi8(v_r1_b, v_shuffle_b); |
| 620 | const __m256i v_al_b = |
| 621 | _mm256_avg_epu8(v_r0_s_b, _mm256_srli_si256(v_r0_s_b, 8)); |
| 622 | const __m256i v_ah_b = |
| 623 | _mm256_avg_epu8(v_r1_s_b, _mm256_srli_si256(v_r1_s_b, 8)); |
| 624 | |
| 625 | const __m256i v_m0_b = |
| 626 | _mm256_permute4x64_epi64(_mm256_unpacklo_epi64(v_al_b, v_ah_b), 0xd8); |
| 627 | const __m256i v_m1_b = _mm256_sub_epi8(v_maxval_b, v_m0_b); |
| 628 | |
| 629 | const __m256i v_res_b = blend_32_u8_avx2( |
| 630 | src0 + c, src1 + c, &v_m0_b, &v_m1_b, AOM_BLEND_A64_ROUND_BITS); |
| 631 | |
| 632 | yy_storeu_256(dst + c, v_res_b); |
| 633 | } |
| 634 | dst += dst_stride; |
| 635 | src0 += src0_stride; |
| 636 | src1 += src1_stride; |
| 637 | mask += mask_stride; |
| 638 | } while (--h); |
| 639 | } |
| 640 | |
| 641 | static INLINE void blend_a64_mask_sx_avx2( |
| 642 | uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, |
| 643 | uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, |
| 644 | const uint8_t *mask, uint32_t mask_stride, int w, int h) { |
| 645 | const __m128i v_shuffle_b = xx_loadu_128(g_blend_a64_mask_shuffle); |
| 646 | const __m128i v_maxval_b = _mm_set1_epi8(AOM_BLEND_A64_MAX_ALPHA); |
| 647 | const __m128i _r = _mm_set1_epi16(1 << (15 - AOM_BLEND_A64_ROUND_BITS)); |
| 648 | switch (w) { |
| 649 | case 4: |
| 650 | do { |
| 651 | const __m128i v_r_b = xx_loadl_64(mask); |
| 652 | const __m128i v_r0_s_b = _mm_shuffle_epi8(v_r_b, v_shuffle_b); |
| 653 | const __m128i v_r_lo_b = _mm_unpacklo_epi64(v_r0_s_b, v_r0_s_b); |
| 654 | const __m128i v_r_hi_b = _mm_unpackhi_epi64(v_r0_s_b, v_r0_s_b); |
| 655 | const __m128i v_m0_b = _mm_avg_epu8(v_r_lo_b, v_r_hi_b); |
| 656 | const __m128i v_m1_b = _mm_sub_epi8(v_maxval_b, v_m0_b); |
| 657 | |
| 658 | const __m128i v_res_b = blend_4_u8(src0, src1, &v_m0_b, &v_m1_b, &_r); |
| 659 | |
| 660 | xx_storel_32(dst, v_res_b); |
| 661 | |
| 662 | dst += dst_stride; |
| 663 | src0 += src0_stride; |
| 664 | src1 += src1_stride; |
| 665 | mask += mask_stride; |
| 666 | } while (--h); |
| 667 | break; |
| 668 | case 8: |
| 669 | do { |
| 670 | const __m128i v_r_b = xx_loadu_128(mask); |
| 671 | const __m128i v_r0_s_b = _mm_shuffle_epi8(v_r_b, v_shuffle_b); |
| 672 | const __m128i v_r_lo_b = _mm_unpacklo_epi64(v_r0_s_b, v_r0_s_b); |
| 673 | const __m128i v_r_hi_b = _mm_unpackhi_epi64(v_r0_s_b, v_r0_s_b); |
| 674 | const __m128i v_m0_b = _mm_avg_epu8(v_r_lo_b, v_r_hi_b); |
| 675 | const __m128i v_m1_b = _mm_sub_epi8(v_maxval_b, v_m0_b); |
| 676 | |
| 677 | const __m128i v_res_b = blend_8_u8(src0, src1, &v_m0_b, &v_m1_b, &_r); |
| 678 | |
| 679 | xx_storel_64(dst, v_res_b); |
| 680 | |
| 681 | dst += dst_stride; |
| 682 | src0 += src0_stride; |
| 683 | src1 += src1_stride; |
| 684 | mask += mask_stride; |
| 685 | } while (--h); |
| 686 | break; |
| 687 | case 16: |
| 688 | blend_a64_mask_sx_w16_avx2(dst, dst_stride, src0, src0_stride, src1, |
| 689 | src1_stride, mask, mask_stride, h); |
| 690 | break; |
| 691 | default: |
| 692 | blend_a64_mask_sx_w32n_avx2(dst, dst_stride, src0, src0_stride, src1, |
| 693 | src1_stride, mask, mask_stride, w, h); |
| 694 | break; |
| 695 | } |
| 696 | } |
| 697 | |
| 698 | static INLINE void blend_a64_mask_sy_w16_avx2( |
| 699 | uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, |
| 700 | uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, |
| 701 | const uint8_t *mask, uint32_t mask_stride, int h) { |
| 702 | const __m128i _r = _mm_set1_epi16(1 << (15 - AOM_BLEND_A64_ROUND_BITS)); |
| 703 | const __m128i v_maxval_b = _mm_set1_epi8(AOM_BLEND_A64_MAX_ALPHA); |
| 704 | do { |
| 705 | const __m128i v_ra_b = xx_loadu_128(mask); |
| 706 | const __m128i v_rb_b = xx_loadu_128(mask + mask_stride); |
| 707 | const __m128i v_m0_b = _mm_avg_epu8(v_ra_b, v_rb_b); |
| 708 | |
| 709 | const __m128i v_m1_b = _mm_sub_epi16(v_maxval_b, v_m0_b); |
| 710 | const __m128i v_res_b = blend_16_u8(src0, src1, &v_m0_b, &v_m1_b, &_r); |
| 711 | |
| 712 | xx_storeu_128(dst, v_res_b); |
| 713 | dst += dst_stride; |
| 714 | src0 += src0_stride; |
| 715 | src1 += src1_stride; |
| 716 | mask += 2 * mask_stride; |
| 717 | } while (--h); |
| 718 | } |
| 719 | |
| 720 | static INLINE void blend_a64_mask_sy_w32n_avx2( |
| 721 | uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, |
| 722 | uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, |
| 723 | const uint8_t *mask, uint32_t mask_stride, int w, int h) { |
| 724 | const __m256i v_maxval_b = _mm256_set1_epi8(AOM_BLEND_A64_MAX_ALPHA); |
| 725 | do { |
| 726 | int c; |
| 727 | for (c = 0; c < w; c += 32) { |
| 728 | const __m256i v_ra_b = yy_loadu_256(mask + c); |
| 729 | const __m256i v_rb_b = yy_loadu_256(mask + c + mask_stride); |
| 730 | const __m256i v_m0_b = _mm256_avg_epu8(v_ra_b, v_rb_b); |
| 731 | const __m256i v_m1_b = _mm256_sub_epi8(v_maxval_b, v_m0_b); |
| 732 | const __m256i v_res_b = blend_32_u8_avx2( |
| 733 | src0 + c, src1 + c, &v_m0_b, &v_m1_b, AOM_BLEND_A64_ROUND_BITS); |
| 734 | |
| 735 | yy_storeu_256(dst + c, v_res_b); |
| 736 | } |
| 737 | dst += dst_stride; |
| 738 | src0 += src0_stride; |
| 739 | src1 += src1_stride; |
| 740 | mask += 2 * mask_stride; |
| 741 | } while (--h); |
| 742 | } |
| 743 | |
| 744 | static INLINE void blend_a64_mask_sy_avx2( |
| 745 | uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, |
| 746 | uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, |
| 747 | const uint8_t *mask, uint32_t mask_stride, int w, int h) { |
| 748 | const __m128i _r = _mm_set1_epi16(1 << (15 - AOM_BLEND_A64_ROUND_BITS)); |
| 749 | const __m128i v_maxval_b = _mm_set1_epi8(AOM_BLEND_A64_MAX_ALPHA); |
| 750 | switch (w) { |
| 751 | case 4: |
| 752 | do { |
| 753 | const __m128i v_ra_b = xx_loadl_32(mask); |
| 754 | const __m128i v_rb_b = xx_loadl_32(mask + mask_stride); |
| 755 | const __m128i v_m0_b = _mm_avg_epu8(v_ra_b, v_rb_b); |
| 756 | const __m128i v_m1_b = _mm_sub_epi8(v_maxval_b, v_m0_b); |
| 757 | const __m128i v_res_b = blend_4_u8(src0, src1, &v_m0_b, &v_m1_b, &_r); |
| 758 | |
| 759 | xx_storel_32(dst, v_res_b); |
| 760 | |
| 761 | dst += dst_stride; |
| 762 | src0 += src0_stride; |
| 763 | src1 += src1_stride; |
| 764 | mask += 2 * mask_stride; |
| 765 | } while (--h); |
| 766 | break; |
| 767 | case 8: |
| 768 | do { |
| 769 | const __m128i v_ra_b = xx_loadl_64(mask); |
| 770 | const __m128i v_rb_b = xx_loadl_64(mask + mask_stride); |
| 771 | const __m128i v_m0_b = _mm_avg_epu8(v_ra_b, v_rb_b); |
| 772 | const __m128i v_m1_b = _mm_sub_epi8(v_maxval_b, v_m0_b); |
| 773 | const __m128i v_res_b = blend_8_u8(src0, src1, &v_m0_b, &v_m1_b, &_r); |
| 774 | |
| 775 | xx_storel_64(dst, v_res_b); |
| 776 | |
| 777 | dst += dst_stride; |
| 778 | src0 += src0_stride; |
| 779 | src1 += src1_stride; |
| 780 | mask += 2 * mask_stride; |
| 781 | } while (--h); |
| 782 | break; |
| 783 | case 16: |
| 784 | blend_a64_mask_sy_w16_avx2(dst, dst_stride, src0, src0_stride, src1, |
| 785 | src1_stride, mask, mask_stride, h); |
| 786 | break; |
| 787 | default: |
| 788 | blend_a64_mask_sy_w32n_avx2(dst, dst_stride, src0, src0_stride, src1, |
| 789 | src1_stride, mask, mask_stride, w, h); |
| 790 | } |
| 791 | } |
| 792 | |
| 793 | static INLINE void blend_a64_mask_w32n_avx2( |
| 794 | uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, |
| 795 | uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, |
| 796 | const uint8_t *mask, uint32_t mask_stride, int w, int h) { |
| 797 | const __m256i v_maxval_b = _mm256_set1_epi8(AOM_BLEND_A64_MAX_ALPHA); |
| 798 | do { |
| 799 | int c; |
| 800 | for (c = 0; c < w; c += 32) { |
| 801 | const __m256i v_m0_b = yy_loadu_256(mask + c); |
| 802 | const __m256i v_m1_b = _mm256_sub_epi8(v_maxval_b, v_m0_b); |
| 803 | |
| 804 | const __m256i v_res_b = blend_32_u8_avx2( |
| 805 | src0 + c, src1 + c, &v_m0_b, &v_m1_b, AOM_BLEND_A64_ROUND_BITS); |
| 806 | |
| 807 | yy_storeu_256(dst + c, v_res_b); |
| 808 | } |
| 809 | dst += dst_stride; |
| 810 | src0 += src0_stride; |
| 811 | src1 += src1_stride; |
| 812 | mask += mask_stride; |
| 813 | } while (--h); |
| 814 | } |
| 815 | |
| 816 | static INLINE void blend_a64_mask_avx2( |
| 817 | uint8_t *dst, uint32_t dst_stride, const uint8_t *src0, |
| 818 | uint32_t src0_stride, const uint8_t *src1, uint32_t src1_stride, |
| 819 | const uint8_t *mask, uint32_t mask_stride, int w, int h) { |
| 820 | const __m128i v_maxval_b = _mm_set1_epi8(AOM_BLEND_A64_MAX_ALPHA); |
| 821 | const __m128i _r = _mm_set1_epi16(1 << (15 - AOM_BLEND_A64_ROUND_BITS)); |
| 822 | switch (w) { |
| 823 | case 4: |
| 824 | do { |
| 825 | const __m128i v_m0_b = xx_loadl_32(mask); |
| 826 | const __m128i v_m1_b = _mm_sub_epi8(v_maxval_b, v_m0_b); |
| 827 | const __m128i v_res_b = blend_4_u8(src0, src1, &v_m0_b, &v_m1_b, &_r); |
| 828 | |
| 829 | xx_storel_32(dst, v_res_b); |
| 830 | |
| 831 | dst += dst_stride; |
| 832 | src0 += src0_stride; |
| 833 | src1 += src1_stride; |
| 834 | mask += mask_stride; |
| 835 | } while (--h); |
| 836 | break; |
| 837 | case 8: |
| 838 | do { |
| 839 | const __m128i v_m0_b = xx_loadl_64(mask); |
| 840 | const __m128i v_m1_b = _mm_sub_epi8(v_maxval_b, v_m0_b); |
| 841 | const __m128i v_res_b = blend_8_u8(src0, src1, &v_m0_b, &v_m1_b, &_r); |
| 842 | |
| 843 | xx_storel_64(dst, v_res_b); |
| 844 | |
| 845 | dst += dst_stride; |
| 846 | src0 += src0_stride; |
| 847 | src1 += src1_stride; |
| 848 | mask += mask_stride; |
| 849 | } while (--h); |
| 850 | break; |
| 851 | case 16: |
| 852 | do { |
| 853 | const __m128i v_m0_b = xx_loadu_128(mask); |
| 854 | const __m128i v_m1_b = _mm_sub_epi8(v_maxval_b, v_m0_b); |
| 855 | const __m128i v_res_b = blend_16_u8(src0, src1, &v_m0_b, &v_m1_b, &_r); |
| 856 | |
| 857 | xx_storeu_128(dst, v_res_b); |
| 858 | dst += dst_stride; |
| 859 | src0 += src0_stride; |
| 860 | src1 += src1_stride; |
| 861 | mask += mask_stride; |
| 862 | } while (--h); |
| 863 | break; |
| 864 | default: |
| 865 | blend_a64_mask_w32n_avx2(dst, dst_stride, src0, src0_stride, src1, |
| 866 | src1_stride, mask, mask_stride, w, h); |
| 867 | } |
| 868 | } |
| 869 | |
| 870 | void aom_blend_a64_mask_avx2(uint8_t *dst, uint32_t dst_stride, |
| 871 | const uint8_t *src0, uint32_t src0_stride, |
| 872 | const uint8_t *src1, uint32_t src1_stride, |
| 873 | const uint8_t *mask, uint32_t mask_stride, int w, |
Yaowu Xu | 1ff1b88 | 2019-05-14 12:28:11 -0700 | [diff] [blame] | 874 | int h, int subw, int subh) { |
Xing Jin | de2b711 | 2018-08-08 19:44:15 +0800 | [diff] [blame] | 875 | assert(IMPLIES(src0 == dst, src0_stride == dst_stride)); |
| 876 | assert(IMPLIES(src1 == dst, src1_stride == dst_stride)); |
| 877 | |
| 878 | assert(h >= 1); |
| 879 | assert(w >= 1); |
| 880 | assert(IS_POWER_OF_TWO(h)); |
| 881 | assert(IS_POWER_OF_TWO(w)); |
| 882 | |
| 883 | if (UNLIKELY((h | w) & 3)) { // if (w <= 2 || h <= 2) |
| 884 | aom_blend_a64_mask_c(dst, dst_stride, src0, src0_stride, src1, src1_stride, |
Yaowu Xu | 1ff1b88 | 2019-05-14 12:28:11 -0700 | [diff] [blame] | 885 | mask, mask_stride, w, h, subw, subh); |
Xing Jin | de2b711 | 2018-08-08 19:44:15 +0800 | [diff] [blame] | 886 | } else { |
Yaowu Xu | 1ff1b88 | 2019-05-14 12:28:11 -0700 | [diff] [blame] | 887 | if (subw & subh) { |
Xing Jin | de2b711 | 2018-08-08 19:44:15 +0800 | [diff] [blame] | 888 | blend_a64_mask_sx_sy_avx2(dst, dst_stride, src0, src0_stride, src1, |
| 889 | src1_stride, mask, mask_stride, w, h); |
Yaowu Xu | 1ff1b88 | 2019-05-14 12:28:11 -0700 | [diff] [blame] | 890 | } else if (subw) { |
Xing Jin | de2b711 | 2018-08-08 19:44:15 +0800 | [diff] [blame] | 891 | blend_a64_mask_sx_avx2(dst, dst_stride, src0, src0_stride, src1, |
| 892 | src1_stride, mask, mask_stride, w, h); |
Yaowu Xu | 1ff1b88 | 2019-05-14 12:28:11 -0700 | [diff] [blame] | 893 | } else if (subh) { |
Xing Jin | de2b711 | 2018-08-08 19:44:15 +0800 | [diff] [blame] | 894 | blend_a64_mask_sy_avx2(dst, dst_stride, src0, src0_stride, src1, |
| 895 | src1_stride, mask, mask_stride, w, h); |
| 896 | } else { |
| 897 | blend_a64_mask_avx2(dst, dst_stride, src0, src0_stride, src1, src1_stride, |
| 898 | mask, mask_stride, w, h); |
| 899 | } |
| 900 | } |
| 901 | } |
David Turner | b5ed1e6 | 2018-10-11 15:17:53 +0100 | [diff] [blame] | 902 | |
| 903 | ////////////////////////////////////////////////////////////////////////////// |
| 904 | // aom_highbd_blend_a64_d16_mask_avx2() |
| 905 | ////////////////////////////////////////////////////////////////////////////// |
| 906 | |
| 907 | static INLINE void highbd_blend_a64_d16_mask_w4_avx2( |
| 908 | uint16_t *dst, int dst_stride, const CONV_BUF_TYPE *src0, int src0_stride, |
| 909 | const CONV_BUF_TYPE *src1, int src1_stride, const __m256i *mask0, |
| 910 | const __m256i *round_offset, int shift, const __m256i *clip_low, |
| 911 | const __m256i *clip_high, const __m256i *mask_max) { |
| 912 | // Load 4x u16 pixels from each of 4 rows from each source |
| 913 | const __m256i s0 = _mm256_set_epi64x(*(uint64_t *)(src0 + 3 * src0_stride), |
| 914 | *(uint64_t *)(src0 + 2 * src0_stride), |
| 915 | *(uint64_t *)(src0 + 1 * src0_stride), |
| 916 | *(uint64_t *)(src0 + 0 * src0_stride)); |
| 917 | const __m256i s1 = _mm256_set_epi64x(*(uint64_t *)(src1 + 3 * src1_stride), |
| 918 | *(uint64_t *)(src1 + 2 * src1_stride), |
| 919 | *(uint64_t *)(src1 + 1 * src1_stride), |
| 920 | *(uint64_t *)(src1 + 0 * src1_stride)); |
| 921 | // Generate the inverse mask |
| 922 | const __m256i mask1 = _mm256_sub_epi16(*mask_max, *mask0); |
| 923 | |
| 924 | // Multiply each mask by the respective source |
| 925 | const __m256i mul0_highs = _mm256_mulhi_epu16(*mask0, s0); |
| 926 | const __m256i mul0_lows = _mm256_mullo_epi16(*mask0, s0); |
| 927 | const __m256i mul0h = _mm256_unpackhi_epi16(mul0_lows, mul0_highs); |
| 928 | const __m256i mul0l = _mm256_unpacklo_epi16(mul0_lows, mul0_highs); |
| 929 | // Note that AVX2 unpack orders 64-bit words as [3 1] [2 0] to keep within |
| 930 | // lanes Later, packs does the same again which cancels this out with no need |
| 931 | // for a permute. The intermediate values being reordered makes no difference |
| 932 | |
| 933 | const __m256i mul1_highs = _mm256_mulhi_epu16(mask1, s1); |
| 934 | const __m256i mul1_lows = _mm256_mullo_epi16(mask1, s1); |
| 935 | const __m256i mul1h = _mm256_unpackhi_epi16(mul1_lows, mul1_highs); |
| 936 | const __m256i mul1l = _mm256_unpacklo_epi16(mul1_lows, mul1_highs); |
| 937 | |
| 938 | const __m256i sumh = _mm256_add_epi32(mul0h, mul1h); |
| 939 | const __m256i suml = _mm256_add_epi32(mul0l, mul1l); |
| 940 | |
| 941 | const __m256i roundh = |
| 942 | _mm256_srai_epi32(_mm256_sub_epi32(sumh, *round_offset), shift); |
| 943 | const __m256i roundl = |
| 944 | _mm256_srai_epi32(_mm256_sub_epi32(suml, *round_offset), shift); |
| 945 | |
| 946 | const __m256i pack = _mm256_packs_epi32(roundl, roundh); |
| 947 | const __m256i clip = |
| 948 | _mm256_min_epi16(_mm256_max_epi16(pack, *clip_low), *clip_high); |
| 949 | |
| 950 | // _mm256_extract_epi64 doesn't exist on x86, so do it the old-fashioned way: |
| 951 | const __m128i cliph = _mm256_extracti128_si256(clip, 1); |
| 952 | xx_storel_64(dst + 3 * dst_stride, _mm_srli_si128(cliph, 8)); |
| 953 | xx_storel_64(dst + 2 * dst_stride, cliph); |
| 954 | const __m128i clipl = _mm256_castsi256_si128(clip); |
| 955 | xx_storel_64(dst + 1 * dst_stride, _mm_srli_si128(clipl, 8)); |
| 956 | xx_storel_64(dst + 0 * dst_stride, clipl); |
| 957 | } |
| 958 | |
| 959 | static INLINE void highbd_blend_a64_d16_mask_subw0_subh0_w4_avx2( |
| 960 | uint16_t *dst, uint32_t dst_stride, const CONV_BUF_TYPE *src0, |
| 961 | uint32_t src0_stride, const CONV_BUF_TYPE *src1, uint32_t src1_stride, |
| 962 | const uint8_t *mask, uint32_t mask_stride, int h, |
| 963 | const __m256i *round_offset, int shift, const __m256i *clip_low, |
| 964 | const __m256i *clip_high, const __m256i *mask_max) { |
| 965 | do { |
| 966 | // Load 8x u8 pixels from each of 4 rows of the mask, pad each to u16 |
| 967 | const __m128i mask08 = _mm_set_epi32(*(uint32_t *)(mask + 3 * mask_stride), |
| 968 | *(uint32_t *)(mask + 2 * mask_stride), |
| 969 | *(uint32_t *)(mask + 1 * mask_stride), |
| 970 | *(uint32_t *)(mask + 0 * mask_stride)); |
| 971 | const __m256i mask0 = _mm256_cvtepu8_epi16(mask08); |
| 972 | |
| 973 | highbd_blend_a64_d16_mask_w4_avx2(dst, dst_stride, src0, src0_stride, src1, |
| 974 | src1_stride, &mask0, round_offset, shift, |
| 975 | clip_low, clip_high, mask_max); |
| 976 | |
| 977 | dst += dst_stride * 4; |
| 978 | src0 += src0_stride * 4; |
| 979 | src1 += src1_stride * 4; |
| 980 | mask += mask_stride * 4; |
| 981 | } while (h -= 4); |
| 982 | } |
| 983 | |
| 984 | static INLINE void highbd_blend_a64_d16_mask_subw1_subh1_w4_avx2( |
| 985 | uint16_t *dst, uint32_t dst_stride, const CONV_BUF_TYPE *src0, |
| 986 | uint32_t src0_stride, const CONV_BUF_TYPE *src1, uint32_t src1_stride, |
| 987 | const uint8_t *mask, uint32_t mask_stride, int h, |
| 988 | const __m256i *round_offset, int shift, const __m256i *clip_low, |
| 989 | const __m256i *clip_high, const __m256i *mask_max) { |
| 990 | const __m256i one_b = _mm256_set1_epi8(1); |
| 991 | const __m256i two_w = _mm256_set1_epi16(2); |
| 992 | do { |
| 993 | // Load 8 pixels from each of 8 rows of mask, |
| 994 | // (saturating) add together rows then use madd to add adjacent pixels |
| 995 | // Finally, divide each value by 4 (with rounding) |
| 996 | const __m256i m0246 = |
| 997 | _mm256_set_epi64x(*(uint64_t *)(mask + 6 * mask_stride), |
| 998 | *(uint64_t *)(mask + 4 * mask_stride), |
| 999 | *(uint64_t *)(mask + 2 * mask_stride), |
| 1000 | *(uint64_t *)(mask + 0 * mask_stride)); |
| 1001 | const __m256i m1357 = |
| 1002 | _mm256_set_epi64x(*(uint64_t *)(mask + 7 * mask_stride), |
| 1003 | *(uint64_t *)(mask + 5 * mask_stride), |
| 1004 | *(uint64_t *)(mask + 3 * mask_stride), |
| 1005 | *(uint64_t *)(mask + 1 * mask_stride)); |
| 1006 | const __m256i addrows = _mm256_adds_epu8(m0246, m1357); |
| 1007 | const __m256i adjacent = _mm256_maddubs_epi16(addrows, one_b); |
| 1008 | const __m256i mask0 = |
| 1009 | _mm256_srli_epi16(_mm256_add_epi16(adjacent, two_w), 2); |
| 1010 | |
| 1011 | highbd_blend_a64_d16_mask_w4_avx2(dst, dst_stride, src0, src0_stride, src1, |
| 1012 | src1_stride, &mask0, round_offset, shift, |
| 1013 | clip_low, clip_high, mask_max); |
| 1014 | |
| 1015 | dst += dst_stride * 4; |
| 1016 | src0 += src0_stride * 4; |
| 1017 | src1 += src1_stride * 4; |
| 1018 | mask += mask_stride * 8; |
| 1019 | } while (h -= 4); |
| 1020 | } |
| 1021 | |
| 1022 | static INLINE void highbd_blend_a64_d16_mask_w8_avx2( |
| 1023 | uint16_t *dst, int dst_stride, const CONV_BUF_TYPE *src0, int src0_stride, |
| 1024 | const CONV_BUF_TYPE *src1, int src1_stride, const __m256i *mask0a, |
| 1025 | const __m256i *mask0b, const __m256i *round_offset, int shift, |
| 1026 | const __m256i *clip_low, const __m256i *clip_high, |
| 1027 | const __m256i *mask_max) { |
| 1028 | // Load 8x u16 pixels from each of 4 rows from each source |
| 1029 | const __m256i s0a = |
| 1030 | yy_loadu2_128(src0 + 0 * src0_stride, src0 + 1 * src0_stride); |
| 1031 | const __m256i s0b = |
| 1032 | yy_loadu2_128(src0 + 2 * src0_stride, src0 + 3 * src0_stride); |
| 1033 | const __m256i s1a = |
| 1034 | yy_loadu2_128(src1 + 0 * src1_stride, src1 + 1 * src1_stride); |
| 1035 | const __m256i s1b = |
| 1036 | yy_loadu2_128(src1 + 2 * src1_stride, src1 + 3 * src1_stride); |
| 1037 | |
| 1038 | // Generate inverse masks |
| 1039 | const __m256i mask1a = _mm256_sub_epi16(*mask_max, *mask0a); |
| 1040 | const __m256i mask1b = _mm256_sub_epi16(*mask_max, *mask0b); |
| 1041 | |
| 1042 | // Multiply sources by respective masks |
| 1043 | const __m256i mul0a_highs = _mm256_mulhi_epu16(*mask0a, s0a); |
| 1044 | const __m256i mul0a_lows = _mm256_mullo_epi16(*mask0a, s0a); |
| 1045 | const __m256i mul0ah = _mm256_unpackhi_epi16(mul0a_lows, mul0a_highs); |
| 1046 | const __m256i mul0al = _mm256_unpacklo_epi16(mul0a_lows, mul0a_highs); |
| 1047 | // Note that AVX2 unpack orders 64-bit words as [3 1] [2 0] to keep within |
| 1048 | // lanes Later, packs does the same again which cancels this out with no need |
| 1049 | // for a permute. The intermediate values being reordered makes no difference |
| 1050 | |
| 1051 | const __m256i mul1a_highs = _mm256_mulhi_epu16(mask1a, s1a); |
| 1052 | const __m256i mul1a_lows = _mm256_mullo_epi16(mask1a, s1a); |
| 1053 | const __m256i mul1ah = _mm256_unpackhi_epi16(mul1a_lows, mul1a_highs); |
| 1054 | const __m256i mul1al = _mm256_unpacklo_epi16(mul1a_lows, mul1a_highs); |
| 1055 | |
| 1056 | const __m256i sumah = _mm256_add_epi32(mul0ah, mul1ah); |
| 1057 | const __m256i sumal = _mm256_add_epi32(mul0al, mul1al); |
| 1058 | |
| 1059 | const __m256i mul0b_highs = _mm256_mulhi_epu16(*mask0b, s0b); |
| 1060 | const __m256i mul0b_lows = _mm256_mullo_epi16(*mask0b, s0b); |
| 1061 | const __m256i mul0bh = _mm256_unpackhi_epi16(mul0b_lows, mul0b_highs); |
| 1062 | const __m256i mul0bl = _mm256_unpacklo_epi16(mul0b_lows, mul0b_highs); |
| 1063 | |
| 1064 | const __m256i mul1b_highs = _mm256_mulhi_epu16(mask1b, s1b); |
| 1065 | const __m256i mul1b_lows = _mm256_mullo_epi16(mask1b, s1b); |
| 1066 | const __m256i mul1bh = _mm256_unpackhi_epi16(mul1b_lows, mul1b_highs); |
| 1067 | const __m256i mul1bl = _mm256_unpacklo_epi16(mul1b_lows, mul1b_highs); |
| 1068 | |
| 1069 | const __m256i sumbh = _mm256_add_epi32(mul0bh, mul1bh); |
| 1070 | const __m256i sumbl = _mm256_add_epi32(mul0bl, mul1bl); |
| 1071 | |
| 1072 | // Divide down each result, with rounding |
| 1073 | const __m256i roundah = |
| 1074 | _mm256_srai_epi32(_mm256_sub_epi32(sumah, *round_offset), shift); |
| 1075 | const __m256i roundal = |
| 1076 | _mm256_srai_epi32(_mm256_sub_epi32(sumal, *round_offset), shift); |
| 1077 | const __m256i roundbh = |
| 1078 | _mm256_srai_epi32(_mm256_sub_epi32(sumbh, *round_offset), shift); |
| 1079 | const __m256i roundbl = |
| 1080 | _mm256_srai_epi32(_mm256_sub_epi32(sumbl, *round_offset), shift); |
| 1081 | |
| 1082 | // Pack each i32 down to an i16 with saturation, then clip to valid range |
| 1083 | const __m256i packa = _mm256_packs_epi32(roundal, roundah); |
| 1084 | const __m256i clipa = |
| 1085 | _mm256_min_epi16(_mm256_max_epi16(packa, *clip_low), *clip_high); |
| 1086 | const __m256i packb = _mm256_packs_epi32(roundbl, roundbh); |
| 1087 | const __m256i clipb = |
| 1088 | _mm256_min_epi16(_mm256_max_epi16(packb, *clip_low), *clip_high); |
| 1089 | |
| 1090 | // Store 8x u16 pixels to each of 4 rows in the destination |
| 1091 | yy_storeu2_128(dst + 0 * dst_stride, dst + 1 * dst_stride, clipa); |
| 1092 | yy_storeu2_128(dst + 2 * dst_stride, dst + 3 * dst_stride, clipb); |
| 1093 | } |
| 1094 | |
| 1095 | static INLINE void highbd_blend_a64_d16_mask_subw0_subh0_w8_avx2( |
| 1096 | uint16_t *dst, int dst_stride, const CONV_BUF_TYPE *src0, int src0_stride, |
| 1097 | const CONV_BUF_TYPE *src1, int src1_stride, const uint8_t *mask, |
| 1098 | int mask_stride, int h, const __m256i *round_offset, int shift, |
| 1099 | const __m256i *clip_low, const __m256i *clip_high, |
| 1100 | const __m256i *mask_max) { |
| 1101 | do { |
| 1102 | // Load 8x u8 pixels from each of 4 rows in the mask |
| 1103 | const __m128i mask0a8 = |
David Turner | bd3f9b6 | 2018-11-14 17:28:52 +0000 | [diff] [blame] | 1104 | _mm_set_epi64x(*(uint64_t *)mask, *(uint64_t *)(mask + mask_stride)); |
David Turner | b5ed1e6 | 2018-10-11 15:17:53 +0100 | [diff] [blame] | 1105 | const __m128i mask0b8 = |
David Turner | bd3f9b6 | 2018-11-14 17:28:52 +0000 | [diff] [blame] | 1106 | _mm_set_epi64x(*(uint64_t *)(mask + 2 * mask_stride), |
| 1107 | *(uint64_t *)(mask + 3 * mask_stride)); |
David Turner | b5ed1e6 | 2018-10-11 15:17:53 +0100 | [diff] [blame] | 1108 | const __m256i mask0a = _mm256_cvtepu8_epi16(mask0a8); |
| 1109 | const __m256i mask0b = _mm256_cvtepu8_epi16(mask0b8); |
| 1110 | |
| 1111 | highbd_blend_a64_d16_mask_w8_avx2( |
| 1112 | dst, dst_stride, src0, src0_stride, src1, src1_stride, &mask0a, &mask0b, |
| 1113 | round_offset, shift, clip_low, clip_high, mask_max); |
| 1114 | |
| 1115 | dst += dst_stride * 4; |
| 1116 | src0 += src0_stride * 4; |
| 1117 | src1 += src1_stride * 4; |
| 1118 | mask += mask_stride * 4; |
| 1119 | } while (h -= 4); |
| 1120 | } |
| 1121 | |
| 1122 | static INLINE void highbd_blend_a64_d16_mask_subw1_subh1_w8_avx2( |
| 1123 | uint16_t *dst, int dst_stride, const CONV_BUF_TYPE *src0, int src0_stride, |
| 1124 | const CONV_BUF_TYPE *src1, int src1_stride, const uint8_t *mask, |
| 1125 | int mask_stride, int h, const __m256i *round_offset, int shift, |
| 1126 | const __m256i *clip_low, const __m256i *clip_high, |
| 1127 | const __m256i *mask_max) { |
| 1128 | const __m256i one_b = _mm256_set1_epi8(1); |
| 1129 | const __m256i two_w = _mm256_set1_epi16(2); |
| 1130 | do { |
| 1131 | // Load 16x u8 pixels from each of 8 rows in the mask, |
| 1132 | // (saturating) add together rows then use madd to add adjacent pixels |
| 1133 | // Finally, divide each value by 4 (with rounding) |
| 1134 | const __m256i m02 = |
| 1135 | yy_loadu2_128(mask + 0 * mask_stride, mask + 2 * mask_stride); |
| 1136 | const __m256i m13 = |
| 1137 | yy_loadu2_128(mask + 1 * mask_stride, mask + 3 * mask_stride); |
| 1138 | const __m256i m0123 = |
| 1139 | _mm256_maddubs_epi16(_mm256_adds_epu8(m02, m13), one_b); |
| 1140 | const __m256i mask_0a = |
| 1141 | _mm256_srli_epi16(_mm256_add_epi16(m0123, two_w), 2); |
| 1142 | const __m256i m46 = |
| 1143 | yy_loadu2_128(mask + 4 * mask_stride, mask + 6 * mask_stride); |
| 1144 | const __m256i m57 = |
| 1145 | yy_loadu2_128(mask + 5 * mask_stride, mask + 7 * mask_stride); |
| 1146 | const __m256i m4567 = |
| 1147 | _mm256_maddubs_epi16(_mm256_adds_epu8(m46, m57), one_b); |
| 1148 | const __m256i mask_0b = |
| 1149 | _mm256_srli_epi16(_mm256_add_epi16(m4567, two_w), 2); |
| 1150 | |
| 1151 | highbd_blend_a64_d16_mask_w8_avx2( |
| 1152 | dst, dst_stride, src0, src0_stride, src1, src1_stride, &mask_0a, |
| 1153 | &mask_0b, round_offset, shift, clip_low, clip_high, mask_max); |
| 1154 | |
| 1155 | dst += dst_stride * 4; |
| 1156 | src0 += src0_stride * 4; |
| 1157 | src1 += src1_stride * 4; |
| 1158 | mask += mask_stride * 8; |
| 1159 | } while (h -= 4); |
| 1160 | } |
| 1161 | |
| 1162 | static INLINE void highbd_blend_a64_d16_mask_w16_avx2( |
| 1163 | uint16_t *dst, int dst_stride, const CONV_BUF_TYPE *src0, int src0_stride, |
| 1164 | const CONV_BUF_TYPE *src1, int src1_stride, const __m256i *mask0a, |
| 1165 | const __m256i *mask0b, const __m256i *round_offset, int shift, |
| 1166 | const __m256i *clip_low, const __m256i *clip_high, |
| 1167 | const __m256i *mask_max) { |
| 1168 | // Load 16x pixels from each of 2 rows from each source |
| 1169 | const __m256i s0a = yy_loadu_256(src0); |
| 1170 | const __m256i s0b = yy_loadu_256(src0 + src0_stride); |
| 1171 | const __m256i s1a = yy_loadu_256(src1); |
| 1172 | const __m256i s1b = yy_loadu_256(src1 + src1_stride); |
| 1173 | |
| 1174 | // Calculate inverse masks |
| 1175 | const __m256i mask1a = _mm256_sub_epi16(*mask_max, *mask0a); |
| 1176 | const __m256i mask1b = _mm256_sub_epi16(*mask_max, *mask0b); |
| 1177 | |
| 1178 | // Multiply each source by appropriate mask |
| 1179 | const __m256i mul0a_highs = _mm256_mulhi_epu16(*mask0a, s0a); |
| 1180 | const __m256i mul0a_lows = _mm256_mullo_epi16(*mask0a, s0a); |
| 1181 | const __m256i mul0ah = _mm256_unpackhi_epi16(mul0a_lows, mul0a_highs); |
| 1182 | const __m256i mul0al = _mm256_unpacklo_epi16(mul0a_lows, mul0a_highs); |
| 1183 | // Note that AVX2 unpack orders 64-bit words as [3 1] [2 0] to keep within |
| 1184 | // lanes Later, packs does the same again which cancels this out with no need |
| 1185 | // for a permute. The intermediate values being reordered makes no difference |
| 1186 | |
| 1187 | const __m256i mul1a_highs = _mm256_mulhi_epu16(mask1a, s1a); |
| 1188 | const __m256i mul1a_lows = _mm256_mullo_epi16(mask1a, s1a); |
| 1189 | const __m256i mul1ah = _mm256_unpackhi_epi16(mul1a_lows, mul1a_highs); |
| 1190 | const __m256i mul1al = _mm256_unpacklo_epi16(mul1a_lows, mul1a_highs); |
| 1191 | |
| 1192 | const __m256i mulah = _mm256_add_epi32(mul0ah, mul1ah); |
| 1193 | const __m256i mulal = _mm256_add_epi32(mul0al, mul1al); |
| 1194 | |
| 1195 | const __m256i mul0b_highs = _mm256_mulhi_epu16(*mask0b, s0b); |
| 1196 | const __m256i mul0b_lows = _mm256_mullo_epi16(*mask0b, s0b); |
| 1197 | const __m256i mul0bh = _mm256_unpackhi_epi16(mul0b_lows, mul0b_highs); |
| 1198 | const __m256i mul0bl = _mm256_unpacklo_epi16(mul0b_lows, mul0b_highs); |
| 1199 | |
| 1200 | const __m256i mul1b_highs = _mm256_mulhi_epu16(mask1b, s1b); |
| 1201 | const __m256i mul1b_lows = _mm256_mullo_epi16(mask1b, s1b); |
| 1202 | const __m256i mul1bh = _mm256_unpackhi_epi16(mul1b_lows, mul1b_highs); |
| 1203 | const __m256i mul1bl = _mm256_unpacklo_epi16(mul1b_lows, mul1b_highs); |
| 1204 | |
| 1205 | const __m256i mulbh = _mm256_add_epi32(mul0bh, mul1bh); |
| 1206 | const __m256i mulbl = _mm256_add_epi32(mul0bl, mul1bl); |
| 1207 | |
| 1208 | const __m256i resah = |
| 1209 | _mm256_srai_epi32(_mm256_sub_epi32(mulah, *round_offset), shift); |
| 1210 | const __m256i resal = |
| 1211 | _mm256_srai_epi32(_mm256_sub_epi32(mulal, *round_offset), shift); |
| 1212 | const __m256i resbh = |
| 1213 | _mm256_srai_epi32(_mm256_sub_epi32(mulbh, *round_offset), shift); |
| 1214 | const __m256i resbl = |
| 1215 | _mm256_srai_epi32(_mm256_sub_epi32(mulbl, *round_offset), shift); |
| 1216 | |
| 1217 | // Signed saturating pack from i32 to i16: |
| 1218 | const __m256i packa = _mm256_packs_epi32(resal, resah); |
| 1219 | const __m256i packb = _mm256_packs_epi32(resbl, resbh); |
| 1220 | |
| 1221 | // Clip the values to the valid range |
| 1222 | const __m256i clipa = |
| 1223 | _mm256_min_epi16(_mm256_max_epi16(packa, *clip_low), *clip_high); |
| 1224 | const __m256i clipb = |
| 1225 | _mm256_min_epi16(_mm256_max_epi16(packb, *clip_low), *clip_high); |
| 1226 | |
| 1227 | // Store 16 pixels |
| 1228 | yy_storeu_256(dst, clipa); |
| 1229 | yy_storeu_256(dst + dst_stride, clipb); |
| 1230 | } |
| 1231 | |
| 1232 | static INLINE void highbd_blend_a64_d16_mask_subw0_subh0_w16_avx2( |
| 1233 | uint16_t *dst, int dst_stride, const CONV_BUF_TYPE *src0, int src0_stride, |
| 1234 | const CONV_BUF_TYPE *src1, int src1_stride, const uint8_t *mask, |
| 1235 | int mask_stride, int h, int w, const __m256i *round_offset, int shift, |
| 1236 | const __m256i *clip_low, const __m256i *clip_high, |
| 1237 | const __m256i *mask_max) { |
| 1238 | for (int i = 0; i < h; i += 2) { |
| 1239 | for (int j = 0; j < w; j += 16) { |
| 1240 | // Load 16x u8 alpha-mask values from each of two rows and pad to u16 |
| 1241 | const __m128i masks_a8 = xx_loadu_128(mask + j); |
| 1242 | const __m128i masks_b8 = xx_loadu_128(mask + mask_stride + j); |
| 1243 | const __m256i mask0a = _mm256_cvtepu8_epi16(masks_a8); |
| 1244 | const __m256i mask0b = _mm256_cvtepu8_epi16(masks_b8); |
| 1245 | |
| 1246 | highbd_blend_a64_d16_mask_w16_avx2( |
| 1247 | dst + j, dst_stride, src0 + j, src0_stride, src1 + j, src1_stride, |
| 1248 | &mask0a, &mask0b, round_offset, shift, clip_low, clip_high, mask_max); |
| 1249 | } |
| 1250 | dst += dst_stride * 2; |
| 1251 | src0 += src0_stride * 2; |
| 1252 | src1 += src1_stride * 2; |
| 1253 | mask += mask_stride * 2; |
| 1254 | } |
| 1255 | } |
| 1256 | |
| 1257 | static INLINE void highbd_blend_a64_d16_mask_subw1_subh1_w16_avx2( |
| 1258 | uint16_t *dst, int dst_stride, const CONV_BUF_TYPE *src0, int src0_stride, |
| 1259 | const CONV_BUF_TYPE *src1, int src1_stride, const uint8_t *mask, |
| 1260 | int mask_stride, int h, int w, const __m256i *round_offset, int shift, |
| 1261 | const __m256i *clip_low, const __m256i *clip_high, |
| 1262 | const __m256i *mask_max) { |
| 1263 | const __m256i one_b = _mm256_set1_epi8(1); |
| 1264 | const __m256i two_w = _mm256_set1_epi16(2); |
| 1265 | for (int i = 0; i < h; i += 2) { |
| 1266 | for (int j = 0; j < w; j += 16) { |
| 1267 | // Load 32x u8 alpha-mask values from each of four rows |
| 1268 | // (saturating) add pairs of rows, then use madd to add adjacent values |
| 1269 | // Finally, divide down each result with rounding |
| 1270 | const __m256i m0 = yy_loadu_256(mask + 0 * mask_stride + 2 * j); |
| 1271 | const __m256i m1 = yy_loadu_256(mask + 1 * mask_stride + 2 * j); |
| 1272 | const __m256i m2 = yy_loadu_256(mask + 2 * mask_stride + 2 * j); |
| 1273 | const __m256i m3 = yy_loadu_256(mask + 3 * mask_stride + 2 * j); |
| 1274 | |
| 1275 | const __m256i m01_8 = _mm256_adds_epu8(m0, m1); |
| 1276 | const __m256i m23_8 = _mm256_adds_epu8(m2, m3); |
| 1277 | |
| 1278 | const __m256i m01 = _mm256_maddubs_epi16(m01_8, one_b); |
| 1279 | const __m256i m23 = _mm256_maddubs_epi16(m23_8, one_b); |
| 1280 | |
| 1281 | const __m256i mask0a = _mm256_srli_epi16(_mm256_add_epi16(m01, two_w), 2); |
| 1282 | const __m256i mask0b = _mm256_srli_epi16(_mm256_add_epi16(m23, two_w), 2); |
| 1283 | |
| 1284 | highbd_blend_a64_d16_mask_w16_avx2( |
| 1285 | dst + j, dst_stride, src0 + j, src0_stride, src1 + j, src1_stride, |
| 1286 | &mask0a, &mask0b, round_offset, shift, clip_low, clip_high, mask_max); |
| 1287 | } |
| 1288 | dst += dst_stride * 2; |
| 1289 | src0 += src0_stride * 2; |
| 1290 | src1 += src1_stride * 2; |
| 1291 | mask += mask_stride * 4; |
| 1292 | } |
| 1293 | } |
| 1294 | |
| 1295 | void aom_highbd_blend_a64_d16_mask_avx2( |
| 1296 | uint8_t *dst8, uint32_t dst_stride, const CONV_BUF_TYPE *src0, |
| 1297 | uint32_t src0_stride, const CONV_BUF_TYPE *src1, uint32_t src1_stride, |
| 1298 | const uint8_t *mask, uint32_t mask_stride, int w, int h, int subw, int subh, |
| 1299 | ConvolveParams *conv_params, const int bd) { |
| 1300 | uint16_t *dst = CONVERT_TO_SHORTPTR(dst8); |
| 1301 | const int round_bits = |
| 1302 | 2 * FILTER_BITS - conv_params->round_0 - conv_params->round_1; |
| 1303 | const int32_t round_offset = |
| 1304 | ((1 << (round_bits + bd)) + (1 << (round_bits + bd - 1)) - |
| 1305 | (1 << (round_bits - 1))) |
| 1306 | << AOM_BLEND_A64_ROUND_BITS; |
| 1307 | const __m256i v_round_offset = _mm256_set1_epi32(round_offset); |
| 1308 | const int shift = round_bits + AOM_BLEND_A64_ROUND_BITS; |
| 1309 | |
| 1310 | const __m256i clip_low = _mm256_set1_epi16(0); |
| 1311 | const __m256i clip_high = _mm256_set1_epi16((1 << bd) - 1); |
| 1312 | const __m256i mask_max = _mm256_set1_epi16(AOM_BLEND_A64_MAX_ALPHA); |
| 1313 | |
| 1314 | assert(IMPLIES((void *)src0 == dst, src0_stride == dst_stride)); |
| 1315 | assert(IMPLIES((void *)src1 == dst, src1_stride == dst_stride)); |
| 1316 | |
| 1317 | assert(h >= 4); |
| 1318 | assert(w >= 4); |
| 1319 | assert(IS_POWER_OF_TWO(h)); |
| 1320 | assert(IS_POWER_OF_TWO(w)); |
| 1321 | |
| 1322 | if (subw == 0 && subh == 0) { |
| 1323 | switch (w) { |
| 1324 | case 4: |
| 1325 | highbd_blend_a64_d16_mask_subw0_subh0_w4_avx2( |
| 1326 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 1327 | mask_stride, h, &v_round_offset, shift, &clip_low, &clip_high, |
| 1328 | &mask_max); |
| 1329 | break; |
| 1330 | case 8: |
| 1331 | highbd_blend_a64_d16_mask_subw0_subh0_w8_avx2( |
| 1332 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 1333 | mask_stride, h, &v_round_offset, shift, &clip_low, &clip_high, |
| 1334 | &mask_max); |
| 1335 | break; |
| 1336 | default: // >= 16 |
| 1337 | highbd_blend_a64_d16_mask_subw0_subh0_w16_avx2( |
| 1338 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 1339 | mask_stride, h, w, &v_round_offset, shift, &clip_low, &clip_high, |
| 1340 | &mask_max); |
| 1341 | break; |
| 1342 | } |
| 1343 | |
| 1344 | } else if (subw == 1 && subh == 1) { |
| 1345 | switch (w) { |
| 1346 | case 4: |
| 1347 | highbd_blend_a64_d16_mask_subw1_subh1_w4_avx2( |
| 1348 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 1349 | mask_stride, h, &v_round_offset, shift, &clip_low, &clip_high, |
| 1350 | &mask_max); |
| 1351 | break; |
| 1352 | case 8: |
| 1353 | highbd_blend_a64_d16_mask_subw1_subh1_w8_avx2( |
| 1354 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 1355 | mask_stride, h, &v_round_offset, shift, &clip_low, &clip_high, |
| 1356 | &mask_max); |
| 1357 | break; |
| 1358 | default: // >= 16 |
| 1359 | highbd_blend_a64_d16_mask_subw1_subh1_w16_avx2( |
| 1360 | dst, dst_stride, src0, src0_stride, src1, src1_stride, mask, |
| 1361 | mask_stride, h, w, &v_round_offset, shift, &clip_low, &clip_high, |
| 1362 | &mask_max); |
| 1363 | break; |
| 1364 | } |
| 1365 | } else { |
| 1366 | // Sub-sampling in only one axis doesn't seem to happen very much, so fall |
| 1367 | // back to the vanilla C implementation instead of having all the optimised |
| 1368 | // code for these. |
| 1369 | aom_highbd_blend_a64_d16_mask_c(dst8, dst_stride, src0, src0_stride, src1, |
| 1370 | src1_stride, mask, mask_stride, w, h, subw, |
| 1371 | subh, conv_params, bd); |
| 1372 | } |
| 1373 | } |