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Yaowu Xuc27fc142016-08-22 16:08:15 -07001/*
Yaowu Xu2ab7ff02016-09-02 12:04:54 -07002 * Copyright (c) 2016, Alliance for Open Media. All rights reserved
Yaowu Xuc27fc142016-08-22 16:08:15 -07003 *
Yaowu Xu2ab7ff02016-09-02 12:04:54 -07004 * This source code is subject to the terms of the BSD 2 Clause License and
5 * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
6 * was not distributed with this source code in the LICENSE file, you can
7 * obtain it at www.aomedia.org/license/software. If the Alliance for Open
8 * Media Patent License 1.0 was not distributed with this source code in the
9 * PATENTS file, you can obtain it at www.aomedia.org/license/patent.
Yaowu Xuc27fc142016-08-22 16:08:15 -070010 */
11
James Zerne1cbb132018-08-22 14:10:36 -070012#ifndef AOM_AV1_ENCODER_RD_H_
13#define AOM_AV1_ENCODER_RD_H_
Yaowu Xuc27fc142016-08-22 16:08:15 -070014
15#include <limits.h>
16
Yaowu Xuc27fc142016-08-22 16:08:15 -070017#include "av1/common/blockd.h"
18
19#include "av1/encoder/block.h"
20#include "av1/encoder/context_tree.h"
21#include "av1/encoder/cost.h"
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#define RDDIV_BITS 7
28#define RD_EPB_SHIFT 6
29
Angie Chiange4ea7482018-03-15 11:36:41 -070030#define RDCOST(RM, R, D) \
31 (ROUND_POWER_OF_TWO(((int64_t)(R)) * (RM), AV1_PROB_COST_SHIFT) + \
32 ((D) * (1 << RDDIV_BITS)))
Yaowu Xuc27fc142016-08-22 16:08:15 -070033
sdeng256c4d32019-06-11 12:19:48 -070034#define RDCOST_NEG_R(RM, R, D) \
35 (((D) * (1 << RDDIV_BITS)) - \
36 ROUND_POWER_OF_TWO(((int64_t)(R)) * (RM), AV1_PROB_COST_SHIFT))
37
Urvang Joshi70006e42017-06-14 16:08:55 -070038#define RDCOST_DBL(RM, R, D) \
Yaowu Xuf883b422016-08-30 14:01:10 -070039 (((((double)(R)) * (RM)) / (double)(1 << AV1_PROB_COST_SHIFT)) + \
Urvang Joshi70006e42017-06-14 16:08:55 -070040 ((double)(D) * (1 << RDDIV_BITS)))
Yaowu Xuc27fc142016-08-22 16:08:15 -070041
42#define QIDX_SKIP_THRESH 115
43
44#define MV_COST_WEIGHT 108
45#define MV_COST_WEIGHT_SUB 120
46
Yaowu Xuc27fc142016-08-22 16:08:15 -070047#define RD_THRESH_MAX_FACT 64
48#define RD_THRESH_INC 1
49
Peng Binc7101aa2018-06-22 20:47:05 +080050// Factor to weigh the rate for switchable interp filters.
51#define SWITCHABLE_INTERP_RATE_FACTOR 1
52
Yaowu Xuc27fc142016-08-22 16:08:15 -070053// This enumerator type needs to be kept aligned with the mode order in
Yaowu Xuf883b422016-08-30 14:01:10 -070054// const MODE_DEFINITION av1_mode_order[MAX_MODES] used in the rd code.
Satish Kumar Suman4667aa12018-12-14 18:28:19 +053055enum {
Yaowu Xuc27fc142016-08-22 16:08:15 -070056 THR_NEARESTMV,
Yaowu Xuc27fc142016-08-22 16:08:15 -070057 THR_NEARESTL2,
58 THR_NEARESTL3,
59 THR_NEARESTB,
Zoe Liue9b15e22017-07-19 15:53:01 -070060 THR_NEARESTA2,
Yaowu Xuc27fc142016-08-22 16:08:15 -070061 THR_NEARESTA,
62 THR_NEARESTG,
63
Yaowu Xuc27fc142016-08-22 16:08:15 -070064 THR_NEWMV,
Yaowu Xuc27fc142016-08-22 16:08:15 -070065 THR_NEWL2,
66 THR_NEWL3,
67 THR_NEWB,
Zoe Liue9b15e22017-07-19 15:53:01 -070068 THR_NEWA2,
Yaowu Xuc27fc142016-08-22 16:08:15 -070069 THR_NEWA,
70 THR_NEWG,
71
72 THR_NEARMV,
Yaowu Xuc27fc142016-08-22 16:08:15 -070073 THR_NEARL2,
74 THR_NEARL3,
75 THR_NEARB,
Zoe Liue9b15e22017-07-19 15:53:01 -070076 THR_NEARA2,
Yaowu Xuc27fc142016-08-22 16:08:15 -070077 THR_NEARA,
78 THR_NEARG,
79
Sarah Parker2b9ec2e2017-10-30 17:34:08 -070080 THR_GLOBALMV,
Debargha Mukherjeeae2f3cf2017-11-06 18:44:00 -080081 THR_GLOBALL2,
82 THR_GLOBALL3,
83 THR_GLOBALB,
84 THR_GLOBALA2,
Debargha Mukherjeeae2f3cf2017-11-06 18:44:00 -080085 THR_GLOBALG,
elliottk05fed212019-04-01 23:05:51 -070086 THR_GLOBALA,
Yaowu Xuc27fc142016-08-22 16:08:15 -070087
Yaowu Xuc27fc142016-08-22 16:08:15 -070088 THR_COMP_NEAREST_NEARESTLA,
Yaowu Xuc27fc142016-08-22 16:08:15 -070089 THR_COMP_NEAREST_NEARESTL2A,
90 THR_COMP_NEAREST_NEARESTL3A,
Yaowu Xuc27fc142016-08-22 16:08:15 -070091 THR_COMP_NEAREST_NEARESTGA,
Yaowu Xuc27fc142016-08-22 16:08:15 -070092 THR_COMP_NEAREST_NEARESTLB,
93 THR_COMP_NEAREST_NEARESTL2B,
94 THR_COMP_NEAREST_NEARESTL3B,
95 THR_COMP_NEAREST_NEARESTGB,
Zoe Liue9b15e22017-07-19 15:53:01 -070096 THR_COMP_NEAREST_NEARESTLA2,
97 THR_COMP_NEAREST_NEARESTL2A2,
98 THR_COMP_NEAREST_NEARESTL3A2,
99 THR_COMP_NEAREST_NEARESTGA2,
Zoe Liuc082bbc2017-05-17 13:31:37 -0700100 THR_COMP_NEAREST_NEARESTLL2,
Zoe Liufcf5fa22017-06-26 16:00:38 -0700101 THR_COMP_NEAREST_NEARESTLL3,
Zoe Liuc082bbc2017-05-17 13:31:37 -0700102 THR_COMP_NEAREST_NEARESTLG,
103 THR_COMP_NEAREST_NEARESTBA,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700104
Yaowu Xuc27fc142016-08-22 16:08:15 -0700105 THR_COMP_NEAR_NEARLA,
106 THR_COMP_NEW_NEARESTLA,
107 THR_COMP_NEAREST_NEWLA,
108 THR_COMP_NEW_NEARLA,
109 THR_COMP_NEAR_NEWLA,
110 THR_COMP_NEW_NEWLA,
Debargha Mukherjeeae2f3cf2017-11-06 18:44:00 -0800111 THR_COMP_GLOBAL_GLOBALLA,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700112
Yaowu Xuc27fc142016-08-22 16:08:15 -0700113 THR_COMP_NEAR_NEARL2A,
114 THR_COMP_NEW_NEARESTL2A,
115 THR_COMP_NEAREST_NEWL2A,
116 THR_COMP_NEW_NEARL2A,
117 THR_COMP_NEAR_NEWL2A,
118 THR_COMP_NEW_NEWL2A,
Debargha Mukherjeeae2f3cf2017-11-06 18:44:00 -0800119 THR_COMP_GLOBAL_GLOBALL2A,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700120
Yaowu Xuc27fc142016-08-22 16:08:15 -0700121 THR_COMP_NEAR_NEARL3A,
122 THR_COMP_NEW_NEARESTL3A,
123 THR_COMP_NEAREST_NEWL3A,
124 THR_COMP_NEW_NEARL3A,
125 THR_COMP_NEAR_NEWL3A,
126 THR_COMP_NEW_NEWL3A,
Debargha Mukherjeeae2f3cf2017-11-06 18:44:00 -0800127 THR_COMP_GLOBAL_GLOBALL3A,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700128
Yaowu Xuc27fc142016-08-22 16:08:15 -0700129 THR_COMP_NEAR_NEARGA,
130 THR_COMP_NEW_NEARESTGA,
131 THR_COMP_NEAREST_NEWGA,
132 THR_COMP_NEW_NEARGA,
133 THR_COMP_NEAR_NEWGA,
134 THR_COMP_NEW_NEWGA,
Debargha Mukherjeeae2f3cf2017-11-06 18:44:00 -0800135 THR_COMP_GLOBAL_GLOBALGA,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700136
Yaowu Xuc27fc142016-08-22 16:08:15 -0700137 THR_COMP_NEAR_NEARLB,
138 THR_COMP_NEW_NEARESTLB,
139 THR_COMP_NEAREST_NEWLB,
140 THR_COMP_NEW_NEARLB,
141 THR_COMP_NEAR_NEWLB,
142 THR_COMP_NEW_NEWLB,
Debargha Mukherjeeae2f3cf2017-11-06 18:44:00 -0800143 THR_COMP_GLOBAL_GLOBALLB,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700144
Yaowu Xuc27fc142016-08-22 16:08:15 -0700145 THR_COMP_NEAR_NEARL2B,
146 THR_COMP_NEW_NEARESTL2B,
147 THR_COMP_NEAREST_NEWL2B,
148 THR_COMP_NEW_NEARL2B,
149 THR_COMP_NEAR_NEWL2B,
150 THR_COMP_NEW_NEWL2B,
Debargha Mukherjeeae2f3cf2017-11-06 18:44:00 -0800151 THR_COMP_GLOBAL_GLOBALL2B,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700152
Yaowu Xuc27fc142016-08-22 16:08:15 -0700153 THR_COMP_NEAR_NEARL3B,
154 THR_COMP_NEW_NEARESTL3B,
155 THR_COMP_NEAREST_NEWL3B,
156 THR_COMP_NEW_NEARL3B,
157 THR_COMP_NEAR_NEWL3B,
158 THR_COMP_NEW_NEWL3B,
Debargha Mukherjeeae2f3cf2017-11-06 18:44:00 -0800159 THR_COMP_GLOBAL_GLOBALL3B,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700160
Yaowu Xuc27fc142016-08-22 16:08:15 -0700161 THR_COMP_NEAR_NEARGB,
162 THR_COMP_NEW_NEARESTGB,
163 THR_COMP_NEAREST_NEWGB,
164 THR_COMP_NEW_NEARGB,
165 THR_COMP_NEAR_NEWGB,
166 THR_COMP_NEW_NEWGB,
Debargha Mukherjeeae2f3cf2017-11-06 18:44:00 -0800167 THR_COMP_GLOBAL_GLOBALGB,
Zoe Liuc082bbc2017-05-17 13:31:37 -0700168
Zoe Liue9b15e22017-07-19 15:53:01 -0700169 THR_COMP_NEAR_NEARLA2,
170 THR_COMP_NEW_NEARESTLA2,
171 THR_COMP_NEAREST_NEWLA2,
172 THR_COMP_NEW_NEARLA2,
173 THR_COMP_NEAR_NEWLA2,
174 THR_COMP_NEW_NEWLA2,
Debargha Mukherjeeae2f3cf2017-11-06 18:44:00 -0800175 THR_COMP_GLOBAL_GLOBALLA2,
Zoe Liue9b15e22017-07-19 15:53:01 -0700176
177 THR_COMP_NEAR_NEARL2A2,
178 THR_COMP_NEW_NEARESTL2A2,
179 THR_COMP_NEAREST_NEWL2A2,
180 THR_COMP_NEW_NEARL2A2,
181 THR_COMP_NEAR_NEWL2A2,
182 THR_COMP_NEW_NEWL2A2,
Debargha Mukherjeeae2f3cf2017-11-06 18:44:00 -0800183 THR_COMP_GLOBAL_GLOBALL2A2,
Zoe Liue9b15e22017-07-19 15:53:01 -0700184
185 THR_COMP_NEAR_NEARL3A2,
186 THR_COMP_NEW_NEARESTL3A2,
187 THR_COMP_NEAREST_NEWL3A2,
188 THR_COMP_NEW_NEARL3A2,
189 THR_COMP_NEAR_NEWL3A2,
190 THR_COMP_NEW_NEWL3A2,
Debargha Mukherjeeae2f3cf2017-11-06 18:44:00 -0800191 THR_COMP_GLOBAL_GLOBALL3A2,
Zoe Liue9b15e22017-07-19 15:53:01 -0700192
193 THR_COMP_NEAR_NEARGA2,
194 THR_COMP_NEW_NEARESTGA2,
195 THR_COMP_NEAREST_NEWGA2,
196 THR_COMP_NEW_NEARGA2,
197 THR_COMP_NEAR_NEWGA2,
198 THR_COMP_NEW_NEWGA2,
Debargha Mukherjeeae2f3cf2017-11-06 18:44:00 -0800199 THR_COMP_GLOBAL_GLOBALGA2,
Zoe Liue9b15e22017-07-19 15:53:01 -0700200
Debargha Mukherjeec1077e92017-11-06 20:17:33 -0800201 THR_COMP_NEAR_NEARLL2,
202 THR_COMP_NEW_NEARESTLL2,
203 THR_COMP_NEAREST_NEWLL2,
204 THR_COMP_NEW_NEARLL2,
205 THR_COMP_NEAR_NEWLL2,
206 THR_COMP_NEW_NEWLL2,
207 THR_COMP_GLOBAL_GLOBALLL2,
208
209 THR_COMP_NEAR_NEARLL3,
210 THR_COMP_NEW_NEARESTLL3,
211 THR_COMP_NEAREST_NEWLL3,
212 THR_COMP_NEW_NEARLL3,
213 THR_COMP_NEAR_NEWLL3,
214 THR_COMP_NEW_NEWLL3,
215 THR_COMP_GLOBAL_GLOBALLL3,
216
217 THR_COMP_NEAR_NEARLG,
218 THR_COMP_NEW_NEARESTLG,
219 THR_COMP_NEAREST_NEWLG,
220 THR_COMP_NEW_NEARLG,
221 THR_COMP_NEAR_NEWLG,
222 THR_COMP_NEW_NEWLG,
223 THR_COMP_GLOBAL_GLOBALLG,
224
225 THR_COMP_NEAR_NEARBA,
226 THR_COMP_NEW_NEARESTBA,
227 THR_COMP_NEAREST_NEWBA,
228 THR_COMP_NEW_NEARBA,
229 THR_COMP_NEAR_NEWBA,
230 THR_COMP_NEW_NEWBA,
231 THR_COMP_GLOBAL_GLOBALBA,
Debargha Mukherjeec1077e92017-11-06 20:17:33 -0800232
Peng Binbb82e052018-09-10 12:15:19 +0800233 THR_DC,
234 THR_PAETH,
235 THR_SMOOTH,
236 THR_SMOOTH_V,
237 THR_SMOOTH_H,
238 THR_H_PRED,
239 THR_V_PRED,
240 THR_D135_PRED,
241 THR_D203_PRED,
242 THR_D157_PRED,
243 THR_D67_PRED,
244 THR_D113_PRED,
245 THR_D45_PRED,
246
247 MAX_MODES,
248
249 LAST_SINGLE_REF_MODES = THR_GLOBALG,
250 MAX_SINGLE_REF_MODES = LAST_SINGLE_REF_MODES + 1,
251 LAST_COMP_REF_MODES = THR_COMP_GLOBAL_GLOBALBA,
252 MAX_COMP_REF_MODES = LAST_COMP_REF_MODES + 1
Satish Kumar Suman4667aa12018-12-14 18:28:19 +0530253} UENUM1BYTE(THR_MODES);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700254
Satish Kumar Suman4667aa12018-12-14 18:28:19 +0530255enum {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700256 THR_LAST,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700257 THR_LAST2,
258 THR_LAST3,
259 THR_BWDR,
Zoe Liue9b15e22017-07-19 15:53:01 -0700260 THR_ALTR2,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700261 THR_GOLD,
262 THR_ALTR,
263
264 THR_COMP_LA,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700265 THR_COMP_L2A,
266 THR_COMP_L3A,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700267 THR_COMP_GA,
268
Yaowu Xuc27fc142016-08-22 16:08:15 -0700269 THR_COMP_LB,
270 THR_COMP_L2B,
271 THR_COMP_L3B,
272 THR_COMP_GB,
Zoe Liue9b15e22017-07-19 15:53:01 -0700273
Zoe Liue9b15e22017-07-19 15:53:01 -0700274 THR_COMP_LA2,
275 THR_COMP_L2A2,
276 THR_COMP_L3A2,
277 THR_COMP_GA2,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700278
279 THR_INTRA,
Zoe Liue9b15e22017-07-19 15:53:01 -0700280
281 MAX_REFS
Satish Kumar Suman4667aa12018-12-14 18:28:19 +0530282} UENUM1BYTE(THR_MODES_SUB8X8);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700283
284typedef struct RD_OPT {
285 // Thresh_mult is used to set a threshold for the rd score. A higher value
286 // means that we will accept the best mode so far more often. This number
287 // is used in combination with the current block size, and thresh_freq_fact
288 // to pick a threshold.
289 int thresh_mult[MAX_MODES];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700290
Rupert Swarbrick93c39e92017-07-12 11:11:02 +0100291 int threshes[MAX_SEGMENTS][BLOCK_SIZES_ALL][MAX_MODES];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700292
Zoe Liu27deb382018-03-27 15:13:56 -0700293 int64_t prediction_type_threshes[REF_FRAMES][REFERENCE_MODES];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700294
295 int RDMULT;
Yue Chen7cae98f2018-08-24 10:43:16 -0700296
Debargha Mukherjeed0c0b772019-05-27 23:05:06 -0700297 double r0, arf_r0;
Debargha Mukherjee88ff7382019-05-01 12:36:10 -0700298 double mc_saved_base, mc_count_base;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700299} RD_OPT;
300
Angie Chiang2a2a7dd2017-04-25 16:08:47 -0700301static INLINE void av1_init_rd_stats(RD_STATS *rd_stats) {
302#if CONFIG_RD_DEBUG
303 int plane;
304#endif
305 rd_stats->rate = 0;
306 rd_stats->dist = 0;
307 rd_stats->rdcost = 0;
308 rd_stats->sse = 0;
309 rd_stats->skip = 1;
Jingning Han3bce7542017-07-25 10:53:57 -0700310 rd_stats->zero_rate = 0;
Angie Chiang2a2a7dd2017-04-25 16:08:47 -0700311#if CONFIG_RD_DEBUG
Imdad Sardharwallaaf8e2642018-01-19 11:46:34 +0000312 // This may run into problems when monochrome video is
313 // encoded, as there will only be 1 plane
Angie Chiang2a2a7dd2017-04-25 16:08:47 -0700314 for (plane = 0; plane < MAX_MB_PLANE; ++plane) {
315 rd_stats->txb_coeff_cost[plane] = 0;
Angie Chiang2a2a7dd2017-04-25 16:08:47 -0700316 {
317 int r, c;
318 for (r = 0; r < TXB_COEFF_COST_MAP_SIZE; ++r)
319 for (c = 0; c < TXB_COEFF_COST_MAP_SIZE; ++c)
320 rd_stats->txb_coeff_cost_map[plane][r][c] = 0;
321 }
Angie Chiang2a2a7dd2017-04-25 16:08:47 -0700322 }
323#endif
324}
Yaowu Xuc27fc142016-08-22 16:08:15 -0700325
Angie Chiang2a2a7dd2017-04-25 16:08:47 -0700326static INLINE void av1_invalid_rd_stats(RD_STATS *rd_stats) {
327#if CONFIG_RD_DEBUG
328 int plane;
329#endif
330 rd_stats->rate = INT_MAX;
331 rd_stats->dist = INT64_MAX;
332 rd_stats->rdcost = INT64_MAX;
333 rd_stats->sse = INT64_MAX;
334 rd_stats->skip = 0;
Jingning Han3bce7542017-07-25 10:53:57 -0700335 rd_stats->zero_rate = 0;
Angie Chiang2a2a7dd2017-04-25 16:08:47 -0700336#if CONFIG_RD_DEBUG
Imdad Sardharwallaaf8e2642018-01-19 11:46:34 +0000337 // This may run into problems when monochrome video is
338 // encoded, as there will only be 1 plane
Angie Chiang2a2a7dd2017-04-25 16:08:47 -0700339 for (plane = 0; plane < MAX_MB_PLANE; ++plane) {
340 rd_stats->txb_coeff_cost[plane] = INT_MAX;
Angie Chiang2a2a7dd2017-04-25 16:08:47 -0700341 {
342 int r, c;
343 for (r = 0; r < TXB_COEFF_COST_MAP_SIZE; ++r)
344 for (c = 0; c < TXB_COEFF_COST_MAP_SIZE; ++c)
345 rd_stats->txb_coeff_cost_map[plane][r][c] = INT_MAX;
346 }
Angie Chiang2a2a7dd2017-04-25 16:08:47 -0700347 }
348#endif
349}
350
351static INLINE void av1_merge_rd_stats(RD_STATS *rd_stats_dst,
352 const RD_STATS *rd_stats_src) {
Hui Sucd735502019-04-08 11:23:02 -0700353 assert(rd_stats_dst->rate != INT_MAX && rd_stats_src->rate != INT_MAX);
Angie Chiang2a2a7dd2017-04-25 16:08:47 -0700354 rd_stats_dst->rate += rd_stats_src->rate;
Debargha Mukherjeede80e762017-11-30 13:58:56 -0800355 if (!rd_stats_dst->zero_rate)
356 rd_stats_dst->zero_rate = rd_stats_src->zero_rate;
Angie Chiang2a2a7dd2017-04-25 16:08:47 -0700357 rd_stats_dst->dist += rd_stats_src->dist;
358 rd_stats_dst->sse += rd_stats_src->sse;
359 rd_stats_dst->skip &= rd_stats_src->skip;
360#if CONFIG_RD_DEBUG
Imdad Sardharwallaaf8e2642018-01-19 11:46:34 +0000361 // This may run into problems when monochrome video is
362 // encoded, as there will only be 1 plane
Hui Sucd735502019-04-08 11:23:02 -0700363 for (int plane = 0; plane < MAX_MB_PLANE; ++plane) {
Angie Chiang2a2a7dd2017-04-25 16:08:47 -0700364 rd_stats_dst->txb_coeff_cost[plane] += rd_stats_src->txb_coeff_cost[plane];
Angie Chiang2a2a7dd2017-04-25 16:08:47 -0700365 {
366 // TODO(angiebird): optimize this part
367 int r, c;
368 int ref_txb_coeff_cost = 0;
369 for (r = 0; r < TXB_COEFF_COST_MAP_SIZE; ++r)
370 for (c = 0; c < TXB_COEFF_COST_MAP_SIZE; ++c) {
371 rd_stats_dst->txb_coeff_cost_map[plane][r][c] +=
372 rd_stats_src->txb_coeff_cost_map[plane][r][c];
373 ref_txb_coeff_cost += rd_stats_dst->txb_coeff_cost_map[plane][r][c];
374 }
375 assert(ref_txb_coeff_cost == rd_stats_dst->txb_coeff_cost[plane]);
376 }
Angie Chiang2a2a7dd2017-04-25 16:08:47 -0700377 }
378#endif
379}
Yaowu Xuc27fc142016-08-22 16:08:15 -0700380
sdeng256c4d32019-06-11 12:19:48 -0700381static INLINE int64_t av1_calculate_rd_cost(int mult, int rate, int64_t dist) {
382 assert(mult >= 0);
383 if (rate >= 0) {
384 return RDCOST(mult, rate, dist);
385 }
386 return RDCOST_NEG_R(mult, -rate, dist);
387}
388
389static INLINE void av1_rd_cost_update(int mult, RD_STATS *rd_cost) {
390 if (rd_cost->rate < INT_MAX && rd_cost->dist < INT64_MAX) {
391 rd_cost->rdcost = av1_calculate_rd_cost(mult, rd_cost->rate, rd_cost->dist);
392 } else {
393 av1_invalid_rd_stats(rd_cost);
394 }
395}
396
sdengeff3bb42019-06-11 15:56:04 -0700397static INLINE void av1_rd_stats_subtraction(const RD_STATS *const left,
398 const RD_STATS *const right,
399 RD_STATS *result) {
400 if (left->rate == INT_MAX || right->rate == INT_MAX ||
401 left->dist == INT64_MAX || right->dist == INT64_MAX ||
402 left->rdcost == INT64_MAX || right->rdcost == INT64_MAX) {
403 av1_invalid_rd_stats(result);
404 } else {
405 result->rate = left->rate - right->rate;
406 result->dist = left->dist - right->dist;
407 result->rdcost = left->rdcost - right->rdcost;
408 }
409}
410
Yaowu Xuc27fc142016-08-22 16:08:15 -0700411struct TileInfo;
412struct TileDataEnc;
Yaowu Xuf883b422016-08-30 14:01:10 -0700413struct AV1_COMP;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700414struct macroblock;
415
Yaowu Xuea8a6ca2018-11-07 14:53:46 -0800416int av1_compute_rd_mult_based_on_qindex(const struct AV1_COMP *cpi, int qindex);
Ravi Chaudhary95492052018-10-24 11:51:28 +0530417
Yaowu Xuf883b422016-08-30 14:01:10 -0700418int av1_compute_rd_mult(const struct AV1_COMP *cpi, int qindex);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700419
Yaowu Xuf883b422016-08-30 14:01:10 -0700420void av1_initialize_rd_consts(struct AV1_COMP *cpi);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700421
Ravi Chaudhary95492052018-10-24 11:51:28 +0530422void av1_initialize_cost_tables(const AV1_COMMON *const cm, MACROBLOCK *x);
423
Yaowu Xuf883b422016-08-30 14:01:10 -0700424void av1_initialize_me_consts(const struct AV1_COMP *cpi, MACROBLOCK *x,
425 int qindex);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700426
Yaowu Xuf883b422016-08-30 14:01:10 -0700427void av1_model_rd_from_var_lapndz(int64_t var, unsigned int n,
428 unsigned int qstep, int *rate, int64_t *dist);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700429
Debargha Mukherjee00079832019-01-17 11:28:52 -0800430void av1_model_rd_curvfit(BLOCK_SIZE bsize, double sse_norm, double xqr,
Debargha Mukherjeea7b37312019-01-14 15:15:49 -0800431 double *rate_f, double *distbysse_f);
Debargha Mukherjee00079832019-01-17 11:28:52 -0800432void av1_model_rd_surffit(BLOCK_SIZE bsize, double sse_norm, double xm,
433 double yl, double *rate_f, double *distbysse_f);
Debargha Mukherjee483e2952018-07-25 07:34:26 -0700434
Yue Chenb23d00a2017-07-28 17:01:21 -0700435int av1_get_switchable_rate(const AV1_COMMON *const cm, MACROBLOCK *x,
436 const MACROBLOCKD *xd);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700437
Yaowu Xuf883b422016-08-30 14:01:10 -0700438int av1_raster_block_offset(BLOCK_SIZE plane_bsize, int raster_block,
439 int stride);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700440
Yaowu Xuf883b422016-08-30 14:01:10 -0700441int16_t *av1_raster_block_offset_int16(BLOCK_SIZE plane_bsize, int raster_block,
442 int16_t *base);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700443
Yaowu Xuf883b422016-08-30 14:01:10 -0700444YV12_BUFFER_CONFIG *av1_get_scaled_ref_frame(const struct AV1_COMP *cpi,
445 int ref_frame);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700446
Yaowu Xuf883b422016-08-30 14:01:10 -0700447void av1_init_me_luts(void);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700448
Yaowu Xu901d6222018-02-21 21:40:48 -0800449void av1_set_mvcost(MACROBLOCK *x, int ref, int ref_mv_idx);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700450
Yunqing Wangef2afb42018-05-01 09:41:00 -0700451void av1_get_entropy_contexts(BLOCK_SIZE bsize,
Yaowu Xuf883b422016-08-30 14:01:10 -0700452 const struct macroblockd_plane *pd,
Wan-Teh Chang660f8ed2018-05-11 17:28:08 -0700453 ENTROPY_CONTEXT t_above[MAX_MIB_SIZE],
454 ENTROPY_CONTEXT t_left[MAX_MIB_SIZE]);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700455
Yaowu Xuf883b422016-08-30 14:01:10 -0700456void av1_set_rd_speed_thresholds(struct AV1_COMP *cpi);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700457
Yaowu Xuf883b422016-08-30 14:01:10 -0700458void av1_update_rd_thresh_fact(const AV1_COMMON *const cm,
459 int (*fact)[MAX_MODES], int rd_thresh, int bsize,
460 int best_mode_index);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700461
Yaowu Xuc27fc142016-08-22 16:08:15 -0700462static INLINE int rd_less_than_thresh(int64_t best_rd, int thresh,
463 int thresh_fact) {
464 return best_rd < ((int64_t)thresh * thresh_fact >> 5) || thresh == INT_MAX;
465}
466
Urvang Joshi52648442016-10-13 17:27:51 -0700467void av1_mv_pred(const struct AV1_COMP *cpi, MACROBLOCK *x,
468 uint8_t *ref_y_buffer, int ref_y_stride, int ref_frame,
469 BLOCK_SIZE block_size);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700470
471static INLINE void set_error_per_bit(MACROBLOCK *x, int rdmult) {
472 x->errorperbit = rdmult >> RD_EPB_SHIFT;
473 x->errorperbit += (x->errorperbit == 0);
474}
475
Yaowu Xuf883b422016-08-30 14:01:10 -0700476void av1_setup_pred_block(const MACROBLOCKD *xd,
477 struct buf_2d dst[MAX_MB_PLANE],
478 const YV12_BUFFER_CONFIG *src, int mi_row, int mi_col,
479 const struct scale_factors *scale,
Imdad Sardharwallaaf8e2642018-01-19 11:46:34 +0000480 const struct scale_factors *scale_uv,
481 const int num_planes);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700482
Yaowu Xuf883b422016-08-30 14:01:10 -0700483int av1_get_intra_cost_penalty(int qindex, int qdelta,
484 aom_bit_depth_t bit_depth);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700485
Yue Chenb23d00a2017-07-28 17:01:21 -0700486void av1_fill_mode_rates(AV1_COMMON *const cm, MACROBLOCK *x,
487 FRAME_CONTEXT *fc);
488
Imdad Sardharwallaaf8e2642018-01-19 11:46:34 +0000489void av1_fill_coeff_costs(MACROBLOCK *x, FRAME_CONTEXT *fc,
490 const int num_planes);
Jingning Handfd72322017-08-09 14:04:12 -0700491
Yue Chen7cae98f2018-08-24 10:43:16 -0700492int av1_get_adaptive_rdmult(const struct AV1_COMP *cpi, double beta);
493
Debargha Mukherjeecfcd5ad2019-05-20 20:27:17 -0700494int av1_get_deltaq_offset(const struct AV1_COMP *cpi, int qindex, double beta);
495
Yaowu Xuc27fc142016-08-22 16:08:15 -0700496#ifdef __cplusplus
497} // extern "C"
498#endif
499
James Zerne1cbb132018-08-22 14:10:36 -0700500#endif // AOM_AV1_ENCODER_RD_H_