Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, Alliance for Open Media. All rights reserved |
| 3 | * |
| 4 | * This source code is subject to the terms of the BSD 2 Clause License and |
| 5 | * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License |
| 6 | * was not distributed with this source code in the LICENSE file, you can |
| 7 | * obtain it at www.aomedia.org/license/software. If the Alliance for Open |
| 8 | * Media Patent License 1.0 was not distributed with this source code in the |
| 9 | * PATENTS file, you can obtain it at www.aomedia.org/license/patent. |
| 10 | */ |
| 11 | |
| 12 | #define SIMD_CHECK 1 |
Tom Finegan | 7a07ece | 2017-02-07 17:14:05 -0800 | [diff] [blame] | 13 | #include "third_party/googletest/src/googletest/include/gtest/gtest.h" |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 14 | #include "test/clear_system_state.h" |
| 15 | #include "test/register_state_check.h" |
| 16 | #include "aom_dsp/aom_simd_inline.h" |
Steinar Midtskogen | 1e42436 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 17 | #include "aom_dsp/simd/v256_intrinsics_c.h" |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 18 | |
| 19 | namespace SIMD_NAMESPACE { |
| 20 | |
| 21 | template <typename param_signature> |
| 22 | class TestIntrinsic : public ::testing::TestWithParam<param_signature> { |
| 23 | public: |
| 24 | virtual ~TestIntrinsic() {} |
| 25 | virtual void SetUp() { |
| 26 | mask = std::tr1::get<0>(this->GetParam()); |
| 27 | maskwidth = std::tr1::get<1>(this->GetParam()); |
| 28 | name = std::tr1::get<2>(this->GetParam()); |
| 29 | } |
| 30 | |
| 31 | virtual void TearDown() { libaom_test::ClearSystemState(); } |
| 32 | |
| 33 | protected: |
| 34 | uint32_t mask, maskwidth; |
| 35 | const char *name; |
| 36 | }; |
| 37 | |
| 38 | // Create one typedef for each function signature |
| 39 | #define TYPEDEF_SIMD(name) \ |
| 40 | typedef TestIntrinsic<std::tr1::tuple<uint32_t, uint32_t, const char *> > \ |
| 41 | ARCH_POSTFIX(name) |
| 42 | |
Steinar Midtskogen | 6c79576 | 2017-03-07 20:55:48 +0100 | [diff] [blame] | 43 | TYPEDEF_SIMD(V64_U8); |
| 44 | TYPEDEF_SIMD(V64_U16); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 45 | TYPEDEF_SIMD(V64_U32); |
| 46 | TYPEDEF_SIMD(V64_V64); |
| 47 | TYPEDEF_SIMD(U32_V64); |
Steinar Midtskogen | 6c79576 | 2017-03-07 20:55:48 +0100 | [diff] [blame] | 48 | TYPEDEF_SIMD(S32_V64); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 49 | TYPEDEF_SIMD(U64_V64); |
Steinar Midtskogen | 6c79576 | 2017-03-07 20:55:48 +0100 | [diff] [blame] | 50 | TYPEDEF_SIMD(S64_V64); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 51 | TYPEDEF_SIMD(V64_U32U32); |
| 52 | TYPEDEF_SIMD(V64_V64V64); |
| 53 | TYPEDEF_SIMD(S64_V64V64); |
| 54 | TYPEDEF_SIMD(V64_V64U32); |
| 55 | TYPEDEF_SIMD(U32_V64V64); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 56 | TYPEDEF_SIMD(V128_V64); |
| 57 | TYPEDEF_SIMD(V128_V128); |
| 58 | TYPEDEF_SIMD(U32_V128); |
| 59 | TYPEDEF_SIMD(U64_V128); |
| 60 | TYPEDEF_SIMD(V64_V128); |
Steinar Midtskogen | 6c79576 | 2017-03-07 20:55:48 +0100 | [diff] [blame] | 61 | TYPEDEF_SIMD(V128_U8); |
| 62 | TYPEDEF_SIMD(V128_U16); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 63 | TYPEDEF_SIMD(V128_U32); |
| 64 | TYPEDEF_SIMD(V128_U64U64); |
| 65 | TYPEDEF_SIMD(V128_V64V64); |
| 66 | TYPEDEF_SIMD(V128_V128V128); |
| 67 | TYPEDEF_SIMD(S64_V128V128); |
| 68 | TYPEDEF_SIMD(V128_V128U32); |
| 69 | TYPEDEF_SIMD(U32_V128V128); |
Steinar Midtskogen | 1e42436 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 70 | TYPEDEF_SIMD(V256_V128); |
| 71 | TYPEDEF_SIMD(V256_V256); |
| 72 | TYPEDEF_SIMD(U64_V256); |
| 73 | TYPEDEF_SIMD(V256_V128V128); |
| 74 | TYPEDEF_SIMD(V256_V256V256); |
| 75 | TYPEDEF_SIMD(S64_V256V256); |
| 76 | TYPEDEF_SIMD(V256_V256U32); |
| 77 | TYPEDEF_SIMD(U32_V256V256); |
| 78 | TYPEDEF_SIMD(V256_U8); |
| 79 | TYPEDEF_SIMD(V256_U16); |
| 80 | TYPEDEF_SIMD(V256_U32); |
| 81 | TYPEDEF_SIMD(U32_V256); |
| 82 | TYPEDEF_SIMD(V64_V256); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 83 | |
| 84 | // Google Test allows up to 50 tests per case, so split the largest |
| 85 | typedef ARCH_POSTFIX(V64_V64) ARCH_POSTFIX(V64_V64_Part2); |
| 86 | typedef ARCH_POSTFIX(V64_V64V64) ARCH_POSTFIX(V64_V64V64_Part2); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 87 | typedef ARCH_POSTFIX(V128_V128) ARCH_POSTFIX(V128_V128_Part2); |
| 88 | typedef ARCH_POSTFIX(V128_V128) ARCH_POSTFIX(V128_V128_Part3); |
| 89 | typedef ARCH_POSTFIX(V128_V128V128) ARCH_POSTFIX(V128_V128V128_Part2); |
Steinar Midtskogen | 1e42436 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 90 | typedef ARCH_POSTFIX(V256_V256) ARCH_POSTFIX(V256_V256_Part2); |
| 91 | typedef ARCH_POSTFIX(V256_V256) ARCH_POSTFIX(V256_V256_Part3); |
| 92 | typedef ARCH_POSTFIX(V256_V256V256) ARCH_POSTFIX(V256_V256V256_Part2); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 93 | |
| 94 | // These functions are machine tuned located elsewhere |
| 95 | template <typename c_ret, typename c_arg> |
| 96 | void TestSimd1Arg(uint32_t iterations, uint32_t mask, uint32_t maskwidth, |
| 97 | const char *name); |
| 98 | |
| 99 | template <typename c_ret, typename c_arg1, typename c_arg2> |
| 100 | void TestSimd2Args(uint32_t iterations, uint32_t mask, uint32_t maskwidth, |
| 101 | const char *name); |
| 102 | |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 103 | const int kIterations = 65536; |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 104 | |
| 105 | // Add a macro layer since TEST_P will quote the name so we need to |
| 106 | // expand it first with the prefix. |
| 107 | #define MY_TEST_P(name, test) TEST_P(name, test) |
| 108 | |
Steinar Midtskogen | 6c79576 | 2017-03-07 20:55:48 +0100 | [diff] [blame] | 109 | MY_TEST_P(ARCH_POSTFIX(V64_U8), TestIntrinsics) { |
| 110 | TestSimd1Arg<c_v64, uint8_t>(kIterations, mask, maskwidth, name); |
| 111 | } |
| 112 | |
| 113 | MY_TEST_P(ARCH_POSTFIX(V64_U16), TestIntrinsics) { |
| 114 | TestSimd1Arg<c_v64, uint16_t>(kIterations, mask, maskwidth, name); |
| 115 | } |
| 116 | |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 117 | MY_TEST_P(ARCH_POSTFIX(V64_U32), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 118 | TestSimd1Arg<c_v64, uint32_t>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | MY_TEST_P(ARCH_POSTFIX(V64_V64), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 122 | TestSimd1Arg<c_v64, c_v64>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 123 | } |
| 124 | |
| 125 | MY_TEST_P(ARCH_POSTFIX(U64_V64), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 126 | TestSimd1Arg<uint64_t, c_v64>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 127 | } |
| 128 | |
Steinar Midtskogen | 6c79576 | 2017-03-07 20:55:48 +0100 | [diff] [blame] | 129 | MY_TEST_P(ARCH_POSTFIX(S64_V64), TestIntrinsics) { |
| 130 | TestSimd1Arg<int64_t, c_v64>(kIterations, mask, maskwidth, name); |
| 131 | } |
| 132 | |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 133 | MY_TEST_P(ARCH_POSTFIX(U32_V64), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 134 | TestSimd1Arg<uint32_t, c_v64>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 135 | } |
| 136 | |
Steinar Midtskogen | 6c79576 | 2017-03-07 20:55:48 +0100 | [diff] [blame] | 137 | MY_TEST_P(ARCH_POSTFIX(S32_V64), TestIntrinsics) { |
| 138 | TestSimd1Arg<int32_t, c_v64>(kIterations, mask, maskwidth, name); |
| 139 | } |
| 140 | |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 141 | MY_TEST_P(ARCH_POSTFIX(V64_U32U32), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 142 | TestSimd2Args<c_v64, uint32_t, uint32_t>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | MY_TEST_P(ARCH_POSTFIX(V64_V64V64), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 146 | TestSimd2Args<c_v64, c_v64, c_v64>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 147 | } |
| 148 | |
| 149 | MY_TEST_P(ARCH_POSTFIX(S64_V64V64), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 150 | TestSimd2Args<int64_t, c_v64, c_v64>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 151 | } |
| 152 | |
| 153 | MY_TEST_P(ARCH_POSTFIX(U32_V64V64), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 154 | TestSimd2Args<uint32_t, c_v64, c_v64>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | MY_TEST_P(ARCH_POSTFIX(V64_V64U32), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 158 | TestSimd2Args<c_v64, c_v64, uint32_t>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 159 | } |
| 160 | |
| 161 | // Google Test allows up to 50 tests per case, so split the largest |
| 162 | MY_TEST_P(ARCH_POSTFIX(V64_V64_Part2), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 163 | TestSimd1Arg<c_v64, c_v64>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 164 | } |
| 165 | |
| 166 | MY_TEST_P(ARCH_POSTFIX(V64_V64V64_Part2), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 167 | TestSimd2Args<c_v64, c_v64, c_v64>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 168 | } |
| 169 | |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 170 | MY_TEST_P(ARCH_POSTFIX(U32_V128), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 171 | TestSimd1Arg<uint32_t, c_v128>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | MY_TEST_P(ARCH_POSTFIX(U64_V128), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 175 | TestSimd1Arg<uint64_t, c_v128>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 176 | } |
| 177 | |
| 178 | MY_TEST_P(ARCH_POSTFIX(V64_V128), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 179 | TestSimd1Arg<c_v64, c_v128>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 180 | } |
| 181 | |
| 182 | MY_TEST_P(ARCH_POSTFIX(V128_V128), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 183 | TestSimd1Arg<c_v128, c_v128>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 184 | } |
| 185 | |
Steinar Midtskogen | 6c79576 | 2017-03-07 20:55:48 +0100 | [diff] [blame] | 186 | MY_TEST_P(ARCH_POSTFIX(V128_U8), TestIntrinsics) { |
| 187 | TestSimd1Arg<c_v128, uint8_t>(kIterations, mask, maskwidth, name); |
| 188 | } |
| 189 | |
| 190 | MY_TEST_P(ARCH_POSTFIX(V128_U16), TestIntrinsics) { |
| 191 | TestSimd1Arg<c_v128, uint16_t>(kIterations, mask, maskwidth, name); |
| 192 | } |
| 193 | |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 194 | MY_TEST_P(ARCH_POSTFIX(V128_U32), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 195 | TestSimd1Arg<c_v128, uint32_t>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 196 | } |
| 197 | |
| 198 | MY_TEST_P(ARCH_POSTFIX(V128_V64), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 199 | TestSimd1Arg<c_v128, c_v64>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 200 | } |
| 201 | |
| 202 | MY_TEST_P(ARCH_POSTFIX(V128_V128V128), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 203 | TestSimd2Args<c_v128, c_v128, c_v128>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 204 | } |
| 205 | |
| 206 | MY_TEST_P(ARCH_POSTFIX(U32_V128V128), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 207 | TestSimd2Args<uint32_t, c_v128, c_v128>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 208 | } |
| 209 | |
| 210 | MY_TEST_P(ARCH_POSTFIX(S64_V128V128), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 211 | TestSimd2Args<int64_t, c_v128, c_v128>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | MY_TEST_P(ARCH_POSTFIX(V128_U64U64), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 215 | TestSimd2Args<c_v128, uint64_t, uint64_t>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 216 | } |
| 217 | |
| 218 | MY_TEST_P(ARCH_POSTFIX(V128_V64V64), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 219 | TestSimd2Args<c_v128, c_v64, c_v64>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 220 | } |
| 221 | |
| 222 | MY_TEST_P(ARCH_POSTFIX(V128_V128U32), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 223 | TestSimd2Args<c_v128, c_v128, uint32_t>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 224 | } |
| 225 | |
| 226 | MY_TEST_P(ARCH_POSTFIX(V128_V128V128_Part2), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 227 | TestSimd2Args<c_v128, c_v128, c_v128>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 228 | } |
| 229 | |
| 230 | MY_TEST_P(ARCH_POSTFIX(V128_V128_Part2), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 231 | TestSimd1Arg<c_v128, c_v128>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 232 | } |
| 233 | |
| 234 | MY_TEST_P(ARCH_POSTFIX(V128_V128_Part3), TestIntrinsics) { |
Steinar Midtskogen | 9a9f41f | 2017-02-02 07:23:50 +0100 | [diff] [blame] | 235 | TestSimd1Arg<c_v128, c_v128>(kIterations, mask, maskwidth, name); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 236 | } |
| 237 | |
Steinar Midtskogen | 1e42436 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 238 | MY_TEST_P(ARCH_POSTFIX(U64_V256), TestIntrinsics) { |
| 239 | TestSimd1Arg<uint64_t, c_v256>(kIterations, mask, maskwidth, name); |
| 240 | } |
| 241 | |
| 242 | MY_TEST_P(ARCH_POSTFIX(V256_V256), TestIntrinsics) { |
| 243 | TestSimd1Arg<c_v256, c_v256>(kIterations, mask, maskwidth, name); |
| 244 | } |
| 245 | |
| 246 | MY_TEST_P(ARCH_POSTFIX(V256_V128), TestIntrinsics) { |
| 247 | TestSimd1Arg<c_v256, c_v128>(kIterations, mask, maskwidth, name); |
| 248 | } |
| 249 | |
| 250 | MY_TEST_P(ARCH_POSTFIX(V256_V256V256), TestIntrinsics) { |
| 251 | TestSimd2Args<c_v256, c_v256, c_v256>(kIterations, mask, maskwidth, name); |
| 252 | } |
| 253 | |
| 254 | MY_TEST_P(ARCH_POSTFIX(V256_V128V128), TestIntrinsics) { |
| 255 | TestSimd2Args<c_v256, c_v128, c_v128>(kIterations, mask, maskwidth, name); |
| 256 | } |
| 257 | |
| 258 | MY_TEST_P(ARCH_POSTFIX(U32_V256V256), TestIntrinsics) { |
| 259 | TestSimd2Args<uint32_t, c_v256, c_v256>(kIterations, mask, maskwidth, name); |
| 260 | } |
| 261 | |
| 262 | MY_TEST_P(ARCH_POSTFIX(S64_V256V256), TestIntrinsics) { |
| 263 | TestSimd2Args<int64_t, c_v256, c_v256>(kIterations, mask, maskwidth, name); |
| 264 | } |
| 265 | |
| 266 | MY_TEST_P(ARCH_POSTFIX(V256_V256V256_Part2), TestIntrinsics) { |
| 267 | TestSimd2Args<c_v256, c_v256, c_v256>(kIterations, mask, maskwidth, name); |
| 268 | } |
| 269 | |
| 270 | MY_TEST_P(ARCH_POSTFIX(V256_V256U32), TestIntrinsics) { |
| 271 | TestSimd2Args<c_v256, c_v256, uint32_t>(kIterations, mask, maskwidth, name); |
| 272 | } |
| 273 | |
| 274 | MY_TEST_P(ARCH_POSTFIX(V256_V256_Part2), TestIntrinsics) { |
| 275 | TestSimd1Arg<c_v256, c_v256>(kIterations, mask, maskwidth, name); |
| 276 | } |
| 277 | |
| 278 | MY_TEST_P(ARCH_POSTFIX(V256_V256_Part3), TestIntrinsics) { |
| 279 | TestSimd1Arg<c_v256, c_v256>(kIterations, mask, maskwidth, name); |
| 280 | } |
| 281 | |
| 282 | MY_TEST_P(ARCH_POSTFIX(V256_U8), TestIntrinsics) { |
| 283 | TestSimd1Arg<c_v256, uint8_t>(kIterations, mask, maskwidth, name); |
| 284 | } |
| 285 | |
| 286 | MY_TEST_P(ARCH_POSTFIX(V256_U16), TestIntrinsics) { |
| 287 | TestSimd1Arg<c_v256, uint16_t>(kIterations, mask, maskwidth, name); |
| 288 | } |
| 289 | |
| 290 | MY_TEST_P(ARCH_POSTFIX(V256_U32), TestIntrinsics) { |
| 291 | TestSimd1Arg<c_v256, uint32_t>(kIterations, mask, maskwidth, name); |
| 292 | } |
| 293 | |
| 294 | MY_TEST_P(ARCH_POSTFIX(U32_V256), TestIntrinsics) { |
| 295 | TestSimd1Arg<uint32_t, c_v256>(kIterations, mask, maskwidth, name); |
| 296 | } |
| 297 | |
| 298 | MY_TEST_P(ARCH_POSTFIX(V64_V256), TestIntrinsics) { |
| 299 | TestSimd1Arg<c_v64, c_v256>(kIterations, mask, maskwidth, name); |
| 300 | } |
| 301 | |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 302 | // Add a macro layer since INSTANTIATE_TEST_CASE_P will quote the name |
| 303 | // so we need to expand it first with the prefix |
| 304 | #define INSTANTIATE(name, type, ...) \ |
| 305 | INSTANTIATE_TEST_CASE_P(name, type, ::testing::Values(__VA_ARGS__)) |
| 306 | |
| 307 | #define SIMD_TUPLE(name, mask, maskwidth) \ |
James Zern | af18794 | 2017-01-31 18:46:35 -0800 | [diff] [blame] | 308 | std::tr1::make_tuple(mask, maskwidth, static_cast<const char *>(#name)) |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 309 | |
| 310 | INSTANTIATE(ARCH, ARCH_POSTFIX(U32_V64V64), |
| 311 | (SIMD_TUPLE(v64_sad_u8, 0U, 0U), SIMD_TUPLE(v64_ssd_u8, 0U, 0U))); |
| 312 | |
| 313 | INSTANTIATE( |
| 314 | ARCH, ARCH_POSTFIX(V64_V64V64), SIMD_TUPLE(v64_add_8, 0U, 0U), |
| 315 | SIMD_TUPLE(v64_add_16, 0U, 0U), SIMD_TUPLE(v64_sadd_s16, 0U, 0U), |
| 316 | SIMD_TUPLE(v64_add_32, 0U, 0U), SIMD_TUPLE(v64_sub_8, 0U, 0U), |
| 317 | SIMD_TUPLE(v64_ssub_u8, 0U, 0U), SIMD_TUPLE(v64_ssub_s8, 0U, 0U), |
| 318 | SIMD_TUPLE(v64_sub_16, 0U, 0U), SIMD_TUPLE(v64_ssub_s16, 0U, 0U), |
Steinar Midtskogen | 9b8444a | 2017-03-31 22:11:06 +0200 | [diff] [blame] | 319 | SIMD_TUPLE(v64_ssub_u16, 0U, 0U), SIMD_TUPLE(v64_sub_32, 0U, 0U), |
| 320 | SIMD_TUPLE(v64_ziplo_8, 0U, 0U), SIMD_TUPLE(v64_ziphi_8, 0U, 0U), |
| 321 | SIMD_TUPLE(v64_ziplo_16, 0U, 0U), SIMD_TUPLE(v64_ziphi_16, 0U, 0U), |
| 322 | SIMD_TUPLE(v64_ziplo_32, 0U, 0U), SIMD_TUPLE(v64_ziphi_32, 0U, 0U), |
| 323 | SIMD_TUPLE(v64_pack_s32_s16, 0U, 0U), SIMD_TUPLE(v64_pack_s16_u8, 0U, 0U), |
| 324 | SIMD_TUPLE(v64_pack_s16_s8, 0U, 0U), SIMD_TUPLE(v64_unziphi_8, 0U, 0U), |
| 325 | SIMD_TUPLE(v64_unziplo_8, 0U, 0U), SIMD_TUPLE(v64_unziphi_16, 0U, 0U), |
| 326 | SIMD_TUPLE(v64_unziplo_16, 0U, 0U), SIMD_TUPLE(v64_or, 0U, 0U), |
| 327 | SIMD_TUPLE(v64_xor, 0U, 0U), SIMD_TUPLE(v64_and, 0U, 0U), |
| 328 | SIMD_TUPLE(v64_andn, 0U, 0U), SIMD_TUPLE(v64_mullo_s16, 0U, 0U), |
| 329 | SIMD_TUPLE(v64_mulhi_s16, 0U, 0U), SIMD_TUPLE(v64_mullo_s32, 0U, 0U), |
| 330 | SIMD_TUPLE(v64_madd_s16, 0U, 0U), SIMD_TUPLE(v64_madd_us8, 0U, 0U), |
| 331 | SIMD_TUPLE(v64_avg_u8, 0U, 0U), SIMD_TUPLE(v64_rdavg_u8, 0U, 0U), |
| 332 | SIMD_TUPLE(v64_avg_u16, 0U, 0U), SIMD_TUPLE(v64_min_u8, 0U, 0U), |
| 333 | SIMD_TUPLE(v64_max_u8, 0U, 0U), SIMD_TUPLE(v64_min_s8, 0U, 0U), |
| 334 | SIMD_TUPLE(v64_max_s8, 0U, 0U), SIMD_TUPLE(v64_min_s16, 0U, 0U), |
| 335 | SIMD_TUPLE(v64_max_s16, 0U, 0U), SIMD_TUPLE(v64_cmpgt_s8, 0U, 0U), |
| 336 | SIMD_TUPLE(v64_cmplt_s8, 0U, 0U), SIMD_TUPLE(v64_cmpeq_8, 0U, 0U), |
| 337 | SIMD_TUPLE(v64_cmpgt_s16, 0U, 0U), SIMD_TUPLE(v64_cmplt_s16, 0U, 0U), |
| 338 | SIMD_TUPLE(v64_cmpeq_16, 0U, 0U)); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 339 | |
| 340 | INSTANTIATE( |
Steinar Midtskogen | 9b8444a | 2017-03-31 22:11:06 +0200 | [diff] [blame] | 341 | ARCH, ARCH_POSTFIX(V64_V64V64_Part2), SIMD_TUPLE(v64_shuffle_8, 7U, 8U), |
| 342 | SIMD_TUPLE(imm_v64_align<1>, 0U, 0U), SIMD_TUPLE(imm_v64_align<2>, 0U, 0U), |
| 343 | SIMD_TUPLE(imm_v64_align<3>, 0U, 0U), SIMD_TUPLE(imm_v64_align<4>, 0U, 0U), |
| 344 | SIMD_TUPLE(imm_v64_align<5>, 0U, 0U), SIMD_TUPLE(imm_v64_align<6>, 0U, 0U), |
| 345 | SIMD_TUPLE(imm_v64_align<7>, 0U, 0U)); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 346 | |
Steinar Midtskogen | 6033fb8 | 2017-04-02 21:32:41 +0200 | [diff] [blame] | 347 | INSTANTIATE(ARCH, ARCH_POSTFIX(V64_V64), SIMD_TUPLE(v64_abs_s8, 0U, 0U), |
| 348 | SIMD_TUPLE(v64_abs_s16, 0U, 0U), |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 349 | SIMD_TUPLE(v64_unpacklo_u8_s16, 0U, 0U), |
| 350 | SIMD_TUPLE(v64_unpackhi_u8_s16, 0U, 0U), |
Steinar Midtskogen | 1b2b739 | 2017-04-11 14:19:20 +0200 | [diff] [blame] | 351 | SIMD_TUPLE(v64_unpacklo_s8_s16, 0U, 0U), |
| 352 | SIMD_TUPLE(v64_unpackhi_s8_s16, 0U, 0U), |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 353 | SIMD_TUPLE(v64_unpacklo_u16_s32, 0U, 0U), |
| 354 | SIMD_TUPLE(v64_unpacklo_s16_s32, 0U, 0U), |
| 355 | SIMD_TUPLE(v64_unpackhi_u16_s32, 0U, 0U), |
| 356 | SIMD_TUPLE(v64_unpackhi_s16_s32, 0U, 0U), |
| 357 | SIMD_TUPLE(imm_v64_shr_n_byte<1>, 0U, 0U), |
| 358 | SIMD_TUPLE(imm_v64_shr_n_byte<2>, 0U, 0U), |
| 359 | SIMD_TUPLE(imm_v64_shr_n_byte<3>, 0U, 0U), |
| 360 | SIMD_TUPLE(imm_v64_shr_n_byte<4>, 0U, 0U), |
| 361 | SIMD_TUPLE(imm_v64_shr_n_byte<5>, 0U, 0U), |
| 362 | SIMD_TUPLE(imm_v64_shr_n_byte<6>, 0U, 0U), |
| 363 | SIMD_TUPLE(imm_v64_shr_n_byte<7>, 0U, 0U), |
| 364 | SIMD_TUPLE(imm_v64_shl_n_byte<1>, 0U, 0U), |
| 365 | SIMD_TUPLE(imm_v64_shl_n_byte<2>, 0U, 0U), |
| 366 | SIMD_TUPLE(imm_v64_shl_n_byte<3>, 0U, 0U), |
| 367 | SIMD_TUPLE(imm_v64_shl_n_byte<4>, 0U, 0U), |
| 368 | SIMD_TUPLE(imm_v64_shl_n_byte<5>, 0U, 0U), |
| 369 | SIMD_TUPLE(imm_v64_shl_n_byte<6>, 0U, 0U), |
| 370 | SIMD_TUPLE(imm_v64_shl_n_byte<7>, 0U, 0U), |
| 371 | SIMD_TUPLE(imm_v64_shl_n_8<1>, 0U, 0U), |
| 372 | SIMD_TUPLE(imm_v64_shl_n_8<2>, 0U, 0U), |
| 373 | SIMD_TUPLE(imm_v64_shl_n_8<3>, 0U, 0U), |
| 374 | SIMD_TUPLE(imm_v64_shl_n_8<4>, 0U, 0U), |
| 375 | SIMD_TUPLE(imm_v64_shl_n_8<5>, 0U, 0U), |
| 376 | SIMD_TUPLE(imm_v64_shl_n_8<6>, 0U, 0U), |
| 377 | SIMD_TUPLE(imm_v64_shl_n_8<7>, 0U, 0U), |
| 378 | SIMD_TUPLE(imm_v64_shr_n_u8<1>, 0U, 0U), |
| 379 | SIMD_TUPLE(imm_v64_shr_n_u8<2>, 0U, 0U), |
| 380 | SIMD_TUPLE(imm_v64_shr_n_u8<3>, 0U, 0U), |
| 381 | SIMD_TUPLE(imm_v64_shr_n_u8<4>, 0U, 0U), |
| 382 | SIMD_TUPLE(imm_v64_shr_n_u8<5>, 0U, 0U), |
| 383 | SIMD_TUPLE(imm_v64_shr_n_u8<6>, 0U, 0U), |
| 384 | SIMD_TUPLE(imm_v64_shr_n_u8<7>, 0U, 0U), |
| 385 | SIMD_TUPLE(imm_v64_shr_n_s8<1>, 0U, 0U), |
| 386 | SIMD_TUPLE(imm_v64_shr_n_s8<2>, 0U, 0U), |
| 387 | SIMD_TUPLE(imm_v64_shr_n_s8<3>, 0U, 0U), |
| 388 | SIMD_TUPLE(imm_v64_shr_n_s8<4>, 0U, 0U), |
| 389 | SIMD_TUPLE(imm_v64_shr_n_s8<5>, 0U, 0U), |
| 390 | SIMD_TUPLE(imm_v64_shr_n_s8<6>, 0U, 0U), |
| 391 | SIMD_TUPLE(imm_v64_shr_n_s8<7>, 0U, 0U), |
| 392 | SIMD_TUPLE(imm_v64_shl_n_16<1>, 0U, 0U), |
| 393 | SIMD_TUPLE(imm_v64_shl_n_16<2>, 0U, 0U), |
| 394 | SIMD_TUPLE(imm_v64_shl_n_16<4>, 0U, 0U), |
| 395 | SIMD_TUPLE(imm_v64_shl_n_16<6>, 0U, 0U), |
Steinar Midtskogen | 1b2b739 | 2017-04-11 14:19:20 +0200 | [diff] [blame] | 396 | SIMD_TUPLE(imm_v64_shl_n_16<8>, 0U, 0U)); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 397 | |
| 398 | INSTANTIATE(ARCH, ARCH_POSTFIX(V64_V64_Part2), |
Steinar Midtskogen | 1b2b739 | 2017-04-11 14:19:20 +0200 | [diff] [blame] | 399 | SIMD_TUPLE(imm_v64_shl_n_16<10>, 0U, 0U), |
| 400 | SIMD_TUPLE(imm_v64_shl_n_16<12>, 0U, 0U), |
Steinar Midtskogen | 6033fb8 | 2017-04-02 21:32:41 +0200 | [diff] [blame] | 401 | SIMD_TUPLE(imm_v64_shl_n_16<14>, 0U, 0U), |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 402 | SIMD_TUPLE(imm_v64_shr_n_u16<1>, 0U, 0U), |
| 403 | SIMD_TUPLE(imm_v64_shr_n_u16<2>, 0U, 0U), |
| 404 | SIMD_TUPLE(imm_v64_shr_n_u16<4>, 0U, 0U), |
| 405 | SIMD_TUPLE(imm_v64_shr_n_u16<6>, 0U, 0U), |
| 406 | SIMD_TUPLE(imm_v64_shr_n_u16<8>, 0U, 0U), |
| 407 | SIMD_TUPLE(imm_v64_shr_n_u16<10>, 0U, 0U), |
| 408 | SIMD_TUPLE(imm_v64_shr_n_u16<12>, 0U, 0U), |
| 409 | SIMD_TUPLE(imm_v64_shr_n_u16<14>, 0U, 0U), |
| 410 | SIMD_TUPLE(imm_v64_shr_n_s16<1>, 0U, 0U), |
| 411 | SIMD_TUPLE(imm_v64_shr_n_s16<2>, 0U, 0U), |
| 412 | SIMD_TUPLE(imm_v64_shr_n_s16<4>, 0U, 0U), |
| 413 | SIMD_TUPLE(imm_v64_shr_n_s16<6>, 0U, 0U), |
| 414 | SIMD_TUPLE(imm_v64_shr_n_s16<8>, 0U, 0U), |
| 415 | SIMD_TUPLE(imm_v64_shr_n_s16<10>, 0U, 0U), |
| 416 | SIMD_TUPLE(imm_v64_shr_n_s16<12>, 0U, 0U), |
| 417 | SIMD_TUPLE(imm_v64_shr_n_s16<14>, 0U, 0U), |
| 418 | SIMD_TUPLE(imm_v64_shl_n_32<1>, 0U, 0U), |
| 419 | SIMD_TUPLE(imm_v64_shl_n_32<4>, 0U, 0U), |
| 420 | SIMD_TUPLE(imm_v64_shl_n_32<8>, 0U, 0U), |
| 421 | SIMD_TUPLE(imm_v64_shl_n_32<12>, 0U, 0U), |
| 422 | SIMD_TUPLE(imm_v64_shl_n_32<16>, 0U, 0U), |
| 423 | SIMD_TUPLE(imm_v64_shl_n_32<20>, 0U, 0U), |
| 424 | SIMD_TUPLE(imm_v64_shl_n_32<24>, 0U, 0U), |
| 425 | SIMD_TUPLE(imm_v64_shl_n_32<28>, 0U, 0U), |
| 426 | SIMD_TUPLE(imm_v64_shr_n_u32<1>, 0U, 0U), |
| 427 | SIMD_TUPLE(imm_v64_shr_n_u32<4>, 0U, 0U), |
| 428 | SIMD_TUPLE(imm_v64_shr_n_u32<8>, 0U, 0U), |
| 429 | SIMD_TUPLE(imm_v64_shr_n_u32<12>, 0U, 0U), |
| 430 | SIMD_TUPLE(imm_v64_shr_n_u32<16>, 0U, 0U), |
| 431 | SIMD_TUPLE(imm_v64_shr_n_u32<20>, 0U, 0U), |
| 432 | SIMD_TUPLE(imm_v64_shr_n_u32<24>, 0U, 0U), |
| 433 | SIMD_TUPLE(imm_v64_shr_n_u32<28>, 0U, 0U), |
| 434 | SIMD_TUPLE(imm_v64_shr_n_s32<1>, 0U, 0U), |
| 435 | SIMD_TUPLE(imm_v64_shr_n_s32<4>, 0U, 0U), |
| 436 | SIMD_TUPLE(imm_v64_shr_n_s32<8>, 0U, 0U), |
| 437 | SIMD_TUPLE(imm_v64_shr_n_s32<12>, 0U, 0U), |
| 438 | SIMD_TUPLE(imm_v64_shr_n_s32<16>, 0U, 0U), |
| 439 | SIMD_TUPLE(imm_v64_shr_n_s32<20>, 0U, 0U), |
| 440 | SIMD_TUPLE(imm_v64_shr_n_s32<24>, 0U, 0U), |
| 441 | SIMD_TUPLE(imm_v64_shr_n_s32<28>, 0U, 0U)); |
| 442 | |
| 443 | INSTANTIATE(ARCH, ARCH_POSTFIX(V64_V64U32), SIMD_TUPLE(v64_shl_8, 7U, 32U), |
| 444 | SIMD_TUPLE(v64_shr_u8, 7U, 32U), SIMD_TUPLE(v64_shr_s8, 7U, 32U), |
| 445 | SIMD_TUPLE(v64_shl_16, 15U, 32U), SIMD_TUPLE(v64_shr_u16, 15U, 32U), |
| 446 | SIMD_TUPLE(v64_shr_s16, 15U, 32U), SIMD_TUPLE(v64_shl_32, 31U, 32U), |
| 447 | SIMD_TUPLE(v64_shr_u32, 31U, 32U), |
| 448 | SIMD_TUPLE(v64_shr_s32, 31U, 32U)); |
| 449 | |
Steinar Midtskogen | 6c79576 | 2017-03-07 20:55:48 +0100 | [diff] [blame] | 450 | INSTANTIATE(ARCH, ARCH_POSTFIX(U64_V64), SIMD_TUPLE(v64_hadd_u8, 0U, 0U), |
| 451 | SIMD_TUPLE(v64_u64, 0U, 0U)); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 452 | |
Steinar Midtskogen | 6c79576 | 2017-03-07 20:55:48 +0100 | [diff] [blame] | 453 | INSTANTIATE(ARCH, ARCH_POSTFIX(S64_V64), SIMD_TUPLE(v64_hadd_s16, 0U, 0U)); |
| 454 | |
| 455 | INSTANTIATE(ARCH, ARCH_POSTFIX(U32_V64), SIMD_TUPLE(v64_low_u32, 0U, 0U), |
| 456 | SIMD_TUPLE(v64_high_u32, 0U, 0U)); |
| 457 | |
| 458 | INSTANTIATE(ARCH, ARCH_POSTFIX(S32_V64), SIMD_TUPLE(v64_low_s32, 0U, 0U), |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 459 | SIMD_TUPLE(v64_high_s32, 0U, 0U)); |
| 460 | |
| 461 | INSTANTIATE(ARCH, ARCH_POSTFIX(S64_V64V64), SIMD_TUPLE(v64_dotp_s16, 0U, 0U), |
| 462 | SIMD_TUPLE(v64_dotp_su8, 0U, 0U)); |
| 463 | |
Steinar Midtskogen | 6c79576 | 2017-03-07 20:55:48 +0100 | [diff] [blame] | 464 | INSTANTIATE(ARCH, ARCH_POSTFIX(V64_U8), SIMD_TUPLE(v64_dup_8, 0U, 0U)); |
| 465 | |
| 466 | INSTANTIATE(ARCH, ARCH_POSTFIX(V64_U16), SIMD_TUPLE(v64_dup_16, 0U, 0U)); |
| 467 | |
| 468 | INSTANTIATE(ARCH, ARCH_POSTFIX(V64_U32), SIMD_TUPLE(v64_dup_32, 0U, 0U)); |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 469 | |
| 470 | INSTANTIATE(ARCH, ARCH_POSTFIX(V64_U32U32), SIMD_TUPLE(v64_from_32, 0U, 0U)); |
| 471 | |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 472 | INSTANTIATE(ARCH, ARCH_POSTFIX(U32_V128V128), SIMD_TUPLE(v128_sad_u8, 0U, 0U), |
| 473 | SIMD_TUPLE(v128_ssd_u8, 0U, 0U)); |
| 474 | |
| 475 | INSTANTIATE( |
| 476 | ARCH, ARCH_POSTFIX(V128_V128V128), SIMD_TUPLE(v128_add_8, 0U, 0U), |
| 477 | SIMD_TUPLE(v128_add_16, 0U, 0U), SIMD_TUPLE(v128_sadd_s16, 0U, 0U), |
| 478 | SIMD_TUPLE(v128_add_32, 0U, 0U), SIMD_TUPLE(v128_sub_8, 0U, 0U), |
| 479 | SIMD_TUPLE(v128_ssub_u8, 0U, 0U), SIMD_TUPLE(v128_ssub_s8, 0U, 0U), |
| 480 | SIMD_TUPLE(v128_sub_16, 0U, 0U), SIMD_TUPLE(v128_ssub_s16, 0U, 0U), |
Steinar Midtskogen | 9b8444a | 2017-03-31 22:11:06 +0200 | [diff] [blame] | 481 | SIMD_TUPLE(v128_ssub_u16, 0U, 0U), SIMD_TUPLE(v128_sub_32, 0U, 0U), |
| 482 | SIMD_TUPLE(v128_ziplo_8, 0U, 0U), SIMD_TUPLE(v128_ziphi_8, 0U, 0U), |
| 483 | SIMD_TUPLE(v128_ziplo_16, 0U, 0U), SIMD_TUPLE(v128_ziphi_16, 0U, 0U), |
| 484 | SIMD_TUPLE(v128_ziplo_32, 0U, 0U), SIMD_TUPLE(v128_ziphi_32, 0U, 0U), |
| 485 | SIMD_TUPLE(v128_ziplo_64, 0U, 0U), SIMD_TUPLE(v128_ziphi_64, 0U, 0U), |
| 486 | SIMD_TUPLE(v128_unziphi_8, 0U, 0U), SIMD_TUPLE(v128_unziplo_8, 0U, 0U), |
| 487 | SIMD_TUPLE(v128_unziphi_16, 0U, 0U), SIMD_TUPLE(v128_unziplo_16, 0U, 0U), |
| 488 | SIMD_TUPLE(v128_unziphi_32, 0U, 0U), SIMD_TUPLE(v128_unziplo_32, 0U, 0U), |
| 489 | SIMD_TUPLE(v128_pack_s32_s16, 0U, 0U), SIMD_TUPLE(v128_pack_s16_u8, 0U, 0U), |
| 490 | SIMD_TUPLE(v128_pack_s16_s8, 0U, 0U), SIMD_TUPLE(v128_or, 0U, 0U), |
| 491 | SIMD_TUPLE(v128_xor, 0U, 0U), SIMD_TUPLE(v128_and, 0U, 0U), |
| 492 | SIMD_TUPLE(v128_andn, 0U, 0U), SIMD_TUPLE(v128_mullo_s16, 0U, 0U), |
| 493 | SIMD_TUPLE(v128_mulhi_s16, 0U, 0U), SIMD_TUPLE(v128_mullo_s32, 0U, 0U), |
| 494 | SIMD_TUPLE(v128_madd_s16, 0U, 0U), SIMD_TUPLE(v128_madd_us8, 0U, 0U), |
| 495 | SIMD_TUPLE(v128_avg_u8, 0U, 0U), SIMD_TUPLE(v128_rdavg_u8, 0U, 0U), |
| 496 | SIMD_TUPLE(v128_avg_u16, 0U, 0U), SIMD_TUPLE(v128_min_u8, 0U, 0U), |
| 497 | SIMD_TUPLE(v128_max_u8, 0U, 0U), SIMD_TUPLE(v128_min_s8, 0U, 0U), |
| 498 | SIMD_TUPLE(v128_max_s8, 0U, 0U), SIMD_TUPLE(v128_min_s16, 0U, 0U), |
| 499 | SIMD_TUPLE(v128_max_s16, 0U, 0U), SIMD_TUPLE(v128_cmpgt_s8, 0U, 0U), |
| 500 | SIMD_TUPLE(v128_cmplt_s8, 0U, 0U), SIMD_TUPLE(v128_cmpeq_8, 0U, 0U), |
| 501 | SIMD_TUPLE(v128_cmpgt_s16, 0U, 0U)); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 502 | |
| 503 | INSTANTIATE(ARCH, ARCH_POSTFIX(V128_V128V128_Part2), |
Steinar Midtskogen | 9b8444a | 2017-03-31 22:11:06 +0200 | [diff] [blame] | 504 | SIMD_TUPLE(v128_cmpeq_16, 0U, 0U), |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 505 | SIMD_TUPLE(v128_cmplt_s16, 0U, 0U), |
| 506 | SIMD_TUPLE(v128_shuffle_8, 15U, 8U), |
| 507 | SIMD_TUPLE(imm_v128_align<1>, 0U, 0U), |
| 508 | SIMD_TUPLE(imm_v128_align<2>, 0U, 0U), |
| 509 | SIMD_TUPLE(imm_v128_align<3>, 0U, 0U), |
| 510 | SIMD_TUPLE(imm_v128_align<4>, 0U, 0U), |
| 511 | SIMD_TUPLE(imm_v128_align<5>, 0U, 0U), |
| 512 | SIMD_TUPLE(imm_v128_align<6>, 0U, 0U), |
| 513 | SIMD_TUPLE(imm_v128_align<7>, 0U, 0U), |
| 514 | SIMD_TUPLE(imm_v128_align<8>, 0U, 0U), |
| 515 | SIMD_TUPLE(imm_v128_align<9>, 0U, 0U), |
| 516 | SIMD_TUPLE(imm_v128_align<10>, 0U, 0U), |
| 517 | SIMD_TUPLE(imm_v128_align<11>, 0U, 0U), |
| 518 | SIMD_TUPLE(imm_v128_align<12>, 0U, 0U), |
| 519 | SIMD_TUPLE(imm_v128_align<13>, 0U, 0U), |
| 520 | SIMD_TUPLE(imm_v128_align<14>, 0U, 0U), |
| 521 | SIMD_TUPLE(imm_v128_align<15>, 0U, 0U)); |
| 522 | |
Steinar Midtskogen | 6033fb8 | 2017-04-02 21:32:41 +0200 | [diff] [blame] | 523 | INSTANTIATE(ARCH, ARCH_POSTFIX(V128_V128), SIMD_TUPLE(v128_abs_s8, 0U, 0U), |
| 524 | SIMD_TUPLE(v128_abs_s16, 0U, 0U), SIMD_TUPLE(v128_padd_s16, 0U, 0U), |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 525 | SIMD_TUPLE(v128_unpacklo_u8_s16, 0U, 0U), |
Steinar Midtskogen | 1b2b739 | 2017-04-11 14:19:20 +0200 | [diff] [blame] | 526 | SIMD_TUPLE(v128_unpacklo_s8_s16, 0U, 0U), |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 527 | SIMD_TUPLE(v128_unpacklo_u16_s32, 0U, 0U), |
| 528 | SIMD_TUPLE(v128_unpacklo_s16_s32, 0U, 0U), |
| 529 | SIMD_TUPLE(v128_unpackhi_u8_s16, 0U, 0U), |
Steinar Midtskogen | 1b2b739 | 2017-04-11 14:19:20 +0200 | [diff] [blame] | 530 | SIMD_TUPLE(v128_unpackhi_s8_s16, 0U, 0U), |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 531 | SIMD_TUPLE(v128_unpackhi_u16_s32, 0U, 0U), |
| 532 | SIMD_TUPLE(v128_unpackhi_s16_s32, 0U, 0U), |
| 533 | SIMD_TUPLE(imm_v128_shr_n_byte<1>, 0U, 0U), |
| 534 | SIMD_TUPLE(imm_v128_shr_n_byte<2>, 0U, 0U), |
| 535 | SIMD_TUPLE(imm_v128_shr_n_byte<3>, 0U, 0U), |
| 536 | SIMD_TUPLE(imm_v128_shr_n_byte<4>, 0U, 0U), |
| 537 | SIMD_TUPLE(imm_v128_shr_n_byte<5>, 0U, 0U), |
| 538 | SIMD_TUPLE(imm_v128_shr_n_byte<6>, 0U, 0U), |
| 539 | SIMD_TUPLE(imm_v128_shr_n_byte<7>, 0U, 0U), |
| 540 | SIMD_TUPLE(imm_v128_shr_n_byte<8>, 0U, 0U), |
| 541 | SIMD_TUPLE(imm_v128_shr_n_byte<9>, 0U, 0U), |
| 542 | SIMD_TUPLE(imm_v128_shr_n_byte<10>, 0U, 0U), |
| 543 | SIMD_TUPLE(imm_v128_shr_n_byte<11>, 0U, 0U), |
| 544 | SIMD_TUPLE(imm_v128_shr_n_byte<12>, 0U, 0U), |
| 545 | SIMD_TUPLE(imm_v128_shr_n_byte<13>, 0U, 0U), |
| 546 | SIMD_TUPLE(imm_v128_shr_n_byte<14>, 0U, 0U), |
| 547 | SIMD_TUPLE(imm_v128_shr_n_byte<15>, 0U, 0U), |
| 548 | SIMD_TUPLE(imm_v128_shl_n_byte<1>, 0U, 0U), |
| 549 | SIMD_TUPLE(imm_v128_shl_n_byte<2>, 0U, 0U), |
| 550 | SIMD_TUPLE(imm_v128_shl_n_byte<3>, 0U, 0U), |
| 551 | SIMD_TUPLE(imm_v128_shl_n_byte<4>, 0U, 0U), |
| 552 | SIMD_TUPLE(imm_v128_shl_n_byte<5>, 0U, 0U), |
| 553 | SIMD_TUPLE(imm_v128_shl_n_byte<6>, 0U, 0U), |
| 554 | SIMD_TUPLE(imm_v128_shl_n_byte<7>, 0U, 0U), |
| 555 | SIMD_TUPLE(imm_v128_shl_n_byte<8>, 0U, 0U), |
| 556 | SIMD_TUPLE(imm_v128_shl_n_byte<9>, 0U, 0U), |
| 557 | SIMD_TUPLE(imm_v128_shl_n_byte<10>, 0U, 0U), |
| 558 | SIMD_TUPLE(imm_v128_shl_n_byte<11>, 0U, 0U), |
| 559 | SIMD_TUPLE(imm_v128_shl_n_byte<12>, 0U, 0U), |
| 560 | SIMD_TUPLE(imm_v128_shl_n_byte<13>, 0U, 0U), |
| 561 | SIMD_TUPLE(imm_v128_shl_n_byte<14>, 0U, 0U), |
| 562 | SIMD_TUPLE(imm_v128_shl_n_byte<15>, 0U, 0U), |
| 563 | SIMD_TUPLE(imm_v128_shl_n_8<1>, 0U, 0U), |
| 564 | SIMD_TUPLE(imm_v128_shl_n_8<2>, 0U, 0U), |
| 565 | SIMD_TUPLE(imm_v128_shl_n_8<3>, 0U, 0U), |
| 566 | SIMD_TUPLE(imm_v128_shl_n_8<4>, 0U, 0U), |
| 567 | SIMD_TUPLE(imm_v128_shl_n_8<5>, 0U, 0U), |
| 568 | SIMD_TUPLE(imm_v128_shl_n_8<6>, 0U, 0U), |
| 569 | SIMD_TUPLE(imm_v128_shl_n_8<7>, 0U, 0U), |
Steinar Midtskogen | 1b2b739 | 2017-04-11 14:19:20 +0200 | [diff] [blame] | 570 | SIMD_TUPLE(imm_v128_shr_n_u8<1>, 0U, 0U)); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 571 | |
| 572 | INSTANTIATE(ARCH, ARCH_POSTFIX(V128_V128_Part2), |
Steinar Midtskogen | 1b2b739 | 2017-04-11 14:19:20 +0200 | [diff] [blame] | 573 | SIMD_TUPLE(imm_v128_shr_n_u8<2>, 0U, 0U), |
| 574 | SIMD_TUPLE(imm_v128_shr_n_u8<3>, 0U, 0U), |
Steinar Midtskogen | 6033fb8 | 2017-04-02 21:32:41 +0200 | [diff] [blame] | 575 | SIMD_TUPLE(imm_v128_shr_n_u8<4>, 0U, 0U), |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 576 | SIMD_TUPLE(imm_v128_shr_n_u8<5>, 0U, 0U), |
| 577 | SIMD_TUPLE(imm_v128_shr_n_u8<6>, 0U, 0U), |
| 578 | SIMD_TUPLE(imm_v128_shr_n_u8<7>, 0U, 0U), |
| 579 | SIMD_TUPLE(imm_v128_shr_n_s8<1>, 0U, 0U), |
| 580 | SIMD_TUPLE(imm_v128_shr_n_s8<2>, 0U, 0U), |
| 581 | SIMD_TUPLE(imm_v128_shr_n_s8<3>, 0U, 0U), |
| 582 | SIMD_TUPLE(imm_v128_shr_n_s8<4>, 0U, 0U), |
| 583 | SIMD_TUPLE(imm_v128_shr_n_s8<5>, 0U, 0U), |
| 584 | SIMD_TUPLE(imm_v128_shr_n_s8<6>, 0U, 0U), |
| 585 | SIMD_TUPLE(imm_v128_shr_n_s8<7>, 0U, 0U), |
| 586 | SIMD_TUPLE(imm_v128_shl_n_16<1>, 0U, 0U), |
| 587 | SIMD_TUPLE(imm_v128_shl_n_16<2>, 0U, 0U), |
| 588 | SIMD_TUPLE(imm_v128_shl_n_16<4>, 0U, 0U), |
| 589 | SIMD_TUPLE(imm_v128_shl_n_16<6>, 0U, 0U), |
| 590 | SIMD_TUPLE(imm_v128_shl_n_16<8>, 0U, 0U), |
| 591 | SIMD_TUPLE(imm_v128_shl_n_16<10>, 0U, 0U), |
| 592 | SIMD_TUPLE(imm_v128_shl_n_16<12>, 0U, 0U), |
| 593 | SIMD_TUPLE(imm_v128_shl_n_16<14>, 0U, 0U), |
| 594 | SIMD_TUPLE(imm_v128_shr_n_u16<1>, 0U, 0U), |
| 595 | SIMD_TUPLE(imm_v128_shr_n_u16<2>, 0U, 0U), |
| 596 | SIMD_TUPLE(imm_v128_shr_n_u16<4>, 0U, 0U), |
| 597 | SIMD_TUPLE(imm_v128_shr_n_u16<6>, 0U, 0U), |
| 598 | SIMD_TUPLE(imm_v128_shr_n_u16<8>, 0U, 0U), |
| 599 | SIMD_TUPLE(imm_v128_shr_n_u16<10>, 0U, 0U), |
| 600 | SIMD_TUPLE(imm_v128_shr_n_u16<12>, 0U, 0U), |
| 601 | SIMD_TUPLE(imm_v128_shr_n_u16<14>, 0U, 0U), |
| 602 | SIMD_TUPLE(imm_v128_shr_n_s16<1>, 0U, 0U), |
| 603 | SIMD_TUPLE(imm_v128_shr_n_s16<2>, 0U, 0U), |
| 604 | SIMD_TUPLE(imm_v128_shr_n_s16<4>, 0U, 0U), |
| 605 | SIMD_TUPLE(imm_v128_shr_n_s16<6>, 0U, 0U), |
| 606 | SIMD_TUPLE(imm_v128_shr_n_s16<8>, 0U, 0U), |
| 607 | SIMD_TUPLE(imm_v128_shr_n_s16<10>, 0U, 0U), |
| 608 | SIMD_TUPLE(imm_v128_shr_n_s16<12>, 0U, 0U), |
| 609 | SIMD_TUPLE(imm_v128_shr_n_s16<14>, 0U, 0U), |
| 610 | SIMD_TUPLE(imm_v128_shl_n_32<1>, 0U, 0U), |
| 611 | SIMD_TUPLE(imm_v128_shl_n_32<4>, 0U, 0U), |
| 612 | SIMD_TUPLE(imm_v128_shl_n_32<8>, 0U, 0U), |
| 613 | SIMD_TUPLE(imm_v128_shl_n_32<12>, 0U, 0U), |
| 614 | SIMD_TUPLE(imm_v128_shl_n_32<16>, 0U, 0U), |
| 615 | SIMD_TUPLE(imm_v128_shl_n_32<20>, 0U, 0U), |
| 616 | SIMD_TUPLE(imm_v128_shl_n_32<24>, 0U, 0U), |
| 617 | SIMD_TUPLE(imm_v128_shl_n_32<28>, 0U, 0U), |
| 618 | SIMD_TUPLE(imm_v128_shr_n_u32<1>, 0U, 0U), |
Steinar Midtskogen | 1b2b739 | 2017-04-11 14:19:20 +0200 | [diff] [blame] | 619 | SIMD_TUPLE(imm_v128_shr_n_u32<4>, 0U, 0U)); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 620 | |
| 621 | INSTANTIATE(ARCH, ARCH_POSTFIX(V128_V128_Part3), |
Steinar Midtskogen | 1b2b739 | 2017-04-11 14:19:20 +0200 | [diff] [blame] | 622 | SIMD_TUPLE(imm_v128_shr_n_u32<8>, 0U, 0U), |
| 623 | SIMD_TUPLE(imm_v128_shr_n_u32<12>, 0U, 0U), |
Steinar Midtskogen | 6033fb8 | 2017-04-02 21:32:41 +0200 | [diff] [blame] | 624 | SIMD_TUPLE(imm_v128_shr_n_u32<16>, 0U, 0U), |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 625 | SIMD_TUPLE(imm_v128_shr_n_u32<20>, 0U, 0U), |
| 626 | SIMD_TUPLE(imm_v128_shr_n_u32<24>, 0U, 0U), |
| 627 | SIMD_TUPLE(imm_v128_shr_n_u32<28>, 0U, 0U), |
| 628 | SIMD_TUPLE(imm_v128_shr_n_s32<1>, 0U, 0U), |
| 629 | SIMD_TUPLE(imm_v128_shr_n_s32<4>, 0U, 0U), |
| 630 | SIMD_TUPLE(imm_v128_shr_n_s32<8>, 0U, 0U), |
| 631 | SIMD_TUPLE(imm_v128_shr_n_s32<12>, 0U, 0U), |
| 632 | SIMD_TUPLE(imm_v128_shr_n_s32<16>, 0U, 0U), |
| 633 | SIMD_TUPLE(imm_v128_shr_n_s32<20>, 0U, 0U), |
| 634 | SIMD_TUPLE(imm_v128_shr_n_s32<24>, 0U, 0U), |
| 635 | SIMD_TUPLE(imm_v128_shr_n_s32<28>, 0U, 0U)); |
| 636 | |
| 637 | INSTANTIATE(ARCH, ARCH_POSTFIX(V128_V64V64), SIMD_TUPLE(v128_from_v64, 0U, 0U), |
| 638 | SIMD_TUPLE(v128_zip_8, 0U, 0U), SIMD_TUPLE(v128_zip_16, 0U, 0U), |
| 639 | SIMD_TUPLE(v128_zip_32, 0U, 0U), SIMD_TUPLE(v128_mul_s16, 0U, 0U)); |
| 640 | |
| 641 | INSTANTIATE(ARCH, ARCH_POSTFIX(V128_U64U64), SIMD_TUPLE(v128_from_64, 0U, 0U)); |
| 642 | |
| 643 | INSTANTIATE(ARCH, ARCH_POSTFIX(V128_V64), |
| 644 | SIMD_TUPLE(v128_unpack_u8_s16, 0U, 0U), |
Steinar Midtskogen | 1b2b739 | 2017-04-11 14:19:20 +0200 | [diff] [blame] | 645 | SIMD_TUPLE(v128_unpack_s8_s16, 0U, 0U), |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 646 | SIMD_TUPLE(v128_unpack_u16_s32, 0U, 0U), |
| 647 | SIMD_TUPLE(v128_unpack_s16_s32, 0U, 0U)); |
| 648 | |
| 649 | INSTANTIATE(ARCH, ARCH_POSTFIX(V128_V128U32), SIMD_TUPLE(v128_shl_8, 7U, 32U), |
| 650 | SIMD_TUPLE(v128_shr_u8, 7U, 32U), SIMD_TUPLE(v128_shr_s8, 7U, 32U), |
| 651 | SIMD_TUPLE(v128_shl_16, 15U, 32U), |
| 652 | SIMD_TUPLE(v128_shr_u16, 15U, 32U), |
| 653 | SIMD_TUPLE(v128_shr_s16, 15U, 32U), |
| 654 | SIMD_TUPLE(v128_shl_32, 31U, 32U), |
| 655 | SIMD_TUPLE(v128_shr_u32, 31U, 32U), |
| 656 | SIMD_TUPLE(v128_shr_s32, 31U, 32U)); |
| 657 | |
| 658 | INSTANTIATE(ARCH, ARCH_POSTFIX(U32_V128), SIMD_TUPLE(v128_low_u32, 0U, 0U)); |
| 659 | |
| 660 | INSTANTIATE(ARCH, ARCH_POSTFIX(U64_V128), SIMD_TUPLE(v128_hadd_u8, 0U, 0U)); |
| 661 | |
| 662 | INSTANTIATE(ARCH, ARCH_POSTFIX(V64_V128), SIMD_TUPLE(v128_low_v64, 0U, 0U), |
| 663 | SIMD_TUPLE(v128_high_v64, 0U, 0U)); |
| 664 | |
Steinar Midtskogen | 6c79576 | 2017-03-07 20:55:48 +0100 | [diff] [blame] | 665 | INSTANTIATE(ARCH, ARCH_POSTFIX(V128_U8), SIMD_TUPLE(v128_dup_8, 0U, 0U)); |
| 666 | |
| 667 | INSTANTIATE(ARCH, ARCH_POSTFIX(V128_U16), SIMD_TUPLE(v128_dup_16, 0U, 0U)); |
| 668 | |
| 669 | INSTANTIATE(ARCH, ARCH_POSTFIX(V128_U32), SIMD_TUPLE(v128_dup_32, 0U, 0U)); |
Steinar Midtskogen | 82d580c | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 670 | |
| 671 | INSTANTIATE(ARCH, ARCH_POSTFIX(S64_V128V128), |
| 672 | SIMD_TUPLE(v128_dotp_s16, 0U, 0U)); |
| 673 | |
Steinar Midtskogen | 1e42436 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 674 | INSTANTIATE(ARCH, ARCH_POSTFIX(U32_V256V256), SIMD_TUPLE(v256_sad_u8, 0U, 0U), |
| 675 | SIMD_TUPLE(v256_ssd_u8, 0U, 0U)); |
| 676 | |
| 677 | INSTANTIATE(ARCH, ARCH_POSTFIX(U64_V256), SIMD_TUPLE(v256_hadd_u8, 0U, 0U)); |
| 678 | |
| 679 | INSTANTIATE(ARCH, ARCH_POSTFIX(S64_V256V256), |
| 680 | SIMD_TUPLE(v256_dotp_s16, 0U, 0U)); |
| 681 | |
| 682 | INSTANTIATE( |
| 683 | ARCH, ARCH_POSTFIX(V256_V256V256), SIMD_TUPLE(v256_add_8, 0U, 0U), |
| 684 | SIMD_TUPLE(v256_add_16, 0U, 0U), SIMD_TUPLE(v256_sadd_s16, 0U, 0U), |
| 685 | SIMD_TUPLE(v256_add_32, 0U, 0U), SIMD_TUPLE(v256_sub_8, 0U, 0U), |
| 686 | SIMD_TUPLE(v256_ssub_u8, 0U, 0U), SIMD_TUPLE(v256_ssub_s8, 0U, 0U), |
| 687 | SIMD_TUPLE(v256_sub_16, 0U, 0U), SIMD_TUPLE(v256_ssub_s16, 0U, 0U), |
| 688 | SIMD_TUPLE(v256_ssub_u16, 0U, 0U), SIMD_TUPLE(v256_sub_32, 0U, 0U), |
| 689 | SIMD_TUPLE(v256_ziplo_8, 0U, 0U), SIMD_TUPLE(v256_ziphi_8, 0U, 0U), |
| 690 | SIMD_TUPLE(v256_ziplo_16, 0U, 0U), SIMD_TUPLE(v256_ziphi_16, 0U, 0U), |
| 691 | SIMD_TUPLE(v256_ziplo_32, 0U, 0U), SIMD_TUPLE(v256_ziphi_32, 0U, 0U), |
| 692 | SIMD_TUPLE(v256_ziplo_64, 0U, 0U), SIMD_TUPLE(v256_ziphi_64, 0U, 0U), |
| 693 | SIMD_TUPLE(v256_ziplo_128, 0U, 0U), SIMD_TUPLE(v256_ziphi_128, 0U, 0U), |
| 694 | SIMD_TUPLE(v256_unziphi_8, 0U, 0U), SIMD_TUPLE(v256_unziplo_8, 0U, 0U), |
| 695 | SIMD_TUPLE(v256_unziphi_16, 0U, 0U), SIMD_TUPLE(v256_unziplo_16, 0U, 0U), |
| 696 | SIMD_TUPLE(v256_unziphi_32, 0U, 0U), SIMD_TUPLE(v256_unziplo_32, 0U, 0U), |
| 697 | SIMD_TUPLE(v256_pack_s32_s16, 0U, 0U), SIMD_TUPLE(v256_pack_s16_u8, 0U, 0U), |
| 698 | SIMD_TUPLE(v256_pack_s16_s8, 0U, 0U), SIMD_TUPLE(v256_or, 0U, 0U), |
| 699 | SIMD_TUPLE(v256_xor, 0U, 0U), SIMD_TUPLE(v256_and, 0U, 0U), |
| 700 | SIMD_TUPLE(v256_andn, 0U, 0U), SIMD_TUPLE(v256_mullo_s16, 0U, 0U), |
| 701 | SIMD_TUPLE(v256_mulhi_s16, 0U, 0U), SIMD_TUPLE(v256_mullo_s32, 0U, 0U), |
| 702 | SIMD_TUPLE(v256_madd_s16, 0U, 0U), SIMD_TUPLE(v256_madd_us8, 0U, 0U), |
| 703 | SIMD_TUPLE(v256_avg_u8, 0U, 0U), SIMD_TUPLE(v256_rdavg_u8, 0U, 0U), |
| 704 | SIMD_TUPLE(v256_avg_u16, 0U, 0U), SIMD_TUPLE(v256_min_u8, 0U, 0U), |
| 705 | SIMD_TUPLE(v256_max_u8, 0U, 0U), SIMD_TUPLE(v256_min_s8, 0U, 0U), |
| 706 | SIMD_TUPLE(v256_max_s8, 0U, 0U), SIMD_TUPLE(v256_min_s16, 0U, 0U), |
| 707 | SIMD_TUPLE(v256_max_s16, 0U, 0U), SIMD_TUPLE(v256_cmpgt_s8, 0U, 0U), |
| 708 | SIMD_TUPLE(v256_cmplt_s8, 0U, 0U)); |
| 709 | |
| 710 | INSTANTIATE( |
| 711 | ARCH, ARCH_POSTFIX(V256_V256V256_Part2), SIMD_TUPLE(v256_cmpeq_8, 0U, 0U), |
| 712 | SIMD_TUPLE(v256_cmpgt_s16, 0U, 0U), SIMD_TUPLE(v256_cmplt_s16, 0U, 0U), |
| 713 | SIMD_TUPLE(v256_cmpeq_16, 0U, 0U), SIMD_TUPLE(v256_shuffle_8, 15U, 8U), |
| 714 | SIMD_TUPLE(v256_pshuffle_8, 15U, 8U), SIMD_TUPLE(imm_v256_align<1>, 0U, 0U), |
| 715 | SIMD_TUPLE(imm_v256_align<2>, 0U, 0U), |
| 716 | SIMD_TUPLE(imm_v256_align<3>, 0U, 0U), |
| 717 | SIMD_TUPLE(imm_v256_align<4>, 0U, 0U), |
| 718 | SIMD_TUPLE(imm_v256_align<5>, 0U, 0U), |
| 719 | SIMD_TUPLE(imm_v256_align<6>, 0U, 0U), |
| 720 | SIMD_TUPLE(imm_v256_align<7>, 0U, 0U), |
| 721 | SIMD_TUPLE(imm_v256_align<8>, 0U, 0U), |
| 722 | SIMD_TUPLE(imm_v256_align<9>, 0U, 0U), |
| 723 | SIMD_TUPLE(imm_v256_align<10>, 0U, 0U), |
| 724 | SIMD_TUPLE(imm_v256_align<11>, 0U, 0U), |
| 725 | SIMD_TUPLE(imm_v256_align<12>, 0U, 0U), |
| 726 | SIMD_TUPLE(imm_v256_align<13>, 0U, 0U), |
| 727 | SIMD_TUPLE(imm_v256_align<14>, 0U, 0U), |
| 728 | SIMD_TUPLE(imm_v256_align<15>, 0U, 0U), |
| 729 | SIMD_TUPLE(imm_v256_align<16>, 0U, 0U), |
| 730 | SIMD_TUPLE(imm_v256_align<17>, 0U, 0U), |
| 731 | SIMD_TUPLE(imm_v256_align<18>, 0U, 0U), |
| 732 | SIMD_TUPLE(imm_v256_align<19>, 0U, 0U), |
| 733 | SIMD_TUPLE(imm_v256_align<20>, 0U, 0U), |
| 734 | SIMD_TUPLE(imm_v256_align<21>, 0U, 0U), |
| 735 | SIMD_TUPLE(imm_v256_align<22>, 0U, 0U), |
| 736 | SIMD_TUPLE(imm_v256_align<23>, 0U, 0U), |
| 737 | SIMD_TUPLE(imm_v256_align<24>, 0U, 0U), |
| 738 | SIMD_TUPLE(imm_v256_align<25>, 0U, 0U), |
| 739 | SIMD_TUPLE(imm_v256_align<26>, 0U, 0U), |
| 740 | SIMD_TUPLE(imm_v256_align<27>, 0U, 0U), |
| 741 | SIMD_TUPLE(imm_v256_align<28>, 0U, 0U), |
| 742 | SIMD_TUPLE(imm_v256_align<29>, 0U, 0U), |
| 743 | SIMD_TUPLE(imm_v256_align<30>, 0U, 0U), |
| 744 | SIMD_TUPLE(imm_v256_align<31>, 0U, 0U)); |
| 745 | |
| 746 | INSTANTIATE(ARCH, ARCH_POSTFIX(V256_V128V128), |
| 747 | SIMD_TUPLE(v256_from_v128, 0U, 0U), SIMD_TUPLE(v256_zip_8, 0U, 0U), |
| 748 | SIMD_TUPLE(v256_zip_16, 0U, 0U), SIMD_TUPLE(v256_zip_32, 0U, 0U), |
| 749 | SIMD_TUPLE(v256_mul_s16, 0U, 0U)); |
| 750 | |
| 751 | INSTANTIATE(ARCH, ARCH_POSTFIX(V256_V128), |
| 752 | SIMD_TUPLE(v256_unpack_u8_s16, 0U, 0U), |
| 753 | SIMD_TUPLE(v256_unpack_s8_s16, 0U, 0U), |
| 754 | SIMD_TUPLE(v256_unpack_u16_s32, 0U, 0U), |
| 755 | SIMD_TUPLE(v256_unpack_s16_s32, 0U, 0U)); |
| 756 | |
| 757 | INSTANTIATE(ARCH, ARCH_POSTFIX(V256_V256U32), SIMD_TUPLE(v256_shl_8, 7U, 32U), |
| 758 | SIMD_TUPLE(v256_shr_u8, 7U, 32U), SIMD_TUPLE(v256_shr_s8, 7U, 32U), |
| 759 | SIMD_TUPLE(v256_shl_16, 15U, 32U), |
| 760 | SIMD_TUPLE(v256_shr_u16, 15U, 32U), |
| 761 | SIMD_TUPLE(v256_shr_s16, 15U, 32U), |
| 762 | SIMD_TUPLE(v256_shl_32, 31U, 32U), |
| 763 | SIMD_TUPLE(v256_shr_u32, 31U, 32U), |
| 764 | SIMD_TUPLE(v256_shr_s32, 31U, 32U)); |
| 765 | |
| 766 | INSTANTIATE(ARCH, ARCH_POSTFIX(V256_V256), SIMD_TUPLE(v256_abs_s8, 0U, 0U), |
| 767 | SIMD_TUPLE(v256_abs_s16, 0U, 0U), SIMD_TUPLE(v256_padd_s16, 0U, 0U), |
| 768 | SIMD_TUPLE(v256_unpacklo_u8_s16, 0U, 0U), |
| 769 | SIMD_TUPLE(v256_unpacklo_s8_s16, 0U, 0U), |
| 770 | SIMD_TUPLE(v256_unpacklo_u16_s32, 0U, 0U), |
| 771 | SIMD_TUPLE(v256_unpacklo_s16_s32, 0U, 0U), |
| 772 | SIMD_TUPLE(v256_unpackhi_u8_s16, 0U, 0U), |
| 773 | SIMD_TUPLE(v256_unpackhi_s8_s16, 0U, 0U), |
| 774 | SIMD_TUPLE(v256_unpackhi_u16_s32, 0U, 0U), |
| 775 | SIMD_TUPLE(v256_unpackhi_s16_s32, 0U, 0U), |
| 776 | SIMD_TUPLE(imm_v256_shr_n_byte<1>, 0U, 0U), |
| 777 | SIMD_TUPLE(imm_v256_shr_n_byte<2>, 0U, 0U), |
| 778 | SIMD_TUPLE(imm_v256_shr_n_byte<3>, 0U, 0U), |
| 779 | SIMD_TUPLE(imm_v256_shr_n_byte<4>, 0U, 0U), |
| 780 | SIMD_TUPLE(imm_v256_shr_n_byte<5>, 0U, 0U), |
| 781 | SIMD_TUPLE(imm_v256_shr_n_byte<6>, 0U, 0U), |
| 782 | SIMD_TUPLE(imm_v256_shr_n_byte<7>, 0U, 0U), |
| 783 | SIMD_TUPLE(imm_v256_shr_n_byte<8>, 0U, 0U), |
| 784 | SIMD_TUPLE(imm_v256_shr_n_byte<9>, 0U, 0U), |
| 785 | SIMD_TUPLE(imm_v256_shr_n_byte<10>, 0U, 0U), |
| 786 | SIMD_TUPLE(imm_v256_shr_n_byte<11>, 0U, 0U), |
| 787 | SIMD_TUPLE(imm_v256_shr_n_byte<12>, 0U, 0U), |
| 788 | SIMD_TUPLE(imm_v256_shr_n_byte<13>, 0U, 0U), |
| 789 | SIMD_TUPLE(imm_v256_shr_n_byte<14>, 0U, 0U), |
| 790 | SIMD_TUPLE(imm_v256_shr_n_byte<15>, 0U, 0U), |
| 791 | SIMD_TUPLE(imm_v256_shr_n_byte<16>, 0U, 0U), |
| 792 | SIMD_TUPLE(imm_v256_shr_n_byte<17>, 0U, 0U), |
| 793 | SIMD_TUPLE(imm_v256_shr_n_byte<18>, 0U, 0U), |
| 794 | SIMD_TUPLE(imm_v256_shr_n_byte<19>, 0U, 0U), |
| 795 | SIMD_TUPLE(imm_v256_shr_n_byte<20>, 0U, 0U), |
| 796 | SIMD_TUPLE(imm_v256_shr_n_byte<21>, 0U, 0U), |
| 797 | SIMD_TUPLE(imm_v256_shr_n_byte<22>, 0U, 0U), |
| 798 | SIMD_TUPLE(imm_v256_shr_n_byte<23>, 0U, 0U), |
| 799 | SIMD_TUPLE(imm_v256_shr_n_byte<24>, 0U, 0U), |
| 800 | SIMD_TUPLE(imm_v256_shr_n_byte<25>, 0U, 0U), |
| 801 | SIMD_TUPLE(imm_v256_shr_n_byte<26>, 0U, 0U), |
| 802 | SIMD_TUPLE(imm_v256_shr_n_byte<27>, 0U, 0U), |
| 803 | SIMD_TUPLE(imm_v256_shr_n_byte<28>, 0U, 0U), |
| 804 | SIMD_TUPLE(imm_v256_shr_n_byte<29>, 0U, 0U), |
| 805 | SIMD_TUPLE(imm_v256_shr_n_byte<30>, 0U, 0U), |
| 806 | SIMD_TUPLE(imm_v256_shr_n_byte<31>, 0U, 0U), |
| 807 | SIMD_TUPLE(imm_v256_shl_n_byte<1>, 0U, 0U), |
| 808 | SIMD_TUPLE(imm_v256_shl_n_byte<2>, 0U, 0U), |
| 809 | SIMD_TUPLE(imm_v256_shl_n_byte<3>, 0U, 0U), |
| 810 | SIMD_TUPLE(imm_v256_shl_n_byte<4>, 0U, 0U), |
| 811 | SIMD_TUPLE(imm_v256_shl_n_byte<5>, 0U, 0U), |
| 812 | SIMD_TUPLE(imm_v256_shl_n_byte<6>, 0U, 0U), |
| 813 | SIMD_TUPLE(imm_v256_shl_n_byte<7>, 0U, 0U), |
| 814 | SIMD_TUPLE(imm_v256_shl_n_byte<8>, 0U, 0U)); |
| 815 | |
| 816 | INSTANTIATE(ARCH, ARCH_POSTFIX(V256_V256_Part2), |
| 817 | SIMD_TUPLE(imm_v256_shl_n_byte<9>, 0U, 0U), |
| 818 | SIMD_TUPLE(imm_v256_shl_n_byte<10>, 0U, 0U), |
| 819 | SIMD_TUPLE(imm_v256_shl_n_byte<11>, 0U, 0U), |
| 820 | SIMD_TUPLE(imm_v256_shl_n_byte<12>, 0U, 0U), |
| 821 | SIMD_TUPLE(imm_v256_shl_n_byte<13>, 0U, 0U), |
| 822 | SIMD_TUPLE(imm_v256_shl_n_byte<14>, 0U, 0U), |
| 823 | SIMD_TUPLE(imm_v256_shl_n_byte<15>, 0U, 0U), |
| 824 | SIMD_TUPLE(imm_v256_shl_n_byte<16>, 0U, 0U), |
| 825 | SIMD_TUPLE(imm_v256_shl_n_byte<17>, 0U, 0U), |
| 826 | SIMD_TUPLE(imm_v256_shl_n_byte<18>, 0U, 0U), |
| 827 | SIMD_TUPLE(imm_v256_shl_n_byte<19>, 0U, 0U), |
| 828 | SIMD_TUPLE(imm_v256_shl_n_byte<20>, 0U, 0U), |
| 829 | SIMD_TUPLE(imm_v256_shl_n_byte<21>, 0U, 0U), |
| 830 | SIMD_TUPLE(imm_v256_shl_n_byte<22>, 0U, 0U), |
| 831 | SIMD_TUPLE(imm_v256_shl_n_byte<23>, 0U, 0U), |
| 832 | SIMD_TUPLE(imm_v256_shl_n_byte<24>, 0U, 0U), |
| 833 | SIMD_TUPLE(imm_v256_shl_n_byte<25>, 0U, 0U), |
| 834 | SIMD_TUPLE(imm_v256_shl_n_byte<26>, 0U, 0U), |
| 835 | SIMD_TUPLE(imm_v256_shl_n_byte<27>, 0U, 0U), |
| 836 | SIMD_TUPLE(imm_v256_shl_n_byte<28>, 0U, 0U), |
| 837 | SIMD_TUPLE(imm_v256_shl_n_byte<29>, 0U, 0U), |
| 838 | SIMD_TUPLE(imm_v256_shl_n_byte<30>, 0U, 0U), |
| 839 | SIMD_TUPLE(imm_v256_shl_n_byte<31>, 0U, 0U), |
| 840 | SIMD_TUPLE(imm_v256_shl_n_8<1>, 0U, 0U), |
| 841 | SIMD_TUPLE(imm_v256_shl_n_8<2>, 0U, 0U), |
| 842 | SIMD_TUPLE(imm_v256_shl_n_8<3>, 0U, 0U), |
| 843 | SIMD_TUPLE(imm_v256_shl_n_8<4>, 0U, 0U), |
| 844 | SIMD_TUPLE(imm_v256_shl_n_8<5>, 0U, 0U), |
| 845 | SIMD_TUPLE(imm_v256_shl_n_8<6>, 0U, 0U), |
| 846 | SIMD_TUPLE(imm_v256_shl_n_8<7>, 0U, 0U), |
| 847 | SIMD_TUPLE(imm_v256_shr_n_u8<1>, 0U, 0U), |
| 848 | SIMD_TUPLE(imm_v256_shr_n_u8<2>, 0U, 0U), |
| 849 | SIMD_TUPLE(imm_v256_shr_n_u8<3>, 0U, 0U), |
| 850 | SIMD_TUPLE(imm_v256_shr_n_u8<4>, 0U, 0U), |
| 851 | SIMD_TUPLE(imm_v256_shr_n_u8<5>, 0U, 0U), |
| 852 | SIMD_TUPLE(imm_v256_shr_n_u8<6>, 0U, 0U), |
| 853 | SIMD_TUPLE(imm_v256_shr_n_u8<7>, 0U, 0U), |
| 854 | SIMD_TUPLE(imm_v256_shr_n_s8<1>, 0U, 0U), |
| 855 | SIMD_TUPLE(imm_v256_shr_n_s8<2>, 0U, 0U), |
| 856 | SIMD_TUPLE(imm_v256_shr_n_s8<3>, 0U, 0U), |
| 857 | SIMD_TUPLE(imm_v256_shr_n_s8<4>, 0U, 0U), |
| 858 | SIMD_TUPLE(imm_v256_shr_n_s8<5>, 0U, 0U), |
| 859 | SIMD_TUPLE(imm_v256_shr_n_s8<6>, 0U, 0U), |
| 860 | SIMD_TUPLE(imm_v256_shr_n_s8<7>, 0U, 0U), |
| 861 | SIMD_TUPLE(imm_v256_shl_n_16<1>, 0U, 0U), |
| 862 | SIMD_TUPLE(imm_v256_shl_n_16<2>, 0U, 0U), |
| 863 | SIMD_TUPLE(imm_v256_shl_n_16<4>, 0U, 0U), |
| 864 | SIMD_TUPLE(imm_v256_shl_n_16<6>, 0U, 0U), |
| 865 | SIMD_TUPLE(imm_v256_shl_n_16<8>, 0U, 0U), |
| 866 | SIMD_TUPLE(imm_v256_shl_n_16<10>, 0U, 0U)); |
| 867 | |
| 868 | INSTANTIATE(ARCH, ARCH_POSTFIX(V256_V256_Part3), |
| 869 | SIMD_TUPLE(imm_v256_shl_n_16<12>, 0U, 0U), |
| 870 | SIMD_TUPLE(imm_v256_shl_n_16<14>, 0U, 0U), |
| 871 | SIMD_TUPLE(imm_v256_shr_n_u16<1>, 0U, 0U), |
| 872 | SIMD_TUPLE(imm_v256_shr_n_u16<2>, 0U, 0U), |
| 873 | SIMD_TUPLE(imm_v256_shr_n_u16<4>, 0U, 0U), |
| 874 | SIMD_TUPLE(imm_v256_shr_n_u16<6>, 0U, 0U), |
| 875 | SIMD_TUPLE(imm_v256_shr_n_u16<8>, 0U, 0U), |
| 876 | SIMD_TUPLE(imm_v256_shr_n_u16<10>, 0U, 0U), |
| 877 | SIMD_TUPLE(imm_v256_shr_n_u16<12>, 0U, 0U), |
| 878 | SIMD_TUPLE(imm_v256_shr_n_u16<14>, 0U, 0U), |
| 879 | SIMD_TUPLE(imm_v256_shr_n_s16<1>, 0U, 0U), |
| 880 | SIMD_TUPLE(imm_v256_shr_n_s16<2>, 0U, 0U), |
| 881 | SIMD_TUPLE(imm_v256_shr_n_s16<4>, 0U, 0U), |
| 882 | SIMD_TUPLE(imm_v256_shr_n_s16<6>, 0U, 0U), |
| 883 | SIMD_TUPLE(imm_v256_shr_n_s16<8>, 0U, 0U), |
| 884 | SIMD_TUPLE(imm_v256_shr_n_s16<10>, 0U, 0U), |
| 885 | SIMD_TUPLE(imm_v256_shr_n_s16<12>, 0U, 0U), |
| 886 | SIMD_TUPLE(imm_v256_shr_n_s16<14>, 0U, 0U), |
| 887 | SIMD_TUPLE(imm_v256_shl_n_32<1>, 0U, 0U), |
| 888 | SIMD_TUPLE(imm_v256_shl_n_32<4>, 0U, 0U), |
| 889 | SIMD_TUPLE(imm_v256_shl_n_32<8>, 0U, 0U), |
| 890 | SIMD_TUPLE(imm_v256_shl_n_32<12>, 0U, 0U), |
| 891 | SIMD_TUPLE(imm_v256_shl_n_32<16>, 0U, 0U), |
| 892 | SIMD_TUPLE(imm_v256_shl_n_32<20>, 0U, 0U), |
| 893 | SIMD_TUPLE(imm_v256_shl_n_32<24>, 0U, 0U), |
| 894 | SIMD_TUPLE(imm_v256_shl_n_32<28>, 0U, 0U), |
| 895 | SIMD_TUPLE(imm_v256_shr_n_u32<1>, 0U, 0U), |
| 896 | SIMD_TUPLE(imm_v256_shr_n_u32<4>, 0U, 0U), |
| 897 | SIMD_TUPLE(imm_v256_shr_n_u32<8>, 0U, 0U), |
| 898 | SIMD_TUPLE(imm_v256_shr_n_u32<12>, 0U, 0U), |
| 899 | SIMD_TUPLE(imm_v256_shr_n_u32<16>, 0U, 0U), |
| 900 | SIMD_TUPLE(imm_v256_shr_n_u32<20>, 0U, 0U), |
| 901 | SIMD_TUPLE(imm_v256_shr_n_u32<24>, 0U, 0U), |
| 902 | SIMD_TUPLE(imm_v256_shr_n_u32<28>, 0U, 0U), |
| 903 | SIMD_TUPLE(imm_v256_shr_n_s32<1>, 0U, 0U), |
| 904 | SIMD_TUPLE(imm_v256_shr_n_s32<4>, 0U, 0U), |
| 905 | SIMD_TUPLE(imm_v256_shr_n_s32<8>, 0U, 0U), |
| 906 | SIMD_TUPLE(imm_v256_shr_n_s32<12>, 0U, 0U), |
| 907 | SIMD_TUPLE(imm_v256_shr_n_s32<16>, 0U, 0U), |
| 908 | SIMD_TUPLE(imm_v256_shr_n_s32<20>, 0U, 0U), |
| 909 | SIMD_TUPLE(imm_v256_shr_n_s32<24>, 0U, 0U), |
| 910 | SIMD_TUPLE(imm_v256_shr_n_s32<28>, 0U, 0U)); |
| 911 | |
| 912 | INSTANTIATE(ARCH, ARCH_POSTFIX(V256_U8), SIMD_TUPLE(v256_dup_8, 0U, 0U)); |
| 913 | |
| 914 | INSTANTIATE(ARCH, ARCH_POSTFIX(V256_U16), SIMD_TUPLE(v256_dup_16, 0U, 0U)); |
| 915 | |
| 916 | INSTANTIATE(ARCH, ARCH_POSTFIX(V256_U32), SIMD_TUPLE(v256_dup_32, 0U, 0U)); |
| 917 | |
| 918 | INSTANTIATE(ARCH, ARCH_POSTFIX(U32_V256), SIMD_TUPLE(v256_low_u32, 0U, 0U)); |
| 919 | |
| 920 | INSTANTIATE(ARCH, ARCH_POSTFIX(V64_V256), SIMD_TUPLE(v256_low_v64, 0U, 0U)); |
| 921 | |
Steinar Midtskogen | 04305c6 | 2016-09-30 13:14:04 +0200 | [diff] [blame] | 922 | } // namespace SIMD_NAMESPACE |