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Yaowu Xuc27fc142016-08-22 16:08:15 -07001/*
Yaowu Xu2ab7ff02016-09-02 12:04:54 -07002 * Copyright (c) 2016, Alliance for Open Media. All rights reserved
Yaowu Xuc27fc142016-08-22 16:08:15 -07003 *
Yaowu Xu2ab7ff02016-09-02 12:04:54 -07004 * This source code is subject to the terms of the BSD 2 Clause License and
5 * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
6 * was not distributed with this source code in the LICENSE file, you can
7 * obtain it at www.aomedia.org/license/software. If the Alliance for Open
8 * Media Patent License 1.0 was not distributed with this source code in the
9 * PATENTS file, you can obtain it at www.aomedia.org/license/patent.
Yaowu Xuc27fc142016-08-22 16:08:15 -070010 */
11
12#include <assert.h>
13#include <math.h>
14#include <stdio.h>
15
Yaowu Xuf883b422016-08-30 14:01:10 -070016#include "./av1_rtcd.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070017
Yaowu Xuf883b422016-08-30 14:01:10 -070018#include "aom_dsp/aom_dsp_common.h"
19#include "aom_mem/aom_mem.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070020#include "aom_ports/bitops.h"
21#include "aom_ports/mem.h"
22#include "aom_ports/system_state.h"
23
24#include "av1/common/common.h"
25#include "av1/common/entropy.h"
26#include "av1/common/entropymode.h"
27#include "av1/common/mvref_common.h"
28#include "av1/common/pred_common.h"
29#include "av1/common/quant_common.h"
30#include "av1/common/reconinter.h"
31#include "av1/common/reconintra.h"
32#include "av1/common/seg_common.h"
33
Tom Finegan17ce8b12017-02-08 12:46:31 -080034#include "av1/encoder/av1_quantize.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070035#include "av1/encoder/cost.h"
36#include "av1/encoder/encodemb.h"
37#include "av1/encoder/encodemv.h"
38#include "av1/encoder/encoder.h"
39#include "av1/encoder/mcomp.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070040#include "av1/encoder/ratectrl.h"
41#include "av1/encoder/rd.h"
42#include "av1/encoder/tokenize.h"
43
44#define RD_THRESH_POW 1.25
45
46// Factor to weigh the rate for switchable interp filters.
47#define SWITCHABLE_INTERP_RATE_FACTOR 1
48
Yaowu Xuc27fc142016-08-22 16:08:15 -070049// The baseline rd thresholds for breaking out of the rd loop for
50// certain modes are assumed to be based on 8x8 blocks.
51// This table is used to correct for block size.
52// The factors here are << 2 (2 = x0.5, 32 = x8 etc).
53static const uint8_t rd_thresh_block_size_factor[BLOCK_SIZES] = {
Jingning Hanf1702dd2016-11-30 21:17:59 -080054#if CONFIG_CB4X4
55 2, 2, 2,
56#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -070057 2, 3, 3, 4, 6, 6, 8, 12, 12, 16, 24, 24, 32,
58#if CONFIG_EXT_PARTITION
59 48, 48, 64
60#endif // CONFIG_EXT_PARTITION
61};
62
Yaowu Xuf883b422016-08-30 14:01:10 -070063static void fill_mode_costs(AV1_COMP *cpi) {
Yaowu Xuc27fc142016-08-22 16:08:15 -070064 const FRAME_CONTEXT *const fc = cpi->common.fc;
65 int i, j;
66
67 for (i = 0; i < INTRA_MODES; ++i)
68 for (j = 0; j < INTRA_MODES; ++j)
Yaowu Xuf883b422016-08-30 14:01:10 -070069 av1_cost_tokens(cpi->y_mode_costs[i][j], av1_kf_y_mode_prob[i][j],
70 av1_intra_mode_tree);
Yaowu Xuc27fc142016-08-22 16:08:15 -070071
72 for (i = 0; i < BLOCK_SIZE_GROUPS; ++i)
Yaowu Xuf883b422016-08-30 14:01:10 -070073 av1_cost_tokens(cpi->mbmode_cost[i], fc->y_mode_prob[i],
74 av1_intra_mode_tree);
Yaowu Xuc27fc142016-08-22 16:08:15 -070075
76 for (i = 0; i < INTRA_MODES; ++i)
Yaowu Xuf883b422016-08-30 14:01:10 -070077 av1_cost_tokens(cpi->intra_uv_mode_cost[i], fc->uv_mode_prob[i],
78 av1_intra_mode_tree);
Yaowu Xuc27fc142016-08-22 16:08:15 -070079
80 for (i = 0; i < SWITCHABLE_FILTER_CONTEXTS; ++i)
Yaowu Xuf883b422016-08-30 14:01:10 -070081 av1_cost_tokens(cpi->switchable_interp_costs[i],
82 fc->switchable_interp_prob[i], av1_switchable_interp_tree);
Yaowu Xuc27fc142016-08-22 16:08:15 -070083
Urvang Joshib100db72016-10-12 16:28:56 -070084#if CONFIG_PALETTE
Yaowu Xuc27fc142016-08-22 16:08:15 -070085 for (i = 0; i < PALETTE_BLOCK_SIZES; ++i) {
Yaowu Xuf883b422016-08-30 14:01:10 -070086 av1_cost_tokens(cpi->palette_y_size_cost[i],
87 av1_default_palette_y_size_prob[i], av1_palette_size_tree);
88 av1_cost_tokens(cpi->palette_uv_size_cost[i],
89 av1_default_palette_uv_size_prob[i], av1_palette_size_tree);
Yaowu Xuc27fc142016-08-22 16:08:15 -070090 }
91
Alex Converse92109812017-02-22 10:21:40 -080092 for (i = 0; i < PALETTE_SIZES; ++i) {
Urvang Joshi23a61112017-01-30 14:59:27 -080093 for (j = 0; j < PALETTE_COLOR_INDEX_CONTEXTS; ++j) {
Yaowu Xuf883b422016-08-30 14:01:10 -070094 av1_cost_tokens(cpi->palette_y_color_cost[i][j],
Urvang Joshi23a61112017-01-30 14:59:27 -080095 av1_default_palette_y_color_index_prob[i][j],
96 av1_palette_color_index_tree[i]);
Yaowu Xuf883b422016-08-30 14:01:10 -070097 av1_cost_tokens(cpi->palette_uv_color_cost[i][j],
Urvang Joshi23a61112017-01-30 14:59:27 -080098 av1_default_palette_uv_color_index_prob[i][j],
99 av1_palette_color_index_tree[i]);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700100 }
Urvang Joshib100db72016-10-12 16:28:56 -0700101 }
102#endif // CONFIG_PALETTE
Yaowu Xuc27fc142016-08-22 16:08:15 -0700103
Jingning Hanaae72a62016-10-25 15:35:29 -0700104 for (i = 0; i < MAX_TX_DEPTH; ++i)
Yaowu Xuc27fc142016-08-22 16:08:15 -0700105 for (j = 0; j < TX_SIZE_CONTEXTS; ++j)
Yaowu Xuf883b422016-08-30 14:01:10 -0700106 av1_cost_tokens(cpi->tx_size_cost[i][j], fc->tx_size_probs[i][j],
107 av1_tx_size_tree[i]);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700108
109#if CONFIG_EXT_TX
110 for (i = TX_4X4; i < EXT_TX_SIZES; ++i) {
111 int s;
112 for (s = 1; s < EXT_TX_SETS_INTER; ++s) {
113 if (use_inter_ext_tx_for_txsize[s][i]) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700114 av1_cost_tokens(cpi->inter_tx_type_costs[s][i],
115 fc->inter_ext_tx_prob[s][i], av1_ext_tx_inter_tree[s]);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700116 }
117 }
118 for (s = 1; s < EXT_TX_SETS_INTRA; ++s) {
119 if (use_intra_ext_tx_for_txsize[s][i]) {
120 for (j = 0; j < INTRA_MODES; ++j)
Yaowu Xuf883b422016-08-30 14:01:10 -0700121 av1_cost_tokens(cpi->intra_tx_type_costs[s][i][j],
122 fc->intra_ext_tx_prob[s][i][j],
123 av1_ext_tx_intra_tree[s]);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700124 }
125 }
126 }
127#else
128 for (i = TX_4X4; i < EXT_TX_SIZES; ++i) {
129 for (j = 0; j < TX_TYPES; ++j)
Yaowu Xuf883b422016-08-30 14:01:10 -0700130 av1_cost_tokens(cpi->intra_tx_type_costs[i][j],
131 fc->intra_ext_tx_prob[i][j], av1_ext_tx_tree);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700132 }
133 for (i = TX_4X4; i < EXT_TX_SIZES; ++i) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700134 av1_cost_tokens(cpi->inter_tx_type_costs[i], fc->inter_ext_tx_prob[i],
135 av1_ext_tx_tree);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700136 }
137#endif // CONFIG_EXT_TX
138#if CONFIG_EXT_INTRA
hui sueda3d762016-12-06 16:58:23 -0800139#if CONFIG_INTRA_INTERP
Yaowu Xuc27fc142016-08-22 16:08:15 -0700140 for (i = 0; i < INTRA_FILTERS + 1; ++i)
Yaowu Xuf883b422016-08-30 14:01:10 -0700141 av1_cost_tokens(cpi->intra_filter_cost[i], fc->intra_filter_probs[i],
142 av1_intra_filter_tree);
hui sueda3d762016-12-06 16:58:23 -0800143#endif // CONFIG_INTRA_INTERP
Yaowu Xuc27fc142016-08-22 16:08:15 -0700144#endif // CONFIG_EXT_INTRA
Debargha Mukherjee5cd2ab92016-09-08 15:15:17 -0700145#if CONFIG_LOOP_RESTORATION
146 av1_cost_tokens(cpi->switchable_restore_cost, fc->switchable_restore_prob,
147 av1_switchable_restore_tree);
148#endif // CONFIG_LOOP_RESTORATION
Debargha Mukherjee9febfc12016-12-07 13:20:44 -0800149#if CONFIG_GLOBAL_MOTION
150 av1_cost_tokens(cpi->gmtype_cost, fc->global_motion_types_prob,
151 av1_global_motion_types_tree);
152#endif // CONFIG_GLOBAL_MOTION
Yaowu Xuc27fc142016-08-22 16:08:15 -0700153}
154
Yaowu Xuf883b422016-08-30 14:01:10 -0700155void av1_fill_token_costs(av1_coeff_cost *c,
Yaowu Xuf883b422016-08-30 14:01:10 -0700156 av1_coeff_probs_model (*p)[PLANE_TYPES]) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700157 int i, j, k, l;
158 TX_SIZE t;
Jingning Han6a9b2402016-12-16 11:56:56 -0800159 for (t = 0; t < TX_SIZES; ++t)
Yaowu Xuc27fc142016-08-22 16:08:15 -0700160 for (i = 0; i < PLANE_TYPES; ++i)
161 for (j = 0; j < REF_TYPES; ++j)
162 for (k = 0; k < COEF_BANDS; ++k)
163 for (l = 0; l < BAND_COEFF_CONTEXTS(k); ++l) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700164 aom_prob probs[ENTROPY_NODES];
165 av1_model_to_full_probs(p[t][i][j][k][l], probs);
166 av1_cost_tokens((int *)c[t][i][j][k][0][l], probs, av1_coef_tree);
167 av1_cost_tokens_skip((int *)c[t][i][j][k][1][l], probs,
168 av1_coef_tree);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700169 assert(c[t][i][j][k][0][l][EOB_TOKEN] ==
170 c[t][i][j][k][1][l][EOB_TOKEN]);
171 }
172}
173
174// Values are now correlated to quantizer.
175static int sad_per_bit16lut_8[QINDEX_RANGE];
176static int sad_per_bit4lut_8[QINDEX_RANGE];
177
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200178#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700179static int sad_per_bit16lut_10[QINDEX_RANGE];
180static int sad_per_bit4lut_10[QINDEX_RANGE];
181static int sad_per_bit16lut_12[QINDEX_RANGE];
182static int sad_per_bit4lut_12[QINDEX_RANGE];
183#endif
184
185static void init_me_luts_bd(int *bit16lut, int *bit4lut, int range,
Yaowu Xuf883b422016-08-30 14:01:10 -0700186 aom_bit_depth_t bit_depth) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700187 int i;
188 // Initialize the sad lut tables using a formulaic calculation for now.
189 // This is to make it easier to resolve the impact of experimental changes
190 // to the quantizer tables.
191 for (i = 0; i < range; i++) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700192 const double q = av1_convert_qindex_to_q(i, bit_depth);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700193 bit16lut[i] = (int)(0.0418 * q + 2.4107);
194 bit4lut[i] = (int)(0.063 * q + 2.742);
195 }
196}
197
Yaowu Xuf883b422016-08-30 14:01:10 -0700198void av1_init_me_luts(void) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700199 init_me_luts_bd(sad_per_bit16lut_8, sad_per_bit4lut_8, QINDEX_RANGE,
Yaowu Xuf883b422016-08-30 14:01:10 -0700200 AOM_BITS_8);
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200201#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700202 init_me_luts_bd(sad_per_bit16lut_10, sad_per_bit4lut_10, QINDEX_RANGE,
Yaowu Xuf883b422016-08-30 14:01:10 -0700203 AOM_BITS_10);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700204 init_me_luts_bd(sad_per_bit16lut_12, sad_per_bit4lut_12, QINDEX_RANGE,
Yaowu Xuf883b422016-08-30 14:01:10 -0700205 AOM_BITS_12);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700206#endif
207}
208
209static const int rd_boost_factor[16] = { 64, 32, 32, 32, 24, 16, 12, 12,
210 8, 8, 4, 4, 2, 2, 1, 0 };
211static const int rd_frame_type_factor[FRAME_UPDATE_TYPES] = {
212 128, 144, 128, 128, 144,
213#if CONFIG_EXT_REFS
214 // TODO(zoeliu): To adjust further following factor values.
215 128, 128, 128
216 // TODO(weitinglin): We should investigate if the values should be the same
217 // as the value used by OVERLAY frame
218 ,
219 144
220#endif // CONFIG_EXT_REFS
221};
222
Yaowu Xuf883b422016-08-30 14:01:10 -0700223int av1_compute_rd_mult(const AV1_COMP *cpi, int qindex) {
224 const int64_t q = av1_dc_quant(qindex, 0, cpi->common.bit_depth);
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200225#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700226 int64_t rdmult = 0;
227 switch (cpi->common.bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700228 case AOM_BITS_8: rdmult = 88 * q * q / 24; break;
229 case AOM_BITS_10: rdmult = ROUND_POWER_OF_TWO(88 * q * q / 24, 4); break;
230 case AOM_BITS_12: rdmult = ROUND_POWER_OF_TWO(88 * q * q / 24, 8); break;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700231 default:
Yaowu Xuf883b422016-08-30 14:01:10 -0700232 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -0700233 return -1;
234 }
235#else
236 int64_t rdmult = 88 * q * q / 24;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200237#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700238 if (cpi->oxcf.pass == 2 && (cpi->common.frame_type != KEY_FRAME)) {
239 const GF_GROUP *const gf_group = &cpi->twopass.gf_group;
240 const FRAME_UPDATE_TYPE frame_type = gf_group->update_type[gf_group->index];
Yaowu Xuf883b422016-08-30 14:01:10 -0700241 const int boost_index = AOMMIN(15, (cpi->rc.gfu_boost / 100));
Yaowu Xuc27fc142016-08-22 16:08:15 -0700242
243 rdmult = (rdmult * rd_frame_type_factor[frame_type]) >> 7;
244 rdmult += ((rdmult * rd_boost_factor[boost_index]) >> 7);
245 }
246 if (rdmult < 1) rdmult = 1;
247 return (int)rdmult;
248}
249
Yaowu Xuf883b422016-08-30 14:01:10 -0700250static int compute_rd_thresh_factor(int qindex, aom_bit_depth_t bit_depth) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700251 double q;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200252#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700253 switch (bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700254 case AOM_BITS_8: q = av1_dc_quant(qindex, 0, AOM_BITS_8) / 4.0; break;
255 case AOM_BITS_10: q = av1_dc_quant(qindex, 0, AOM_BITS_10) / 16.0; break;
256 case AOM_BITS_12: q = av1_dc_quant(qindex, 0, AOM_BITS_12) / 64.0; break;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700257 default:
Yaowu Xuf883b422016-08-30 14:01:10 -0700258 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -0700259 return -1;
260 }
261#else
262 (void)bit_depth;
Yaowu Xuf883b422016-08-30 14:01:10 -0700263 q = av1_dc_quant(qindex, 0, AOM_BITS_8) / 4.0;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200264#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700265 // TODO(debargha): Adjust the function below.
Yaowu Xuf883b422016-08-30 14:01:10 -0700266 return AOMMAX((int)(pow(q, RD_THRESH_POW) * 5.12), 8);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700267}
268
Yaowu Xuf883b422016-08-30 14:01:10 -0700269void av1_initialize_me_consts(const AV1_COMP *cpi, MACROBLOCK *x, int qindex) {
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200270#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700271 switch (cpi->common.bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700272 case AOM_BITS_8:
Yaowu Xuc27fc142016-08-22 16:08:15 -0700273 x->sadperbit16 = sad_per_bit16lut_8[qindex];
274 x->sadperbit4 = sad_per_bit4lut_8[qindex];
275 break;
Yaowu Xuf883b422016-08-30 14:01:10 -0700276 case AOM_BITS_10:
Yaowu Xuc27fc142016-08-22 16:08:15 -0700277 x->sadperbit16 = sad_per_bit16lut_10[qindex];
278 x->sadperbit4 = sad_per_bit4lut_10[qindex];
279 break;
Yaowu Xuf883b422016-08-30 14:01:10 -0700280 case AOM_BITS_12:
Yaowu Xuc27fc142016-08-22 16:08:15 -0700281 x->sadperbit16 = sad_per_bit16lut_12[qindex];
282 x->sadperbit4 = sad_per_bit4lut_12[qindex];
283 break;
284 default:
Yaowu Xuf883b422016-08-30 14:01:10 -0700285 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -0700286 }
287#else
288 (void)cpi;
289 x->sadperbit16 = sad_per_bit16lut_8[qindex];
290 x->sadperbit4 = sad_per_bit4lut_8[qindex];
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200291#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700292}
293
Yaowu Xuf883b422016-08-30 14:01:10 -0700294static void set_block_thresholds(const AV1_COMMON *cm, RD_OPT *rd) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700295 int i, bsize, segment_id;
296
297 for (segment_id = 0; segment_id < MAX_SEGMENTS; ++segment_id) {
298 const int qindex =
Yaowu Xuf883b422016-08-30 14:01:10 -0700299 clamp(av1_get_qindex(&cm->seg, segment_id, cm->base_qindex) +
Yaowu Xuc27fc142016-08-22 16:08:15 -0700300 cm->y_dc_delta_q,
301 0, MAXQ);
302 const int q = compute_rd_thresh_factor(qindex, cm->bit_depth);
303
304 for (bsize = 0; bsize < BLOCK_SIZES; ++bsize) {
305 // Threshold here seems unnecessarily harsh but fine given actual
306 // range of values used for cpi->sf.thresh_mult[].
307 const int t = q * rd_thresh_block_size_factor[bsize];
308 const int thresh_max = INT_MAX / t;
309
Jingning Han9104bed2016-12-14 09:38:00 -0800310#if CONFIG_CB4X4
311 for (i = 0; i < MAX_MODES; ++i)
312 rd->threshes[segment_id][bsize][i] = rd->thresh_mult[i] < thresh_max
313 ? rd->thresh_mult[i] * t / 4
314 : INT_MAX;
315#else
Yaowu Xuc27fc142016-08-22 16:08:15 -0700316 if (bsize >= BLOCK_8X8) {
317 for (i = 0; i < MAX_MODES; ++i)
318 rd->threshes[segment_id][bsize][i] = rd->thresh_mult[i] < thresh_max
319 ? rd->thresh_mult[i] * t / 4
320 : INT_MAX;
321 } else {
322 for (i = 0; i < MAX_REFS; ++i)
323 rd->threshes[segment_id][bsize][i] =
324 rd->thresh_mult_sub8x8[i] < thresh_max
325 ? rd->thresh_mult_sub8x8[i] * t / 4
326 : INT_MAX;
327 }
Jingning Han9104bed2016-12-14 09:38:00 -0800328#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700329 }
330 }
331}
332
Yaowu Xu4306b6e2016-09-27 12:55:32 -0700333void av1_set_mvcost(MACROBLOCK *x, MV_REFERENCE_FRAME ref_frame, int ref,
334 int ref_mv_idx) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700335 MB_MODE_INFO_EXT *mbmi_ext = x->mbmi_ext;
Yaowu Xu4306b6e2016-09-27 12:55:32 -0700336 int8_t rf_type = av1_ref_frame_type(x->e_mbd.mi[0]->mbmi.ref_frame);
337 int nmv_ctx = av1_nmv_ctx(mbmi_ext->ref_mv_count[rf_type],
338 mbmi_ext->ref_mv_stack[rf_type], ref, ref_mv_idx);
339 (void)ref_frame;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700340 x->mvcost = x->mv_cost_stack[nmv_ctx];
341 x->nmvjointcost = x->nmv_vec_cost[nmv_ctx];
342 x->mvsadcost = x->mvcost;
343 x->nmvjointsadcost = x->nmvjointcost;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700344}
Yaowu Xuc27fc142016-08-22 16:08:15 -0700345
Yaowu Xuf883b422016-08-30 14:01:10 -0700346void av1_initialize_rd_consts(AV1_COMP *cpi) {
347 AV1_COMMON *const cm = &cpi->common;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700348 MACROBLOCK *const x = &cpi->td.mb;
349 RD_OPT *const rd = &cpi->rd;
350 int i;
Jingning Hanb3b034d2016-11-29 17:57:14 -0800351 int nmv_ctx;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700352
Yaowu Xuf883b422016-08-30 14:01:10 -0700353 aom_clear_system_state();
Yaowu Xuc27fc142016-08-22 16:08:15 -0700354
355 rd->RDDIV = RDDIV_BITS; // In bits (to multiply D by 128).
Yaowu Xuf883b422016-08-30 14:01:10 -0700356 rd->RDMULT = av1_compute_rd_mult(cpi, cm->base_qindex + cm->y_dc_delta_q);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700357
358 set_error_per_bit(x, rd->RDMULT);
359
360 set_block_thresholds(cm, rd);
361
Jingning Hanb3b034d2016-11-29 17:57:14 -0800362 for (nmv_ctx = 0; nmv_ctx < NMV_CONTEXTS; ++nmv_ctx) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700363 av1_build_nmv_cost_table(
Jingning Hanb3b034d2016-11-29 17:57:14 -0800364 x->nmv_vec_cost[nmv_ctx],
365 cm->allow_high_precision_mv ? x->nmvcost_hp[nmv_ctx]
366 : x->nmvcost[nmv_ctx],
367 &cm->fc->nmvc[nmv_ctx], cm->allow_high_precision_mv);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700368 }
Jingning Hanb3b034d2016-11-29 17:57:14 -0800369 x->mvcost = x->mv_cost_stack[0];
370 x->nmvjointcost = x->nmv_vec_cost[0];
371 x->mvsadcost = x->mvcost;
372 x->nmvjointsadcost = x->nmvjointcost;
Jingning Hanb3b034d2016-11-29 17:57:14 -0800373
Yaowu Xuc27fc142016-08-22 16:08:15 -0700374 if (cpi->oxcf.pass != 1) {
Alex Converseccf472b2016-10-12 13:03:55 -0700375 av1_fill_token_costs(x->token_costs, cm->fc->coef_probs);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700376
377 if (cpi->sf.partition_search_type != VAR_BASED_PARTITION ||
378 cm->frame_type == KEY_FRAME) {
379#if CONFIG_EXT_PARTITION_TYPES
Alex Converse4e18d402017-03-14 15:36:38 -0700380 for (i = 0; i < PARTITION_PLOFFSET; ++i)
Alex Converse2b9d19d2017-04-03 11:11:17 -0700381 av1_cost_tokens(cpi->partition_cost[i], cm->fc->partition_prob[i],
382 av1_partition_tree);
Alex Converse4e18d402017-03-14 15:36:38 -0700383 for (; i < PARTITION_CONTEXTS_PRIMARY; ++i)
Alex Converse2b9d19d2017-04-03 11:11:17 -0700384 av1_cost_tokens(cpi->partition_cost[i], cm->fc->partition_prob[i],
385 av1_ext_partition_tree);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700386#else
Alex Converse55c6bde2017-01-12 15:55:31 -0800387 for (i = 0; i < PARTITION_CONTEXTS_PRIMARY; ++i)
Alex Converse2b9d19d2017-04-03 11:11:17 -0700388 av1_cost_tokens(cpi->partition_cost[i], cm->fc->partition_prob[i],
389 av1_partition_tree);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700390#endif // CONFIG_EXT_PARTITION_TYPES
Alex Converse55c6bde2017-01-12 15:55:31 -0800391#if CONFIG_UNPOISON_PARTITION_CTX
392 for (; i < PARTITION_CONTEXTS_PRIMARY + PARTITION_BLOCK_SIZES; ++i) {
393 aom_prob p = cm->fc->partition_prob[i][PARTITION_VERT];
394 assert(p > 0);
Alex Converse2b9d19d2017-04-03 11:11:17 -0700395 cpi->partition_cost[i][PARTITION_NONE] = INT_MAX;
396 cpi->partition_cost[i][PARTITION_HORZ] = INT_MAX;
397 cpi->partition_cost[i][PARTITION_VERT] = av1_cost_bit(p, 0);
398 cpi->partition_cost[i][PARTITION_SPLIT] = av1_cost_bit(p, 1);
Alex Converse55c6bde2017-01-12 15:55:31 -0800399 }
400 for (; i < PARTITION_CONTEXTS_PRIMARY + 2 * PARTITION_BLOCK_SIZES; ++i) {
401 aom_prob p = cm->fc->partition_prob[i][PARTITION_HORZ];
402 assert(p > 0);
Alex Converse2b9d19d2017-04-03 11:11:17 -0700403 cpi->partition_cost[i][PARTITION_NONE] = INT_MAX;
404 cpi->partition_cost[i][PARTITION_HORZ] = av1_cost_bit(p, 0);
405 cpi->partition_cost[i][PARTITION_VERT] = INT_MAX;
406 cpi->partition_cost[i][PARTITION_SPLIT] = av1_cost_bit(p, 1);
Alex Converse55c6bde2017-01-12 15:55:31 -0800407 }
Alex Converse2b9d19d2017-04-03 11:11:17 -0700408 cpi->partition_cost[PARTITION_CONTEXTS][PARTITION_NONE] = INT_MAX;
409 cpi->partition_cost[PARTITION_CONTEXTS][PARTITION_HORZ] = INT_MAX;
410 cpi->partition_cost[PARTITION_CONTEXTS][PARTITION_VERT] = INT_MAX;
411 cpi->partition_cost[PARTITION_CONTEXTS][PARTITION_SPLIT] = 0;
412#endif // CONFIG_UNPOISON_PARTITION_CTX
Yaowu Xuc27fc142016-08-22 16:08:15 -0700413 }
414
415 fill_mode_costs(cpi);
416
417 if (!frame_is_intra_only(cm)) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700418 for (i = 0; i < NEWMV_MODE_CONTEXTS; ++i) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700419 cpi->newmv_mode_cost[i][0] = av1_cost_bit(cm->fc->newmv_prob[i], 0);
420 cpi->newmv_mode_cost[i][1] = av1_cost_bit(cm->fc->newmv_prob[i], 1);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700421 }
422
423 for (i = 0; i < ZEROMV_MODE_CONTEXTS; ++i) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700424 cpi->zeromv_mode_cost[i][0] = av1_cost_bit(cm->fc->zeromv_prob[i], 0);
425 cpi->zeromv_mode_cost[i][1] = av1_cost_bit(cm->fc->zeromv_prob[i], 1);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700426 }
427
428 for (i = 0; i < REFMV_MODE_CONTEXTS; ++i) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700429 cpi->refmv_mode_cost[i][0] = av1_cost_bit(cm->fc->refmv_prob[i], 0);
430 cpi->refmv_mode_cost[i][1] = av1_cost_bit(cm->fc->refmv_prob[i], 1);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700431 }
432
433 for (i = 0; i < DRL_MODE_CONTEXTS; ++i) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700434 cpi->drl_mode_cost0[i][0] = av1_cost_bit(cm->fc->drl_prob[i], 0);
435 cpi->drl_mode_cost0[i][1] = av1_cost_bit(cm->fc->drl_prob[i], 1);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700436 }
Yaowu Xuc27fc142016-08-22 16:08:15 -0700437#if CONFIG_EXT_INTER
438 for (i = 0; i < INTER_MODE_CONTEXTS; ++i)
Yaowu Xuf883b422016-08-30 14:01:10 -0700439 av1_cost_tokens((int *)cpi->inter_compound_mode_cost[i],
440 cm->fc->inter_compound_mode_probs[i],
441 av1_inter_compound_mode_tree);
Yue Chen4d26acb2017-05-01 12:28:34 -0700442#if CONFIG_INTERINTRA
Yaowu Xuc27fc142016-08-22 16:08:15 -0700443 for (i = 0; i < BLOCK_SIZE_GROUPS; ++i)
Yaowu Xuf883b422016-08-30 14:01:10 -0700444 av1_cost_tokens((int *)cpi->interintra_mode_cost[i],
445 cm->fc->interintra_mode_prob[i],
446 av1_interintra_mode_tree);
Yue Chen4d26acb2017-05-01 12:28:34 -0700447#endif // CONFIG_INTERINTRA
Yaowu Xuc27fc142016-08-22 16:08:15 -0700448#endif // CONFIG_EXT_INTER
Yue Chencb60b182016-10-13 15:18:22 -0700449#if CONFIG_MOTION_VAR || CONFIG_WARPED_MOTION
Yaowu Xuc27fc142016-08-22 16:08:15 -0700450 for (i = BLOCK_8X8; i < BLOCK_SIZES; i++) {
Yue Chencb60b182016-10-13 15:18:22 -0700451 av1_cost_tokens((int *)cpi->motion_mode_cost[i],
452 cm->fc->motion_mode_prob[i], av1_motion_mode_tree);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700453 }
Yue Chen69f18e12016-09-08 14:48:15 -0700454#if CONFIG_MOTION_VAR && CONFIG_WARPED_MOTION
455 for (i = BLOCK_8X8; i < BLOCK_SIZES; i++) {
456 cpi->motion_mode_cost1[i][0] = av1_cost_bit(cm->fc->obmc_prob[i], 0);
457 cpi->motion_mode_cost1[i][1] = av1_cost_bit(cm->fc->obmc_prob[i], 1);
458 }
459#endif // CONFIG_MOTION_VAR && CONFIG_WARPED_MOTION
Yue Chencb60b182016-10-13 15:18:22 -0700460#endif // CONFIG_MOTION_VAR || CONFIG_WARPED_MOTION
Yaowu Xuc27fc142016-08-22 16:08:15 -0700461 }
462 }
463}
464
465static void model_rd_norm(int xsq_q10, int *r_q10, int *d_q10) {
466 // NOTE: The tables below must be of the same size.
467
468 // The functions described below are sampled at the four most significant
469 // bits of x^2 + 8 / 256.
470
471 // Normalized rate:
472 // This table models the rate for a Laplacian source with given variance
473 // when quantized with a uniform quantizer with given stepsize. The
474 // closed form expression is:
475 // Rn(x) = H(sqrt(r)) + sqrt(r)*[1 + H(r)/(1 - r)],
476 // where r = exp(-sqrt(2) * x) and x = qpstep / sqrt(variance),
477 // and H(x) is the binary entropy function.
478 static const int rate_tab_q10[] = {
479 65536, 6086, 5574, 5275, 5063, 4899, 4764, 4651, 4553, 4389, 4255, 4142,
480 4044, 3958, 3881, 3811, 3748, 3635, 3538, 3453, 3376, 3307, 3244, 3186,
481 3133, 3037, 2952, 2877, 2809, 2747, 2690, 2638, 2589, 2501, 2423, 2353,
482 2290, 2232, 2179, 2130, 2084, 2001, 1928, 1862, 1802, 1748, 1698, 1651,
483 1608, 1530, 1460, 1398, 1342, 1290, 1243, 1199, 1159, 1086, 1021, 963,
484 911, 864, 821, 781, 745, 680, 623, 574, 530, 490, 455, 424,
485 395, 345, 304, 269, 239, 213, 190, 171, 154, 126, 104, 87,
486 73, 61, 52, 44, 38, 28, 21, 16, 12, 10, 8, 6,
487 5, 3, 2, 1, 1, 1, 0, 0,
488 };
489 // Normalized distortion:
490 // This table models the normalized distortion for a Laplacian source
491 // with given variance when quantized with a uniform quantizer
492 // with given stepsize. The closed form expression is:
493 // Dn(x) = 1 - 1/sqrt(2) * x / sinh(x/sqrt(2))
494 // where x = qpstep / sqrt(variance).
495 // Note the actual distortion is Dn * variance.
496 static const int dist_tab_q10[] = {
497 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 4, 5,
498 5, 6, 7, 7, 8, 9, 11, 12, 13, 15, 16, 17,
499 18, 21, 24, 26, 29, 31, 34, 36, 39, 44, 49, 54,
500 59, 64, 69, 73, 78, 88, 97, 106, 115, 124, 133, 142,
501 151, 167, 184, 200, 215, 231, 245, 260, 274, 301, 327, 351,
502 375, 397, 418, 439, 458, 495, 528, 559, 587, 613, 637, 659,
503 680, 717, 749, 777, 801, 823, 842, 859, 874, 899, 919, 936,
504 949, 960, 969, 977, 983, 994, 1001, 1006, 1010, 1013, 1015, 1017,
505 1018, 1020, 1022, 1022, 1023, 1023, 1023, 1024,
506 };
507 static const int xsq_iq_q10[] = {
508 0, 4, 8, 12, 16, 20, 24, 28, 32,
509 40, 48, 56, 64, 72, 80, 88, 96, 112,
510 128, 144, 160, 176, 192, 208, 224, 256, 288,
511 320, 352, 384, 416, 448, 480, 544, 608, 672,
512 736, 800, 864, 928, 992, 1120, 1248, 1376, 1504,
513 1632, 1760, 1888, 2016, 2272, 2528, 2784, 3040, 3296,
514 3552, 3808, 4064, 4576, 5088, 5600, 6112, 6624, 7136,
515 7648, 8160, 9184, 10208, 11232, 12256, 13280, 14304, 15328,
516 16352, 18400, 20448, 22496, 24544, 26592, 28640, 30688, 32736,
517 36832, 40928, 45024, 49120, 53216, 57312, 61408, 65504, 73696,
518 81888, 90080, 98272, 106464, 114656, 122848, 131040, 147424, 163808,
519 180192, 196576, 212960, 229344, 245728,
520 };
521 const int tmp = (xsq_q10 >> 2) + 8;
522 const int k = get_msb(tmp) - 3;
523 const int xq = (k << 3) + ((tmp >> k) & 0x7);
524 const int one_q10 = 1 << 10;
525 const int a_q10 = ((xsq_q10 - xsq_iq_q10[xq]) << 10) >> (2 + k);
526 const int b_q10 = one_q10 - a_q10;
527 *r_q10 = (rate_tab_q10[xq] * b_q10 + rate_tab_q10[xq + 1] * a_q10) >> 10;
528 *d_q10 = (dist_tab_q10[xq] * b_q10 + dist_tab_q10[xq + 1] * a_q10) >> 10;
529}
530
Yaowu Xuf883b422016-08-30 14:01:10 -0700531void av1_model_rd_from_var_lapndz(int64_t var, unsigned int n_log2,
532 unsigned int qstep, int *rate,
533 int64_t *dist) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700534 // This function models the rate and distortion for a Laplacian
535 // source with given variance when quantized with a uniform quantizer
536 // with given stepsize. The closed form expressions are in:
537 // Hang and Chen, "Source Model for transform video coder and its
538 // application - Part I: Fundamental Theory", IEEE Trans. Circ.
539 // Sys. for Video Tech., April 1997.
540 if (var == 0) {
541 *rate = 0;
542 *dist = 0;
543 } else {
544 int d_q10, r_q10;
545 static const uint32_t MAX_XSQ_Q10 = 245727;
546 const uint64_t xsq_q10_64 =
547 (((uint64_t)qstep * qstep << (n_log2 + 10)) + (var >> 1)) / var;
Yaowu Xuf883b422016-08-30 14:01:10 -0700548 const int xsq_q10 = (int)AOMMIN(xsq_q10_64, MAX_XSQ_Q10);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700549 model_rd_norm(xsq_q10, &r_q10, &d_q10);
Yaowu Xuf883b422016-08-30 14:01:10 -0700550 *rate = ROUND_POWER_OF_TWO(r_q10 << n_log2, 10 - AV1_PROB_COST_SHIFT);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700551 *dist = (var * (int64_t)d_q10 + 512) >> 10;
552 }
553}
554
555static void get_entropy_contexts_plane(
556 BLOCK_SIZE plane_bsize, TX_SIZE tx_size, const struct macroblockd_plane *pd,
557 ENTROPY_CONTEXT t_above[2 * MAX_MIB_SIZE],
558 ENTROPY_CONTEXT t_left[2 * MAX_MIB_SIZE]) {
Jingning Han9eef06d2016-12-05 12:39:34 -0800559 const int num_4x4_w = block_size_wide[plane_bsize] >> tx_size_wide_log2[0];
560 const int num_4x4_h = block_size_high[plane_bsize] >> tx_size_high_log2[0];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700561 const ENTROPY_CONTEXT *const above = pd->above_context;
562 const ENTROPY_CONTEXT *const left = pd->left_context;
563
564 int i;
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800565
Jingning Han39772c12016-12-01 12:47:05 -0800566#if CONFIG_CB4X4
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800567 switch (tx_size) {
Jingning Han39772c12016-12-01 12:47:05 -0800568 case TX_2X2:
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800569 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
570 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
571 break;
572 case TX_4X4:
573 for (i = 0; i < num_4x4_w; i += 2)
574 t_above[i] = !!*(const uint16_t *)&above[i];
575 for (i = 0; i < num_4x4_h; i += 2)
576 t_left[i] = !!*(const uint16_t *)&left[i];
577 break;
578 case TX_8X8:
579 for (i = 0; i < num_4x4_w; i += 4)
580 t_above[i] = !!*(const uint32_t *)&above[i];
581 for (i = 0; i < num_4x4_h; i += 4)
582 t_left[i] = !!*(const uint32_t *)&left[i];
583 break;
584 case TX_16X16:
585 for (i = 0; i < num_4x4_w; i += 8)
586 t_above[i] = !!*(const uint64_t *)&above[i];
587 for (i = 0; i < num_4x4_h; i += 8)
588 t_left[i] = !!*(const uint64_t *)&left[i];
589 break;
590 case TX_32X32:
591 for (i = 0; i < num_4x4_w; i += 16)
592 t_above[i] =
593 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
594 for (i = 0; i < num_4x4_h; i += 16)
595 t_left[i] =
596 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
597 break;
Urvang Joshi4c6d4362017-05-11 12:35:46 -0700598#if CONFIG_TX64X64
599 case TX_64X64:
600 for (i = 0; i < num_4x4_w; i += 32)
601 t_above[i] =
602 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8] |
603 *(const uint64_t *)&above[i + 16] |
604 *(const uint64_t *)&above[i + 24]);
605 for (i = 0; i < num_4x4_h; i += 32)
606 t_left[i] =
607 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8] |
608 *(const uint64_t *)&left[i + 16] |
609 *(const uint64_t *)&left[i + 24]);
610 break;
611#endif // CONFIG_TX64X64
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800612 case TX_4X8:
613 for (i = 0; i < num_4x4_w; i += 2)
614 t_above[i] = !!*(const uint16_t *)&above[i];
615 for (i = 0; i < num_4x4_h; i += 4)
616 t_left[i] = !!*(const uint32_t *)&left[i];
617 break;
618 case TX_8X4:
619 for (i = 0; i < num_4x4_w; i += 4)
620 t_above[i] = !!*(const uint32_t *)&above[i];
621 for (i = 0; i < num_4x4_h; i += 2)
622 t_left[i] = !!*(const uint16_t *)&left[i];
623 break;
624 case TX_8X16:
625 for (i = 0; i < num_4x4_w; i += 4)
626 t_above[i] = !!*(const uint32_t *)&above[i];
627 for (i = 0; i < num_4x4_h; i += 8)
628 t_left[i] = !!*(const uint64_t *)&left[i];
629 break;
630 case TX_16X8:
631 for (i = 0; i < num_4x4_w; i += 8)
632 t_above[i] = !!*(const uint64_t *)&above[i];
633 for (i = 0; i < num_4x4_h; i += 4)
634 t_left[i] = !!*(const uint32_t *)&left[i];
635 break;
636 case TX_16X32:
637 for (i = 0; i < num_4x4_w; i += 8)
638 t_above[i] = !!*(const uint64_t *)&above[i];
639 for (i = 0; i < num_4x4_h; i += 16)
640 t_left[i] =
641 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
642 break;
643 case TX_32X16:
644 for (i = 0; i < num_4x4_w; i += 16)
645 t_above[i] =
646 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
647 for (i = 0; i < num_4x4_h; i += 8)
648 t_left[i] = !!*(const uint64_t *)&left[i];
Jingning Han0f6a60a2017-01-20 09:25:40 -0800649 break;
Yue Chen56e226e2017-05-02 16:21:40 -0700650#if CONFIG_EXT_TX && CONFIG_RECT_TX && CONFIG_RECT_TX_EXT
651 case TX_4X16:
652 for (i = 0; i < num_4x4_w; i += 2)
653 t_above[i] = !!*(const uint16_t *)&above[i];
654 for (i = 0; i < num_4x4_h; i += 8)
655 t_left[i] = !!*(const uint64_t *)&left[i];
656 break;
657 case TX_16X4:
658 for (i = 0; i < num_4x4_w; i += 8)
659 t_above[i] = !!*(const uint64_t *)&above[i];
660 for (i = 0; i < num_4x4_h; i += 2)
661 t_left[i] = !!*(const uint16_t *)&left[i];
662 break;
663 case TX_8X32:
664 for (i = 0; i < num_4x4_w; i += 4)
665 t_above[i] = !!*(const uint32_t *)&above[i];
666 for (i = 0; i < num_4x4_h; i += 16)
667 t_left[i] =
668 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
669 break;
670 case TX_32X8:
671 for (i = 0; i < num_4x4_w; i += 16)
672 t_above[i] =
673 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
674 for (i = 0; i < num_4x4_h; i += 4)
675 t_left[i] = !!*(const uint32_t *)&left[i];
676 break;
677#endif // CONFIG_EXT_TX && CONFIG_RECT_TX && CONFIG_RECT_TX_EXT
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800678
679 default: assert(0 && "Invalid transform size."); break;
680 }
681 return;
Jingning Han39772c12016-12-01 12:47:05 -0800682#endif
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800683
684 switch (tx_size) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700685 case TX_4X4:
686 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
687 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
688 break;
689 case TX_8X8:
690 for (i = 0; i < num_4x4_w; i += 2)
691 t_above[i] = !!*(const uint16_t *)&above[i];
692 for (i = 0; i < num_4x4_h; i += 2)
693 t_left[i] = !!*(const uint16_t *)&left[i];
694 break;
695 case TX_16X16:
696 for (i = 0; i < num_4x4_w; i += 4)
697 t_above[i] = !!*(const uint32_t *)&above[i];
698 for (i = 0; i < num_4x4_h; i += 4)
699 t_left[i] = !!*(const uint32_t *)&left[i];
700 break;
701 case TX_32X32:
702 for (i = 0; i < num_4x4_w; i += 8)
703 t_above[i] = !!*(const uint64_t *)&above[i];
704 for (i = 0; i < num_4x4_h; i += 8)
705 t_left[i] = !!*(const uint64_t *)&left[i];
706 break;
Debargha Mukherjee153e1f82016-11-17 09:59:14 -0800707#if CONFIG_TX64X64
708 case TX_64X64:
709 for (i = 0; i < num_4x4_w; i += 16)
710 t_above[i] =
711 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
712 for (i = 0; i < num_4x4_h; i += 16)
Debargha Mukherjee932cf692016-11-18 08:14:10 -0800713 t_left[i] =
714 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
Debargha Mukherjee153e1f82016-11-17 09:59:14 -0800715 break;
716#endif // CONFIG_TX64X64
Yaowu Xuc27fc142016-08-22 16:08:15 -0700717 case TX_4X8:
718 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
719 for (i = 0; i < num_4x4_h; i += 2)
720 t_left[i] = !!*(const uint16_t *)&left[i];
721 break;
722 case TX_8X4:
723 for (i = 0; i < num_4x4_w; i += 2)
724 t_above[i] = !!*(const uint16_t *)&above[i];
725 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
726 break;
727 case TX_8X16:
728 for (i = 0; i < num_4x4_w; i += 2)
729 t_above[i] = !!*(const uint16_t *)&above[i];
730 for (i = 0; i < num_4x4_h; i += 4)
731 t_left[i] = !!*(const uint32_t *)&left[i];
732 break;
733 case TX_16X8:
734 for (i = 0; i < num_4x4_w; i += 4)
735 t_above[i] = !!*(const uint32_t *)&above[i];
736 for (i = 0; i < num_4x4_h; i += 2)
737 t_left[i] = !!*(const uint16_t *)&left[i];
738 break;
739 case TX_16X32:
740 for (i = 0; i < num_4x4_w; i += 4)
741 t_above[i] = !!*(const uint32_t *)&above[i];
742 for (i = 0; i < num_4x4_h; i += 8)
743 t_left[i] = !!*(const uint64_t *)&left[i];
744 break;
745 case TX_32X16:
746 for (i = 0; i < num_4x4_w; i += 8)
747 t_above[i] = !!*(const uint64_t *)&above[i];
748 for (i = 0; i < num_4x4_h; i += 4)
749 t_left[i] = !!*(const uint32_t *)&left[i];
750 break;
Yue Chen56e226e2017-05-02 16:21:40 -0700751#if CONFIG_EXT_TX && CONFIG_RECT_TX && CONFIG_RECT_TX_EXT
752 case TX_4X16:
753 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
754 for (i = 0; i < num_4x4_h; i += 4)
755 t_left[i] = !!*(const uint32_t *)&left[i];
756 break;
757 case TX_16X4:
758 for (i = 0; i < num_4x4_w; i += 4)
759 t_above[i] = !!*(const uint32_t *)&above[i];
760 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
761 break;
762 case TX_8X32:
763 for (i = 0; i < num_4x4_w; i += 2)
764 t_above[i] = !!*(const uint16_t *)&above[i];
765 for (i = 0; i < num_4x4_h; i += 8)
766 t_left[i] = !!*(const uint64_t *)&left[i];
767 break;
768 case TX_32X8:
769 for (i = 0; i < num_4x4_w; i += 8)
770 t_above[i] = !!*(const uint64_t *)&above[i];
771 for (i = 0; i < num_4x4_h; i += 2)
772 t_left[i] = !!*(const uint16_t *)&left[i];
773 break;
774#endif // CONFIG_EXT_TX && CONFIG_RECT_TX && CONFIG_RECT_TX_EXT
Yaowu Xuc27fc142016-08-22 16:08:15 -0700775 default: assert(0 && "Invalid transform size."); break;
776 }
777}
778
Yaowu Xuf883b422016-08-30 14:01:10 -0700779void av1_get_entropy_contexts(BLOCK_SIZE bsize, TX_SIZE tx_size,
780 const struct macroblockd_plane *pd,
781 ENTROPY_CONTEXT t_above[2 * MAX_MIB_SIZE],
782 ENTROPY_CONTEXT t_left[2 * MAX_MIB_SIZE]) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700783 const BLOCK_SIZE plane_bsize = get_plane_block_size(bsize, pd);
784 get_entropy_contexts_plane(plane_bsize, tx_size, pd, t_above, t_left);
785}
786
Urvang Joshi52648442016-10-13 17:27:51 -0700787void av1_mv_pred(const AV1_COMP *cpi, MACROBLOCK *x, uint8_t *ref_y_buffer,
Yaowu Xuf883b422016-08-30 14:01:10 -0700788 int ref_y_stride, int ref_frame, BLOCK_SIZE block_size) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700789 int i;
790 int zero_seen = 0;
791 int best_index = 0;
792 int best_sad = INT_MAX;
793 int this_sad = INT_MAX;
794 int max_mv = 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700795 uint8_t *src_y_ptr = x->plane[0].src.buf;
796 uint8_t *ref_y_ptr;
Thomas Daede07438572017-05-10 11:22:33 -0700797 MV pred_mv[MAX_MV_REF_CANDIDATES + 1];
Debargha Mukherjeed80d63f2017-05-17 15:53:27 -0700798 int num_mv_refs = 0;
799
800 pred_mv[num_mv_refs++] = x->mbmi_ext->ref_mvs[ref_frame][0].as_mv;
801 if (x->mbmi_ext->ref_mvs[ref_frame][0].as_int !=
802 x->mbmi_ext->ref_mvs[ref_frame][1].as_int) {
803 pred_mv[num_mv_refs++] = x->mbmi_ext->ref_mvs[ref_frame][1].as_mv;
Thomas Daede07438572017-05-10 11:22:33 -0700804 }
Debargha Mukherjeed80d63f2017-05-17 15:53:27 -0700805 if (cpi->sf.adaptive_motion_search && block_size < x->max_partition_size)
806 pred_mv[num_mv_refs++] = x->pred_mv[ref_frame];
807
Yaowu Xuc27fc142016-08-22 16:08:15 -0700808 assert(num_mv_refs <= (int)(sizeof(pred_mv) / sizeof(pred_mv[0])));
Debargha Mukherjeed80d63f2017-05-17 15:53:27 -0700809
Yaowu Xuc27fc142016-08-22 16:08:15 -0700810 // Get the sad for each candidate reference mv.
811 for (i = 0; i < num_mv_refs; ++i) {
812 const MV *this_mv = &pred_mv[i];
813 int fp_row, fp_col;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700814 fp_row = (this_mv->row + 3 + (this_mv->row >= 0)) >> 3;
815 fp_col = (this_mv->col + 3 + (this_mv->col >= 0)) >> 3;
Yaowu Xuf883b422016-08-30 14:01:10 -0700816 max_mv = AOMMAX(max_mv, AOMMAX(abs(this_mv->row), abs(this_mv->col)) >> 3);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700817
818 if (fp_row == 0 && fp_col == 0 && zero_seen) continue;
819 zero_seen |= (fp_row == 0 && fp_col == 0);
820
821 ref_y_ptr = &ref_y_buffer[ref_y_stride * fp_row + fp_col];
822 // Find sad for current vector.
823 this_sad = cpi->fn_ptr[block_size].sdf(src_y_ptr, x->plane[0].src.stride,
824 ref_y_ptr, ref_y_stride);
825 // Note if it is the best so far.
826 if (this_sad < best_sad) {
827 best_sad = this_sad;
828 best_index = i;
829 }
830 }
831
832 // Note the index of the mv that worked best in the reference list.
833 x->mv_best_ref_index[ref_frame] = best_index;
834 x->max_mv_context[ref_frame] = max_mv;
835 x->pred_mv_sad[ref_frame] = best_sad;
836}
837
Yaowu Xuf883b422016-08-30 14:01:10 -0700838void av1_setup_pred_block(const MACROBLOCKD *xd,
839 struct buf_2d dst[MAX_MB_PLANE],
840 const YV12_BUFFER_CONFIG *src, int mi_row, int mi_col,
841 const struct scale_factors *scale,
842 const struct scale_factors *scale_uv) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700843 int i;
844
845 dst[0].buf = src->y_buffer;
846 dst[0].stride = src->y_stride;
847 dst[1].buf = src->u_buffer;
848 dst[2].buf = src->v_buffer;
849 dst[1].stride = dst[2].stride = src->uv_stride;
850
851 for (i = 0; i < MAX_MB_PLANE; ++i) {
Jingning Han91d9a792017-04-18 12:01:52 -0700852 setup_pred_plane(dst + i, xd->mi[0]->mbmi.sb_type, dst[i].buf,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700853 i ? src->uv_crop_width : src->y_crop_width,
854 i ? src->uv_crop_height : src->y_crop_height,
855 dst[i].stride, mi_row, mi_col, i ? scale_uv : scale,
856 xd->plane[i].subsampling_x, xd->plane[i].subsampling_y);
857 }
858}
859
Yaowu Xuf883b422016-08-30 14:01:10 -0700860int av1_raster_block_offset(BLOCK_SIZE plane_bsize, int raster_block,
861 int stride) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700862 const int bw = b_width_log2_lookup[plane_bsize];
863 const int y = 4 * (raster_block >> bw);
864 const int x = 4 * (raster_block & ((1 << bw) - 1));
865 return y * stride + x;
866}
867
Yaowu Xuf883b422016-08-30 14:01:10 -0700868int16_t *av1_raster_block_offset_int16(BLOCK_SIZE plane_bsize, int raster_block,
869 int16_t *base) {
Jingning Hanae5cfde2016-11-30 12:01:44 -0800870 const int stride = block_size_wide[plane_bsize];
Yaowu Xuf883b422016-08-30 14:01:10 -0700871 return base + av1_raster_block_offset(plane_bsize, raster_block, stride);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700872}
873
Yaowu Xuf883b422016-08-30 14:01:10 -0700874YV12_BUFFER_CONFIG *av1_get_scaled_ref_frame(const AV1_COMP *cpi,
875 int ref_frame) {
876 const AV1_COMMON *const cm = &cpi->common;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700877 const int scaled_idx = cpi->scaled_ref_idx[ref_frame - 1];
878 const int ref_idx = get_ref_frame_buf_idx(cpi, ref_frame);
879 return (scaled_idx != ref_idx && scaled_idx != INVALID_IDX)
880 ? &cm->buffer_pool->frame_bufs[scaled_idx].buf
881 : NULL;
882}
883
884#if CONFIG_DUAL_FILTER
Angie Chiang65eb2cf2016-10-26 10:48:47 -0700885int av1_get_switchable_rate(const AV1_COMP *cpi, const MACROBLOCKD *xd) {
Angie Chiang75c22092016-10-25 12:19:16 -0700886 const AV1_COMMON *const cm = &cpi->common;
887 if (cm->interp_filter == SWITCHABLE) {
888 const MB_MODE_INFO *const mbmi = &xd->mi[0]->mbmi;
889 int inter_filter_cost = 0;
890 int dir;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700891
Angie Chiang75c22092016-10-25 12:19:16 -0700892 for (dir = 0; dir < 2; ++dir) {
893 if (has_subpel_mv_component(xd->mi[0], xd, dir) ||
894 (mbmi->ref_frame[1] > INTRA_FRAME &&
895 has_subpel_mv_component(xd->mi[0], xd, dir + 2))) {
896 const int ctx = av1_get_pred_context_switchable_interp(xd, dir);
897 inter_filter_cost +=
898 cpi->switchable_interp_costs[ctx][mbmi->interp_filter[dir]];
899 }
Yaowu Xuc27fc142016-08-22 16:08:15 -0700900 }
Angie Chiang75c22092016-10-25 12:19:16 -0700901 return SWITCHABLE_INTERP_RATE_FACTOR * inter_filter_cost;
902 } else {
903 return 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700904 }
Yaowu Xuc27fc142016-08-22 16:08:15 -0700905}
906#else
Angie Chiang65eb2cf2016-10-26 10:48:47 -0700907int av1_get_switchable_rate(const AV1_COMP *cpi, const MACROBLOCKD *xd) {
Angie Chiang75c22092016-10-25 12:19:16 -0700908 const AV1_COMMON *const cm = &cpi->common;
909 if (cm->interp_filter == SWITCHABLE) {
Angie Chiang1733f6b2017-01-05 09:52:20 -0800910 const MB_MODE_INFO *const mbmi = &xd->mi[0]->mbmi;
911 const int ctx = av1_get_pred_context_switchable_interp(xd);
912 return SWITCHABLE_INTERP_RATE_FACTOR *
913 cpi->switchable_interp_costs[ctx][mbmi->interp_filter];
Angie Chiang75c22092016-10-25 12:19:16 -0700914 }
915 return 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700916}
917#endif
918
Yaowu Xuf883b422016-08-30 14:01:10 -0700919void av1_set_rd_speed_thresholds(AV1_COMP *cpi) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700920 int i;
921 RD_OPT *const rd = &cpi->rd;
922 SPEED_FEATURES *const sf = &cpi->sf;
923
924 // Set baseline threshold values.
Thomas Daede6eca8352017-03-17 14:14:12 -0700925 for (i = 0; i < MAX_MODES; ++i) rd->thresh_mult[i] = cpi->oxcf.mode == 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700926
927 if (sf->adaptive_rd_thresh) {
928 rd->thresh_mult[THR_NEARESTMV] = 300;
929#if CONFIG_EXT_REFS
930 rd->thresh_mult[THR_NEARESTL2] = 300;
931 rd->thresh_mult[THR_NEARESTL3] = 300;
932 rd->thresh_mult[THR_NEARESTB] = 300;
933#endif // CONFIG_EXT_REFS
934 rd->thresh_mult[THR_NEARESTA] = 300;
935 rd->thresh_mult[THR_NEARESTG] = 300;
936 } else {
937 rd->thresh_mult[THR_NEARESTMV] = 0;
938#if CONFIG_EXT_REFS
939 rd->thresh_mult[THR_NEARESTL2] = 0;
940 rd->thresh_mult[THR_NEARESTL3] = 0;
941 rd->thresh_mult[THR_NEARESTB] = 0;
942#endif // CONFIG_EXT_REFS
943 rd->thresh_mult[THR_NEARESTA] = 0;
944 rd->thresh_mult[THR_NEARESTG] = 0;
945 }
946
947 rd->thresh_mult[THR_DC] += 1000;
948
949 rd->thresh_mult[THR_NEWMV] += 1000;
950#if CONFIG_EXT_REFS
951 rd->thresh_mult[THR_NEWL2] += 1000;
952 rd->thresh_mult[THR_NEWL3] += 1000;
953 rd->thresh_mult[THR_NEWB] += 1000;
954#endif // CONFIG_EXT_REFS
955 rd->thresh_mult[THR_NEWA] += 1000;
956 rd->thresh_mult[THR_NEWG] += 1000;
957
958 rd->thresh_mult[THR_NEARMV] += 1000;
959#if CONFIG_EXT_REFS
960 rd->thresh_mult[THR_NEARL2] += 1000;
961 rd->thresh_mult[THR_NEARL3] += 1000;
962 rd->thresh_mult[THR_NEARB] += 1000;
963#endif // CONFIG_EXT_REFS
964 rd->thresh_mult[THR_NEARA] += 1000;
965 rd->thresh_mult[THR_NEARG] += 1000;
966
Yaowu Xuc27fc142016-08-22 16:08:15 -0700967 rd->thresh_mult[THR_ZEROMV] += 2000;
968#if CONFIG_EXT_REFS
969 rd->thresh_mult[THR_ZEROL2] += 2000;
970 rd->thresh_mult[THR_ZEROL3] += 2000;
971 rd->thresh_mult[THR_ZEROB] += 2000;
972#endif // CONFIG_EXT_REFS
973 rd->thresh_mult[THR_ZEROG] += 2000;
974 rd->thresh_mult[THR_ZEROA] += 2000;
975
976 rd->thresh_mult[THR_TM] += 1000;
977
978#if CONFIG_EXT_INTER
979
980 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLA] += 1000;
981#if CONFIG_EXT_REFS
982 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL2A] += 1000;
983 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL3A] += 1000;
984#endif // CONFIG_EXT_REFS
985 rd->thresh_mult[THR_COMP_NEAREST_NEARESTGA] += 1000;
986#if CONFIG_EXT_REFS
987 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLB] += 1000;
988 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL2B] += 1000;
989 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL3B] += 1000;
990 rd->thresh_mult[THR_COMP_NEAREST_NEARESTGB] += 1000;
991#endif // CONFIG_EXT_REFS
992
993#else // CONFIG_EXT_INTER
994
995 rd->thresh_mult[THR_COMP_NEARESTLA] += 1000;
996#if CONFIG_EXT_REFS
997 rd->thresh_mult[THR_COMP_NEARESTL2A] += 1000;
998 rd->thresh_mult[THR_COMP_NEARESTL3A] += 1000;
999#endif // CONFIG_EXT_REFS
1000 rd->thresh_mult[THR_COMP_NEARESTGA] += 1000;
1001#if CONFIG_EXT_REFS
1002 rd->thresh_mult[THR_COMP_NEARESTLB] += 1000;
1003 rd->thresh_mult[THR_COMP_NEARESTL2B] += 1000;
1004 rd->thresh_mult[THR_COMP_NEARESTL3B] += 1000;
1005 rd->thresh_mult[THR_COMP_NEARESTGB] += 1000;
1006#endif // CONFIG_EXT_REFS
1007
1008#endif // CONFIG_EXT_INTER
1009
1010#if CONFIG_EXT_INTER
1011
Yaowu Xuc27fc142016-08-22 16:08:15 -07001012 rd->thresh_mult[THR_COMP_NEAR_NEARLA] += 1200;
1013 rd->thresh_mult[THR_COMP_NEAREST_NEWLA] += 1500;
1014 rd->thresh_mult[THR_COMP_NEW_NEARESTLA] += 1500;
1015 rd->thresh_mult[THR_COMP_NEAR_NEWLA] += 1700;
1016 rd->thresh_mult[THR_COMP_NEW_NEARLA] += 1700;
1017 rd->thresh_mult[THR_COMP_NEW_NEWLA] += 2000;
1018 rd->thresh_mult[THR_COMP_ZERO_ZEROLA] += 2500;
1019
1020#if CONFIG_EXT_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001021 rd->thresh_mult[THR_COMP_NEAR_NEARL2A] += 1200;
1022 rd->thresh_mult[THR_COMP_NEAREST_NEWL2A] += 1500;
1023 rd->thresh_mult[THR_COMP_NEW_NEARESTL2A] += 1500;
1024 rd->thresh_mult[THR_COMP_NEAR_NEWL2A] += 1700;
1025 rd->thresh_mult[THR_COMP_NEW_NEARL2A] += 1700;
1026 rd->thresh_mult[THR_COMP_NEW_NEWL2A] += 2000;
1027 rd->thresh_mult[THR_COMP_ZERO_ZEROL2A] += 2500;
1028
Yaowu Xuc27fc142016-08-22 16:08:15 -07001029 rd->thresh_mult[THR_COMP_NEAR_NEARL3A] += 1200;
1030 rd->thresh_mult[THR_COMP_NEAREST_NEWL3A] += 1500;
1031 rd->thresh_mult[THR_COMP_NEW_NEARESTL3A] += 1500;
1032 rd->thresh_mult[THR_COMP_NEAR_NEWL3A] += 1700;
1033 rd->thresh_mult[THR_COMP_NEW_NEARL3A] += 1700;
1034 rd->thresh_mult[THR_COMP_NEW_NEWL3A] += 2000;
1035 rd->thresh_mult[THR_COMP_ZERO_ZEROL3A] += 2500;
1036#endif // CONFIG_EXT_REFS
1037
Yaowu Xuc27fc142016-08-22 16:08:15 -07001038 rd->thresh_mult[THR_COMP_NEAR_NEARGA] += 1200;
1039 rd->thresh_mult[THR_COMP_NEAREST_NEWGA] += 1500;
1040 rd->thresh_mult[THR_COMP_NEW_NEARESTGA] += 1500;
1041 rd->thresh_mult[THR_COMP_NEAR_NEWGA] += 1700;
1042 rd->thresh_mult[THR_COMP_NEW_NEARGA] += 1700;
1043 rd->thresh_mult[THR_COMP_NEW_NEWGA] += 2000;
1044 rd->thresh_mult[THR_COMP_ZERO_ZEROGA] += 2500;
1045
1046#if CONFIG_EXT_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001047 rd->thresh_mult[THR_COMP_NEAR_NEARLB] += 1200;
1048 rd->thresh_mult[THR_COMP_NEAREST_NEWLB] += 1500;
1049 rd->thresh_mult[THR_COMP_NEW_NEARESTLB] += 1500;
1050 rd->thresh_mult[THR_COMP_NEAR_NEWLB] += 1700;
1051 rd->thresh_mult[THR_COMP_NEW_NEARLB] += 1700;
1052 rd->thresh_mult[THR_COMP_NEW_NEWLB] += 2000;
1053 rd->thresh_mult[THR_COMP_ZERO_ZEROLB] += 2500;
1054
Yaowu Xuc27fc142016-08-22 16:08:15 -07001055 rd->thresh_mult[THR_COMP_NEAR_NEARL2B] += 1200;
1056 rd->thresh_mult[THR_COMP_NEAREST_NEWL2B] += 1500;
1057 rd->thresh_mult[THR_COMP_NEW_NEARESTL2B] += 1500;
1058 rd->thresh_mult[THR_COMP_NEAR_NEWL2B] += 1700;
1059 rd->thresh_mult[THR_COMP_NEW_NEARL2B] += 1700;
1060 rd->thresh_mult[THR_COMP_NEW_NEWL2B] += 2000;
1061 rd->thresh_mult[THR_COMP_ZERO_ZEROL2B] += 2500;
1062
Yaowu Xuc27fc142016-08-22 16:08:15 -07001063 rd->thresh_mult[THR_COMP_NEAR_NEARL3B] += 1200;
1064 rd->thresh_mult[THR_COMP_NEAREST_NEWL3B] += 1500;
1065 rd->thresh_mult[THR_COMP_NEW_NEARESTL3B] += 1500;
1066 rd->thresh_mult[THR_COMP_NEAR_NEWL3B] += 1700;
1067 rd->thresh_mult[THR_COMP_NEW_NEARL3B] += 1700;
1068 rd->thresh_mult[THR_COMP_NEW_NEWL3B] += 2000;
1069 rd->thresh_mult[THR_COMP_ZERO_ZEROL3B] += 2500;
1070
Yaowu Xuc27fc142016-08-22 16:08:15 -07001071 rd->thresh_mult[THR_COMP_NEAR_NEARGB] += 1200;
1072 rd->thresh_mult[THR_COMP_NEAREST_NEWGB] += 1500;
1073 rd->thresh_mult[THR_COMP_NEW_NEARESTGB] += 1500;
1074 rd->thresh_mult[THR_COMP_NEAR_NEWGB] += 1700;
1075 rd->thresh_mult[THR_COMP_NEW_NEARGB] += 1700;
1076 rd->thresh_mult[THR_COMP_NEW_NEWGB] += 2000;
1077 rd->thresh_mult[THR_COMP_ZERO_ZEROGB] += 2500;
1078#endif // CONFIG_EXT_REFS
1079
1080#else // CONFIG_EXT_INTER
1081
1082 rd->thresh_mult[THR_COMP_NEARLA] += 1500;
1083 rd->thresh_mult[THR_COMP_NEWLA] += 2000;
1084#if CONFIG_EXT_REFS
1085 rd->thresh_mult[THR_COMP_NEARL2A] += 1500;
1086 rd->thresh_mult[THR_COMP_NEWL2A] += 2000;
1087 rd->thresh_mult[THR_COMP_NEARL3A] += 1500;
1088 rd->thresh_mult[THR_COMP_NEWL3A] += 2000;
1089#endif // CONFIG_EXT_REFS
1090 rd->thresh_mult[THR_COMP_NEARGA] += 1500;
1091 rd->thresh_mult[THR_COMP_NEWGA] += 2000;
1092
1093#if CONFIG_EXT_REFS
1094 rd->thresh_mult[THR_COMP_NEARLB] += 1500;
1095 rd->thresh_mult[THR_COMP_NEWLB] += 2000;
1096 rd->thresh_mult[THR_COMP_NEARL2B] += 1500;
1097 rd->thresh_mult[THR_COMP_NEWL2B] += 2000;
1098 rd->thresh_mult[THR_COMP_NEARL3B] += 1500;
1099 rd->thresh_mult[THR_COMP_NEWL3B] += 2000;
1100 rd->thresh_mult[THR_COMP_NEARGB] += 1500;
1101 rd->thresh_mult[THR_COMP_NEWGB] += 2000;
1102#endif // CONFIG_EXT_REFS
1103
1104 rd->thresh_mult[THR_COMP_ZEROLA] += 2500;
1105#if CONFIG_EXT_REFS
1106 rd->thresh_mult[THR_COMP_ZEROL2A] += 2500;
1107 rd->thresh_mult[THR_COMP_ZEROL3A] += 2500;
1108#endif // CONFIG_EXT_REFS
1109 rd->thresh_mult[THR_COMP_ZEROGA] += 2500;
1110
1111#if CONFIG_EXT_REFS
1112 rd->thresh_mult[THR_COMP_ZEROLB] += 2500;
1113 rd->thresh_mult[THR_COMP_ZEROL2B] += 2500;
1114 rd->thresh_mult[THR_COMP_ZEROL3B] += 2500;
1115 rd->thresh_mult[THR_COMP_ZEROGB] += 2500;
1116#endif // CONFIG_EXT_REFS
1117
1118#endif // CONFIG_EXT_INTER
1119
1120 rd->thresh_mult[THR_H_PRED] += 2000;
1121 rd->thresh_mult[THR_V_PRED] += 2000;
1122 rd->thresh_mult[THR_D135_PRED] += 2500;
1123 rd->thresh_mult[THR_D207_PRED] += 2500;
1124 rd->thresh_mult[THR_D153_PRED] += 2500;
1125 rd->thresh_mult[THR_D63_PRED] += 2500;
1126 rd->thresh_mult[THR_D117_PRED] += 2500;
1127 rd->thresh_mult[THR_D45_PRED] += 2500;
1128
1129#if CONFIG_EXT_INTER
1130 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROL] += 1500;
1131 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTL] += 1500;
1132 rd->thresh_mult[THR_COMP_INTERINTRA_NEARL] += 1500;
1133 rd->thresh_mult[THR_COMP_INTERINTRA_NEWL] += 2000;
1134
1135#if CONFIG_EXT_REFS
1136 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROL2] += 1500;
1137 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTL2] += 1500;
1138 rd->thresh_mult[THR_COMP_INTERINTRA_NEARL2] += 1500;
1139 rd->thresh_mult[THR_COMP_INTERINTRA_NEWL2] += 2000;
1140
1141 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROL3] += 1500;
1142 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTL3] += 1500;
1143 rd->thresh_mult[THR_COMP_INTERINTRA_NEARL3] += 1500;
1144 rd->thresh_mult[THR_COMP_INTERINTRA_NEWL3] += 2000;
1145#endif // CONFIG_EXT_REFS
1146
1147 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROG] += 1500;
1148 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTG] += 1500;
1149 rd->thresh_mult[THR_COMP_INTERINTRA_NEARG] += 1500;
1150 rd->thresh_mult[THR_COMP_INTERINTRA_NEWG] += 2000;
1151
1152#if CONFIG_EXT_REFS
1153 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROB] += 1500;
1154 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTB] += 1500;
1155 rd->thresh_mult[THR_COMP_INTERINTRA_NEARB] += 1500;
1156 rd->thresh_mult[THR_COMP_INTERINTRA_NEWB] += 2000;
1157#endif // CONFIG_EXT_REFS
1158
1159 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROA] += 1500;
1160 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTA] += 1500;
1161 rd->thresh_mult[THR_COMP_INTERINTRA_NEARA] += 1500;
1162 rd->thresh_mult[THR_COMP_INTERINTRA_NEWA] += 2000;
1163#endif // CONFIG_EXT_INTER
1164}
1165
Yaowu Xuf883b422016-08-30 14:01:10 -07001166void av1_set_rd_speed_thresholds_sub8x8(AV1_COMP *cpi) {
Thomas Daede6eca8352017-03-17 14:14:12 -07001167 static const int thresh_mult[MAX_REFS] = {
Yaowu Xuc27fc142016-08-22 16:08:15 -07001168#if CONFIG_EXT_REFS
Thomas Daede6eca8352017-03-17 14:14:12 -07001169 2500,
1170 2500,
1171 2500,
1172 2500,
1173 2500,
1174 2500,
1175 4500,
1176 4500,
1177 4500,
1178 4500,
1179 4500,
1180 4500,
1181 4500,
1182 4500,
1183 2500
Yaowu Xuc27fc142016-08-22 16:08:15 -07001184#else
Thomas Daede6eca8352017-03-17 14:14:12 -07001185 2500,
1186 2500,
1187 2500,
1188 4500,
1189 4500,
1190 2500
Yaowu Xuc27fc142016-08-22 16:08:15 -07001191#endif // CONFIG_EXT_REFS
1192 };
1193 RD_OPT *const rd = &cpi->rd;
Thomas Daede6eca8352017-03-17 14:14:12 -07001194 memcpy(rd->thresh_mult_sub8x8, thresh_mult, sizeof(thresh_mult));
Yaowu Xuc27fc142016-08-22 16:08:15 -07001195}
1196
Yaowu Xuf883b422016-08-30 14:01:10 -07001197void av1_update_rd_thresh_fact(const AV1_COMMON *const cm,
1198 int (*factor_buf)[MAX_MODES], int rd_thresh,
1199 int bsize, int best_mode_index) {
Yaowu Xuc27fc142016-08-22 16:08:15 -07001200 if (rd_thresh > 0) {
Jingning Han9104bed2016-12-14 09:38:00 -08001201#if CONFIG_CB4X4
1202 const int top_mode = MAX_MODES;
1203#else
Yaowu Xuc27fc142016-08-22 16:08:15 -07001204 const int top_mode = bsize < BLOCK_8X8 ? MAX_REFS : MAX_MODES;
Jingning Han9104bed2016-12-14 09:38:00 -08001205#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -07001206 int mode;
1207 for (mode = 0; mode < top_mode; ++mode) {
Yaowu Xuf883b422016-08-30 14:01:10 -07001208 const BLOCK_SIZE min_size = AOMMAX(bsize - 1, BLOCK_4X4);
Urvang Joshicb586f32016-09-20 11:36:33 -07001209 const BLOCK_SIZE max_size = AOMMIN(bsize + 2, (int)cm->sb_size);
Yaowu Xuc27fc142016-08-22 16:08:15 -07001210 BLOCK_SIZE bs;
1211 for (bs = min_size; bs <= max_size; ++bs) {
1212 int *const fact = &factor_buf[bs][mode];
1213 if (mode == best_mode_index) {
1214 *fact -= (*fact >> 4);
1215 } else {
Yaowu Xuf883b422016-08-30 14:01:10 -07001216 *fact = AOMMIN(*fact + RD_THRESH_INC, rd_thresh * RD_THRESH_MAX_FACT);
Yaowu Xuc27fc142016-08-22 16:08:15 -07001217 }
1218 }
1219 }
1220 }
1221}
1222
Yaowu Xuf883b422016-08-30 14:01:10 -07001223int av1_get_intra_cost_penalty(int qindex, int qdelta,
1224 aom_bit_depth_t bit_depth) {
1225 const int q = av1_dc_quant(qindex, qdelta, bit_depth);
Sebastien Alaiwan71e87842017-04-12 16:03:28 +02001226#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -07001227 switch (bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -07001228 case AOM_BITS_8: return 20 * q;
1229 case AOM_BITS_10: return 5 * q;
1230 case AOM_BITS_12: return ROUND_POWER_OF_TWO(5 * q, 2);
Yaowu Xuc27fc142016-08-22 16:08:15 -07001231 default:
Yaowu Xuf883b422016-08-30 14:01:10 -07001232 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -07001233 return -1;
1234 }
1235#else
1236 return 20 * q;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +02001237#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -07001238}