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Yaowu Xuc27fc142016-08-22 16:08:15 -07001/*
Yaowu Xu2ab7ff02016-09-02 12:04:54 -07002 * Copyright (c) 2016, Alliance for Open Media. All rights reserved
Yaowu Xuc27fc142016-08-22 16:08:15 -07003 *
Yaowu Xu2ab7ff02016-09-02 12:04:54 -07004 * This source code is subject to the terms of the BSD 2 Clause License and
5 * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
6 * was not distributed with this source code in the LICENSE file, you can
7 * obtain it at www.aomedia.org/license/software. If the Alliance for Open
8 * Media Patent License 1.0 was not distributed with this source code in the
9 * PATENTS file, you can obtain it at www.aomedia.org/license/patent.
Yaowu Xuc27fc142016-08-22 16:08:15 -070010 */
11
12#include <assert.h>
13#include <math.h>
14#include <stdio.h>
15
Yaowu Xuf883b422016-08-30 14:01:10 -070016#include "./av1_rtcd.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070017
Yaowu Xuf883b422016-08-30 14:01:10 -070018#include "aom_dsp/aom_dsp_common.h"
19#include "aom_mem/aom_mem.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070020#include "aom_ports/bitops.h"
21#include "aom_ports/mem.h"
22#include "aom_ports/system_state.h"
23
24#include "av1/common/common.h"
25#include "av1/common/entropy.h"
26#include "av1/common/entropymode.h"
27#include "av1/common/mvref_common.h"
28#include "av1/common/pred_common.h"
29#include "av1/common/quant_common.h"
30#include "av1/common/reconinter.h"
31#include "av1/common/reconintra.h"
32#include "av1/common/seg_common.h"
33
Tom Finegan17ce8b12017-02-08 12:46:31 -080034#include "av1/encoder/av1_quantize.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070035#include "av1/encoder/cost.h"
36#include "av1/encoder/encodemb.h"
37#include "av1/encoder/encodemv.h"
38#include "av1/encoder/encoder.h"
39#include "av1/encoder/mcomp.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070040#include "av1/encoder/ratectrl.h"
41#include "av1/encoder/rd.h"
42#include "av1/encoder/tokenize.h"
43
44#define RD_THRESH_POW 1.25
45
46// Factor to weigh the rate for switchable interp filters.
47#define SWITCHABLE_INTERP_RATE_FACTOR 1
48
Yaowu Xuc27fc142016-08-22 16:08:15 -070049// The baseline rd thresholds for breaking out of the rd loop for
50// certain modes are assumed to be based on 8x8 blocks.
51// This table is used to correct for block size.
52// The factors here are << 2 (2 = x0.5, 32 = x8 etc).
Rupert Swarbrick93c39e92017-07-12 11:11:02 +010053static const uint8_t rd_thresh_block_size_factor[BLOCK_SIZES_ALL] = {
Timothy B. Terriberry81ec2612017-04-26 16:53:47 -070054#if CONFIG_CHROMA_2X2 || CONFIG_CHROMA_SUB8X8
Jingning Hanf1702dd2016-11-30 21:17:59 -080055 2, 2, 2,
56#endif
Rupert Swarbrick72678572017-08-02 12:05:26 +010057 2, 3, 3, 4, 6, 6, 8, 12, 12, 16, 24, 24, 32,
Yaowu Xuc27fc142016-08-22 16:08:15 -070058#if CONFIG_EXT_PARTITION
Rupert Swarbrick93c39e92017-07-12 11:11:02 +010059 48, 48, 64,
Yaowu Xuc27fc142016-08-22 16:08:15 -070060#endif // CONFIG_EXT_PARTITION
Rupert Swarbrick72678572017-08-02 12:05:26 +010061 4, 4, 8, 8, 16, 16
Yaowu Xuc27fc142016-08-22 16:08:15 -070062};
63
Yue Chenb23d00a2017-07-28 17:01:21 -070064void av1_fill_mode_rates(AV1_COMMON *const cm, MACROBLOCK *x,
65 FRAME_CONTEXT *fc) {
Yaowu Xuc27fc142016-08-22 16:08:15 -070066 int i, j;
67
Yue Chenb23d00a2017-07-28 17:01:21 -070068 if (cm->frame_type == KEY_FRAME) {
Yue Chenb23d00a2017-07-28 17:01:21 -070069 for (i = 0; i < PARTITION_CONTEXTS_PRIMARY; ++i)
Yue Chenba47c842017-08-02 16:07:59 -070070 av1_cost_tokens_from_cdf(x->partition_cost[i], fc->partition_cdf[i],
71 NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -070072#if CONFIG_UNPOISON_PARTITION_CTX
73 for (; i < PARTITION_CONTEXTS_PRIMARY + PARTITION_BLOCK_SIZES; ++i) {
74 aom_prob p = fc->partition_prob[i][PARTITION_VERT];
75 assert(p > 0);
76 x->partition_cost[i][PARTITION_NONE] = INT_MAX;
77 x->partition_cost[i][PARTITION_HORZ] = INT_MAX;
78 x->partition_cost[i][PARTITION_VERT] = av1_cost_bit(p, 0);
79 x->partition_cost[i][PARTITION_SPLIT] = av1_cost_bit(p, 1);
80 }
81 for (; i < PARTITION_CONTEXTS_PRIMARY + 2 * PARTITION_BLOCK_SIZES; ++i) {
82 aom_prob p = fc->partition_prob[i][PARTITION_HORZ];
83 assert(p > 0);
84 x->partition_cost[i][PARTITION_NONE] = INT_MAX;
85 x->partition_cost[i][PARTITION_HORZ] = av1_cost_bit(p, 0);
86 x->partition_cost[i][PARTITION_VERT] = INT_MAX;
87 x->partition_cost[i][PARTITION_SPLIT] = av1_cost_bit(p, 1);
88 }
89 x->partition_cost[PARTITION_CONTEXTS][PARTITION_NONE] = INT_MAX;
90 x->partition_cost[PARTITION_CONTEXTS][PARTITION_HORZ] = INT_MAX;
91 x->partition_cost[PARTITION_CONTEXTS][PARTITION_VERT] = INT_MAX;
92 x->partition_cost[PARTITION_CONTEXTS][PARTITION_SPLIT] = 0;
93#endif // CONFIG_UNPOISON_PARTITION_CTX
94 }
95
Yaowu Xuc27fc142016-08-22 16:08:15 -070096 for (i = 0; i < INTRA_MODES; ++i)
97 for (j = 0; j < INTRA_MODES; ++j)
Yue Chenb23d00a2017-07-28 17:01:21 -070098 av1_cost_tokens_from_cdf(x->y_mode_costs[i][j], av1_kf_y_mode_cdf[i][j],
Nathan E. Egge693eedd2017-06-29 20:01:58 -040099 av1_intra_mode_inv);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700100
101 for (i = 0; i < BLOCK_SIZE_GROUPS; ++i)
Yue Chenb23d00a2017-07-28 17:01:21 -0700102 av1_cost_tokens_from_cdf(x->mbmode_cost[i], fc->y_mode_cdf[i],
Nathan E. Egge693eedd2017-06-29 20:01:58 -0400103 av1_intra_mode_inv);
Luc Trudeau6e1cd782017-06-21 13:52:36 -0400104 const int *uv_mode_inv_map =
105#if CONFIG_CFL
106 // CfL codes the uv_mode without reordering it
107 NULL;
108#else
109 av1_intra_mode_inv;
110#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700111 for (i = 0; i < INTRA_MODES; ++i)
Yue Chenb23d00a2017-07-28 17:01:21 -0700112 av1_cost_tokens_from_cdf(x->intra_uv_mode_cost[i], fc->uv_mode_cdf[i],
Luc Trudeau6e1cd782017-06-21 13:52:36 -0400113 uv_mode_inv_map);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700114
115 for (i = 0; i < SWITCHABLE_FILTER_CONTEXTS; ++i)
Yue Chenba47c842017-08-02 16:07:59 -0700116 av1_cost_tokens_from_cdf(x->switchable_interp_costs[i],
117 fc->switchable_interp_cdf[i],
118 av1_switchable_interp_inv);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700119
Urvang Joshib100db72016-10-12 16:28:56 -0700120#if CONFIG_PALETTE
Yaowu Xuc27fc142016-08-22 16:08:15 -0700121 for (i = 0; i < PALETTE_BLOCK_SIZES; ++i) {
Yue Chenb23d00a2017-07-28 17:01:21 -0700122 av1_cost_tokens_from_cdf(x->palette_y_size_cost[i],
hui su466ae062017-07-25 16:55:51 -0700123 fc->palette_y_size_cdf[i], NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700124 av1_cost_tokens_from_cdf(x->palette_uv_size_cost[i],
hui su466ae062017-07-25 16:55:51 -0700125 fc->palette_uv_size_cdf[i], NULL);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700126 }
127
Alex Converse92109812017-02-22 10:21:40 -0800128 for (i = 0; i < PALETTE_SIZES; ++i) {
Urvang Joshi23a61112017-01-30 14:59:27 -0800129 for (j = 0; j < PALETTE_COLOR_INDEX_CONTEXTS; ++j) {
Yue Chenb23d00a2017-07-28 17:01:21 -0700130 av1_cost_tokens_from_cdf(x->palette_y_color_cost[i][j],
hui su466ae062017-07-25 16:55:51 -0700131 fc->palette_y_color_index_cdf[i][j], NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700132 av1_cost_tokens_from_cdf(x->palette_uv_color_cost[i][j],
hui su466ae062017-07-25 16:55:51 -0700133 fc->palette_uv_color_index_cdf[i][j], NULL);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700134 }
Urvang Joshib100db72016-10-12 16:28:56 -0700135 }
136#endif // CONFIG_PALETTE
Yaowu Xuc27fc142016-08-22 16:08:15 -0700137
Jingning Hanaae72a62016-10-25 15:35:29 -0700138 for (i = 0; i < MAX_TX_DEPTH; ++i)
Yaowu Xuc27fc142016-08-22 16:08:15 -0700139 for (j = 0; j < TX_SIZE_CONTEXTS; ++j)
Yue Chenba47c842017-08-02 16:07:59 -0700140 av1_cost_tokens_from_cdf(x->tx_size_cost[i][j], fc->tx_size_cdf[i][j],
141 NULL);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700142
143#if CONFIG_EXT_TX
144 for (i = TX_4X4; i < EXT_TX_SIZES; ++i) {
145 int s;
146 for (s = 1; s < EXT_TX_SETS_INTER; ++s) {
147 if (use_inter_ext_tx_for_txsize[s][i]) {
Yue Chenba47c842017-08-02 16:07:59 -0700148 av1_cost_tokens_from_cdf(x->inter_tx_type_costs[s][i],
149 fc->inter_ext_tx_cdf[s][i],
150 av1_ext_tx_inter_inv[s]);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700151 }
152 }
153 for (s = 1; s < EXT_TX_SETS_INTRA; ++s) {
154 if (use_intra_ext_tx_for_txsize[s][i]) {
155 for (j = 0; j < INTRA_MODES; ++j)
Yue Chenba47c842017-08-02 16:07:59 -0700156 av1_cost_tokens_from_cdf(x->intra_tx_type_costs[s][i][j],
157 fc->intra_ext_tx_cdf[s][i][j],
158 av1_ext_tx_intra_inv[s]);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700159 }
160 }
161 }
162#else
163 for (i = TX_4X4; i < EXT_TX_SIZES; ++i) {
164 for (j = 0; j < TX_TYPES; ++j)
Yue Chenba47c842017-08-02 16:07:59 -0700165 av1_cost_tokens_from_cdf(x->intra_tx_type_costs[i][j],
166 fc->intra_ext_tx_cdf[i][j], av1_ext_tx_inv);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700167 }
168 for (i = TX_4X4; i < EXT_TX_SIZES; ++i) {
Yue Chenba47c842017-08-02 16:07:59 -0700169 av1_cost_tokens_from_cdf(x->inter_tx_type_costs[i], fc->inter_ext_tx_cdf[i],
170 av1_ext_tx_inv);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700171 }
172#endif // CONFIG_EXT_TX
173#if CONFIG_EXT_INTRA
hui sueda3d762016-12-06 16:58:23 -0800174#if CONFIG_INTRA_INTERP
Yaowu Xuc27fc142016-08-22 16:08:15 -0700175 for (i = 0; i < INTRA_FILTERS + 1; ++i)
Yue Chenba47c842017-08-02 16:07:59 -0700176 av1_cost_tokens_from_cdf(x->intra_filter_cost[i], fc->intra_filter_cdf[i],
177 NULL);
hui sueda3d762016-12-06 16:58:23 -0800178#endif // CONFIG_INTRA_INTERP
Yaowu Xuc27fc142016-08-22 16:08:15 -0700179#endif // CONFIG_EXT_INTRA
Debargha Mukherjee5cd2ab92016-09-08 15:15:17 -0700180#if CONFIG_LOOP_RESTORATION
Yue Chenb23d00a2017-07-28 17:01:21 -0700181 av1_cost_tokens(x->switchable_restore_cost, fc->switchable_restore_prob,
Debargha Mukherjee5cd2ab92016-09-08 15:15:17 -0700182 av1_switchable_restore_tree);
183#endif // CONFIG_LOOP_RESTORATION
Yue Chenb23d00a2017-07-28 17:01:21 -0700184
185 if (!frame_is_intra_only(cm)) {
186 for (i = 0; i < NEWMV_MODE_CONTEXTS; ++i) {
Yue Chenba47c842017-08-02 16:07:59 -0700187#if CONFIG_NEW_MULTISYMBOL
188 av1_cost_tokens_from_cdf(x->newmv_mode_cost[i], fc->newmv_cdf[i], NULL);
189#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700190 x->newmv_mode_cost[i][0] = av1_cost_bit(fc->newmv_prob[i], 0);
191 x->newmv_mode_cost[i][1] = av1_cost_bit(fc->newmv_prob[i], 1);
Yue Chenba47c842017-08-02 16:07:59 -0700192#endif
Yue Chenb23d00a2017-07-28 17:01:21 -0700193 }
194
195 for (i = 0; i < ZEROMV_MODE_CONTEXTS; ++i) {
Yue Chenba47c842017-08-02 16:07:59 -0700196#if CONFIG_NEW_MULTISYMBOL
197 av1_cost_tokens_from_cdf(x->zeromv_mode_cost[i], fc->zeromv_cdf[i], NULL);
198#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700199 x->zeromv_mode_cost[i][0] = av1_cost_bit(fc->zeromv_prob[i], 0);
200 x->zeromv_mode_cost[i][1] = av1_cost_bit(fc->zeromv_prob[i], 1);
Yue Chenba47c842017-08-02 16:07:59 -0700201#endif
Yue Chenb23d00a2017-07-28 17:01:21 -0700202 }
203
204 for (i = 0; i < REFMV_MODE_CONTEXTS; ++i) {
Yue Chenba47c842017-08-02 16:07:59 -0700205#if CONFIG_NEW_MULTISYMBOL
206 av1_cost_tokens_from_cdf(x->refmv_mode_cost[i], fc->refmv_cdf[i], NULL);
207#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700208 x->refmv_mode_cost[i][0] = av1_cost_bit(fc->refmv_prob[i], 0);
209 x->refmv_mode_cost[i][1] = av1_cost_bit(fc->refmv_prob[i], 1);
Yue Chenba47c842017-08-02 16:07:59 -0700210#endif
Yue Chenb23d00a2017-07-28 17:01:21 -0700211 }
212
213 for (i = 0; i < DRL_MODE_CONTEXTS; ++i) {
Yue Chenba47c842017-08-02 16:07:59 -0700214#if CONFIG_NEW_MULTISYMBOL
215 av1_cost_tokens_from_cdf(x->drl_mode_cost0[i], fc->drl_cdf[i], NULL);
216#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700217 x->drl_mode_cost0[i][0] = av1_cost_bit(fc->drl_prob[i], 0);
218 x->drl_mode_cost0[i][1] = av1_cost_bit(fc->drl_prob[i], 1);
Yue Chenba47c842017-08-02 16:07:59 -0700219#endif
Yue Chenb23d00a2017-07-28 17:01:21 -0700220 }
221#if CONFIG_EXT_INTER
222 for (i = 0; i < INTER_MODE_CONTEXTS; ++i)
Yue Chenba47c842017-08-02 16:07:59 -0700223 av1_cost_tokens_from_cdf(x->inter_compound_mode_cost[i],
224 fc->inter_compound_mode_cdf[i], NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700225#if CONFIG_COMPOUND_SINGLEREF
226 for (i = 0; i < INTER_MODE_CONTEXTS; ++i)
Yue Chenba47c842017-08-02 16:07:59 -0700227 av1_cost_tokens_from_cdf(x->inter_singleref_comp_mode_cost[i],
228 fc->inter_singleref_comp_mode_cdf[i], NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700229#endif // CONFIG_COMPOUND_SINGLEREF
230#if CONFIG_INTERINTRA
231 for (i = 0; i < BLOCK_SIZE_GROUPS; ++i)
Yue Chenba47c842017-08-02 16:07:59 -0700232 av1_cost_tokens_from_cdf(x->interintra_mode_cost[i],
233 fc->interintra_mode_cdf[i], NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700234#endif // CONFIG_INTERINTRA
235#endif // CONFIG_EXT_INTER
236#if CONFIG_MOTION_VAR || CONFIG_WARPED_MOTION
237 for (i = BLOCK_8X8; i < BLOCK_SIZES_ALL; i++) {
Wei-Ting Lin060f7f22017-08-01 10:26:24 -0700238 av1_cost_tokens_from_cdf(x->motion_mode_cost[i], fc->motion_mode_cdf[i],
239 NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700240 }
241#if CONFIG_MOTION_VAR && CONFIG_WARPED_MOTION
242 for (i = BLOCK_8X8; i < BLOCK_SIZES_ALL; i++) {
Yue Chenba47c842017-08-02 16:07:59 -0700243#if CONFIG_NEW_MULTISYMBOL
244 av1_cost_tokens_from_cdf(x->motion_mode_cost1[i], fc->obmc_cdf[i], NULL);
245#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700246 x->motion_mode_cost1[i][0] = av1_cost_bit(fc->obmc_prob[i], 0);
247 x->motion_mode_cost1[i][1] = av1_cost_bit(fc->obmc_prob[i], 1);
Yue Chenba47c842017-08-02 16:07:59 -0700248#endif
Yue Chenb23d00a2017-07-28 17:01:21 -0700249 }
250#endif // CONFIG_MOTION_VAR && CONFIG_WARPED_MOTION
251#if CONFIG_MOTION_VAR && CONFIG_NCOBMC_ADAPT_WEIGHT
252 for (i = ADAPT_OVERLAP_BLOCK_8X8; i < ADAPT_OVERLAP_BLOCKS; ++i) {
Wei-Ting Lin060f7f22017-08-01 10:26:24 -0700253 av1_cost_tokens_from_cdf(x->ncobmc_mode_cost[i], fc->ncobmc_mode_cdf[i],
254 NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700255 }
256#endif // CONFIG_MOTION_VAR && CONFIG_NCOBMC_ADAPT_WEIGHT
257#endif // CONFIG_MOTION_VAR || CONFIG_WARPED_MOTION
258 }
Yaowu Xuc27fc142016-08-22 16:08:15 -0700259}
260
Yaowu Xuc27fc142016-08-22 16:08:15 -0700261// Values are now correlated to quantizer.
262static int sad_per_bit16lut_8[QINDEX_RANGE];
263static int sad_per_bit4lut_8[QINDEX_RANGE];
264
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200265#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700266static int sad_per_bit16lut_10[QINDEX_RANGE];
267static int sad_per_bit4lut_10[QINDEX_RANGE];
268static int sad_per_bit16lut_12[QINDEX_RANGE];
269static int sad_per_bit4lut_12[QINDEX_RANGE];
270#endif
271
272static void init_me_luts_bd(int *bit16lut, int *bit4lut, int range,
Yaowu Xuf883b422016-08-30 14:01:10 -0700273 aom_bit_depth_t bit_depth) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700274 int i;
275 // Initialize the sad lut tables using a formulaic calculation for now.
276 // This is to make it easier to resolve the impact of experimental changes
277 // to the quantizer tables.
278 for (i = 0; i < range; i++) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700279 const double q = av1_convert_qindex_to_q(i, bit_depth);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700280 bit16lut[i] = (int)(0.0418 * q + 2.4107);
281 bit4lut[i] = (int)(0.063 * q + 2.742);
282 }
283}
284
Yaowu Xuf883b422016-08-30 14:01:10 -0700285void av1_init_me_luts(void) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700286 init_me_luts_bd(sad_per_bit16lut_8, sad_per_bit4lut_8, QINDEX_RANGE,
Yaowu Xuf883b422016-08-30 14:01:10 -0700287 AOM_BITS_8);
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200288#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700289 init_me_luts_bd(sad_per_bit16lut_10, sad_per_bit4lut_10, QINDEX_RANGE,
Yaowu Xuf883b422016-08-30 14:01:10 -0700290 AOM_BITS_10);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700291 init_me_luts_bd(sad_per_bit16lut_12, sad_per_bit4lut_12, QINDEX_RANGE,
Yaowu Xuf883b422016-08-30 14:01:10 -0700292 AOM_BITS_12);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700293#endif
294}
295
296static const int rd_boost_factor[16] = { 64, 32, 32, 32, 24, 16, 12, 12,
297 8, 8, 4, 4, 2, 2, 1, 0 };
298static const int rd_frame_type_factor[FRAME_UPDATE_TYPES] = {
299 128, 144, 128, 128, 144,
300#if CONFIG_EXT_REFS
301 // TODO(zoeliu): To adjust further following factor values.
302 128, 128, 128
303 // TODO(weitinglin): We should investigate if the values should be the same
304 // as the value used by OVERLAY frame
305 ,
Zoe Liue9b15e22017-07-19 15:53:01 -0700306 144 // INTNL_OVERLAY_UPDATE
307#if CONFIG_ALTREF2
308 ,
309 128 // INTNL_ARF_UPDATE
310#endif // CONFIG_ALTREF2
Yaowu Xuc27fc142016-08-22 16:08:15 -0700311#endif // CONFIG_EXT_REFS
312};
313
Yaowu Xuf883b422016-08-30 14:01:10 -0700314int av1_compute_rd_mult(const AV1_COMP *cpi, int qindex) {
315 const int64_t q = av1_dc_quant(qindex, 0, cpi->common.bit_depth);
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200316#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700317 int64_t rdmult = 0;
318 switch (cpi->common.bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700319 case AOM_BITS_8: rdmult = 88 * q * q / 24; break;
320 case AOM_BITS_10: rdmult = ROUND_POWER_OF_TWO(88 * q * q / 24, 4); break;
321 case AOM_BITS_12: rdmult = ROUND_POWER_OF_TWO(88 * q * q / 24, 8); break;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700322 default:
Yaowu Xuf883b422016-08-30 14:01:10 -0700323 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -0700324 return -1;
325 }
326#else
327 int64_t rdmult = 88 * q * q / 24;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200328#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700329 if (cpi->oxcf.pass == 2 && (cpi->common.frame_type != KEY_FRAME)) {
330 const GF_GROUP *const gf_group = &cpi->twopass.gf_group;
331 const FRAME_UPDATE_TYPE frame_type = gf_group->update_type[gf_group->index];
Yaowu Xuf883b422016-08-30 14:01:10 -0700332 const int boost_index = AOMMIN(15, (cpi->rc.gfu_boost / 100));
Yaowu Xuc27fc142016-08-22 16:08:15 -0700333
334 rdmult = (rdmult * rd_frame_type_factor[frame_type]) >> 7;
335 rdmult += ((rdmult * rd_boost_factor[boost_index]) >> 7);
336 }
337 if (rdmult < 1) rdmult = 1;
338 return (int)rdmult;
339}
340
Yaowu Xuf883b422016-08-30 14:01:10 -0700341static int compute_rd_thresh_factor(int qindex, aom_bit_depth_t bit_depth) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700342 double q;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200343#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700344 switch (bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700345 case AOM_BITS_8: q = av1_dc_quant(qindex, 0, AOM_BITS_8) / 4.0; break;
346 case AOM_BITS_10: q = av1_dc_quant(qindex, 0, AOM_BITS_10) / 16.0; break;
347 case AOM_BITS_12: q = av1_dc_quant(qindex, 0, AOM_BITS_12) / 64.0; break;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700348 default:
Yaowu Xuf883b422016-08-30 14:01:10 -0700349 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -0700350 return -1;
351 }
352#else
353 (void)bit_depth;
Yaowu Xuf883b422016-08-30 14:01:10 -0700354 q = av1_dc_quant(qindex, 0, AOM_BITS_8) / 4.0;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200355#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700356 // TODO(debargha): Adjust the function below.
Yaowu Xuf883b422016-08-30 14:01:10 -0700357 return AOMMAX((int)(pow(q, RD_THRESH_POW) * 5.12), 8);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700358}
359
Yaowu Xuf883b422016-08-30 14:01:10 -0700360void av1_initialize_me_consts(const AV1_COMP *cpi, MACROBLOCK *x, int qindex) {
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200361#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700362 switch (cpi->common.bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700363 case AOM_BITS_8:
Yaowu Xuc27fc142016-08-22 16:08:15 -0700364 x->sadperbit16 = sad_per_bit16lut_8[qindex];
365 x->sadperbit4 = sad_per_bit4lut_8[qindex];
366 break;
Yaowu Xuf883b422016-08-30 14:01:10 -0700367 case AOM_BITS_10:
Yaowu Xuc27fc142016-08-22 16:08:15 -0700368 x->sadperbit16 = sad_per_bit16lut_10[qindex];
369 x->sadperbit4 = sad_per_bit4lut_10[qindex];
370 break;
Yaowu Xuf883b422016-08-30 14:01:10 -0700371 case AOM_BITS_12:
Yaowu Xuc27fc142016-08-22 16:08:15 -0700372 x->sadperbit16 = sad_per_bit16lut_12[qindex];
373 x->sadperbit4 = sad_per_bit4lut_12[qindex];
374 break;
375 default:
Yaowu Xuf883b422016-08-30 14:01:10 -0700376 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -0700377 }
378#else
379 (void)cpi;
380 x->sadperbit16 = sad_per_bit16lut_8[qindex];
381 x->sadperbit4 = sad_per_bit4lut_8[qindex];
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200382#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700383}
384
Yaowu Xuf883b422016-08-30 14:01:10 -0700385static void set_block_thresholds(const AV1_COMMON *cm, RD_OPT *rd) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700386 int i, bsize, segment_id;
387
388 for (segment_id = 0; segment_id < MAX_SEGMENTS; ++segment_id) {
389 const int qindex =
Yaowu Xuf883b422016-08-30 14:01:10 -0700390 clamp(av1_get_qindex(&cm->seg, segment_id, cm->base_qindex) +
Yaowu Xuc27fc142016-08-22 16:08:15 -0700391 cm->y_dc_delta_q,
392 0, MAXQ);
393 const int q = compute_rd_thresh_factor(qindex, cm->bit_depth);
394
Rupert Swarbrick93c39e92017-07-12 11:11:02 +0100395 for (bsize = 0; bsize < BLOCK_SIZES_ALL; ++bsize) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700396 // Threshold here seems unnecessarily harsh but fine given actual
397 // range of values used for cpi->sf.thresh_mult[].
398 const int t = q * rd_thresh_block_size_factor[bsize];
399 const int thresh_max = INT_MAX / t;
400
Jingning Han9104bed2016-12-14 09:38:00 -0800401#if CONFIG_CB4X4
402 for (i = 0; i < MAX_MODES; ++i)
403 rd->threshes[segment_id][bsize][i] = rd->thresh_mult[i] < thresh_max
404 ? rd->thresh_mult[i] * t / 4
405 : INT_MAX;
406#else
Yaowu Xuc27fc142016-08-22 16:08:15 -0700407 if (bsize >= BLOCK_8X8) {
408 for (i = 0; i < MAX_MODES; ++i)
409 rd->threshes[segment_id][bsize][i] = rd->thresh_mult[i] < thresh_max
410 ? rd->thresh_mult[i] * t / 4
411 : INT_MAX;
412 } else {
413 for (i = 0; i < MAX_REFS; ++i)
414 rd->threshes[segment_id][bsize][i] =
415 rd->thresh_mult_sub8x8[i] < thresh_max
416 ? rd->thresh_mult_sub8x8[i] * t / 4
417 : INT_MAX;
418 }
Jingning Han9104bed2016-12-14 09:38:00 -0800419#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700420 }
421 }
422}
423
Yaowu Xu4306b6e2016-09-27 12:55:32 -0700424void av1_set_mvcost(MACROBLOCK *x, MV_REFERENCE_FRAME ref_frame, int ref,
425 int ref_mv_idx) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700426 MB_MODE_INFO_EXT *mbmi_ext = x->mbmi_ext;
Yaowu Xu4306b6e2016-09-27 12:55:32 -0700427 int8_t rf_type = av1_ref_frame_type(x->e_mbd.mi[0]->mbmi.ref_frame);
428 int nmv_ctx = av1_nmv_ctx(mbmi_ext->ref_mv_count[rf_type],
429 mbmi_ext->ref_mv_stack[rf_type], ref, ref_mv_idx);
430 (void)ref_frame;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700431 x->mvcost = x->mv_cost_stack[nmv_ctx];
432 x->nmvjointcost = x->nmv_vec_cost[nmv_ctx];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700433}
Yaowu Xuc27fc142016-08-22 16:08:15 -0700434
hui subd57abe2017-07-24 18:14:03 -0700435void av1_fill_token_costs_from_cdf(av1_coeff_cost *cost,
436 coeff_cdf_model (*cdf)[PLANE_TYPES]) {
hui suc0cf71d2017-07-20 16:38:50 -0700437 for (int tx = 0; tx < TX_SIZES; ++tx) {
438 for (int pt = 0; pt < PLANE_TYPES; ++pt) {
439 for (int rt = 0; rt < REF_TYPES; ++rt) {
440 for (int band = 0; band < COEF_BANDS; ++band) {
441 for (int ctx = 0; ctx < BAND_COEFF_CONTEXTS(band); ++ctx) {
442 av1_cost_tokens_from_cdf(cost[tx][pt][rt][band][ctx],
443 cdf[tx][pt][rt][band][ctx], NULL);
444 }
445 }
446 }
447 }
448 }
449}
450
Yaowu Xuf883b422016-08-30 14:01:10 -0700451void av1_initialize_rd_consts(AV1_COMP *cpi) {
452 AV1_COMMON *const cm = &cpi->common;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700453 MACROBLOCK *const x = &cpi->td.mb;
454 RD_OPT *const rd = &cpi->rd;
Jingning Hanb3b034d2016-11-29 17:57:14 -0800455 int nmv_ctx;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700456
Yaowu Xuf883b422016-08-30 14:01:10 -0700457 aom_clear_system_state();
Yaowu Xuc27fc142016-08-22 16:08:15 -0700458
Yaowu Xuf883b422016-08-30 14:01:10 -0700459 rd->RDMULT = av1_compute_rd_mult(cpi, cm->base_qindex + cm->y_dc_delta_q);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700460
461 set_error_per_bit(x, rd->RDMULT);
462
463 set_block_thresholds(cm, rd);
464
Jingning Hanb3b034d2016-11-29 17:57:14 -0800465 for (nmv_ctx = 0; nmv_ctx < NMV_CONTEXTS; ++nmv_ctx) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700466 av1_build_nmv_cost_table(
Jingning Hanb3b034d2016-11-29 17:57:14 -0800467 x->nmv_vec_cost[nmv_ctx],
468 cm->allow_high_precision_mv ? x->nmvcost_hp[nmv_ctx]
469 : x->nmvcost[nmv_ctx],
470 &cm->fc->nmvc[nmv_ctx], cm->allow_high_precision_mv);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700471 }
Jingning Hanb3b034d2016-11-29 17:57:14 -0800472 x->mvcost = x->mv_cost_stack[0];
473 x->nmvjointcost = x->nmv_vec_cost[0];
Jingning Hanb3b034d2016-11-29 17:57:14 -0800474
Alex Conversed5d9b6c2017-05-23 15:23:45 -0700475#if CONFIG_INTRABC
476 if (frame_is_intra_only(cm) && cm->allow_screen_content_tools &&
477 cpi->oxcf.pass != 1) {
478 av1_build_nmv_cost_table(
479 x->nmv_vec_cost[0],
480 cm->allow_high_precision_mv ? x->nmvcost_hp[0] : x->nmvcost[0],
481 &cm->fc->ndvc, MV_SUBPEL_NONE);
482 }
483#endif
484
Yue Chenb23d00a2017-07-28 17:01:21 -0700485#if CONFIG_GLOBAL_MOTION
hui subd57abe2017-07-24 18:14:03 -0700486 if (cpi->oxcf.pass != 1) {
Zoe Liubc030ee2017-07-31 15:20:46 -0700487 for (int i = 0; i < TRANS_TYPES; ++i)
Yue Chenb23d00a2017-07-28 17:01:21 -0700488 cpi->gmtype_cost[i] = (1 + (i > 0 ? GLOBAL_TYPE_BITS : 0))
489 << AV1_PROB_COST_SHIFT;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700490 }
hui subd57abe2017-07-24 18:14:03 -0700491#endif // CONFIG_GLOBAL_MOTION
Yaowu Xuc27fc142016-08-22 16:08:15 -0700492}
493
494static void model_rd_norm(int xsq_q10, int *r_q10, int *d_q10) {
495 // NOTE: The tables below must be of the same size.
496
497 // The functions described below are sampled at the four most significant
498 // bits of x^2 + 8 / 256.
499
500 // Normalized rate:
501 // This table models the rate for a Laplacian source with given variance
502 // when quantized with a uniform quantizer with given stepsize. The
503 // closed form expression is:
504 // Rn(x) = H(sqrt(r)) + sqrt(r)*[1 + H(r)/(1 - r)],
505 // where r = exp(-sqrt(2) * x) and x = qpstep / sqrt(variance),
506 // and H(x) is the binary entropy function.
507 static const int rate_tab_q10[] = {
508 65536, 6086, 5574, 5275, 5063, 4899, 4764, 4651, 4553, 4389, 4255, 4142,
509 4044, 3958, 3881, 3811, 3748, 3635, 3538, 3453, 3376, 3307, 3244, 3186,
510 3133, 3037, 2952, 2877, 2809, 2747, 2690, 2638, 2589, 2501, 2423, 2353,
511 2290, 2232, 2179, 2130, 2084, 2001, 1928, 1862, 1802, 1748, 1698, 1651,
512 1608, 1530, 1460, 1398, 1342, 1290, 1243, 1199, 1159, 1086, 1021, 963,
513 911, 864, 821, 781, 745, 680, 623, 574, 530, 490, 455, 424,
514 395, 345, 304, 269, 239, 213, 190, 171, 154, 126, 104, 87,
515 73, 61, 52, 44, 38, 28, 21, 16, 12, 10, 8, 6,
516 5, 3, 2, 1, 1, 1, 0, 0,
517 };
518 // Normalized distortion:
519 // This table models the normalized distortion for a Laplacian source
520 // with given variance when quantized with a uniform quantizer
521 // with given stepsize. The closed form expression is:
522 // Dn(x) = 1 - 1/sqrt(2) * x / sinh(x/sqrt(2))
523 // where x = qpstep / sqrt(variance).
524 // Note the actual distortion is Dn * variance.
525 static const int dist_tab_q10[] = {
526 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 4, 5,
527 5, 6, 7, 7, 8, 9, 11, 12, 13, 15, 16, 17,
528 18, 21, 24, 26, 29, 31, 34, 36, 39, 44, 49, 54,
529 59, 64, 69, 73, 78, 88, 97, 106, 115, 124, 133, 142,
530 151, 167, 184, 200, 215, 231, 245, 260, 274, 301, 327, 351,
531 375, 397, 418, 439, 458, 495, 528, 559, 587, 613, 637, 659,
532 680, 717, 749, 777, 801, 823, 842, 859, 874, 899, 919, 936,
533 949, 960, 969, 977, 983, 994, 1001, 1006, 1010, 1013, 1015, 1017,
534 1018, 1020, 1022, 1022, 1023, 1023, 1023, 1024,
535 };
536 static const int xsq_iq_q10[] = {
537 0, 4, 8, 12, 16, 20, 24, 28, 32,
538 40, 48, 56, 64, 72, 80, 88, 96, 112,
539 128, 144, 160, 176, 192, 208, 224, 256, 288,
540 320, 352, 384, 416, 448, 480, 544, 608, 672,
541 736, 800, 864, 928, 992, 1120, 1248, 1376, 1504,
542 1632, 1760, 1888, 2016, 2272, 2528, 2784, 3040, 3296,
543 3552, 3808, 4064, 4576, 5088, 5600, 6112, 6624, 7136,
544 7648, 8160, 9184, 10208, 11232, 12256, 13280, 14304, 15328,
545 16352, 18400, 20448, 22496, 24544, 26592, 28640, 30688, 32736,
546 36832, 40928, 45024, 49120, 53216, 57312, 61408, 65504, 73696,
547 81888, 90080, 98272, 106464, 114656, 122848, 131040, 147424, 163808,
548 180192, 196576, 212960, 229344, 245728,
549 };
550 const int tmp = (xsq_q10 >> 2) + 8;
551 const int k = get_msb(tmp) - 3;
552 const int xq = (k << 3) + ((tmp >> k) & 0x7);
553 const int one_q10 = 1 << 10;
554 const int a_q10 = ((xsq_q10 - xsq_iq_q10[xq]) << 10) >> (2 + k);
555 const int b_q10 = one_q10 - a_q10;
556 *r_q10 = (rate_tab_q10[xq] * b_q10 + rate_tab_q10[xq + 1] * a_q10) >> 10;
557 *d_q10 = (dist_tab_q10[xq] * b_q10 + dist_tab_q10[xq + 1] * a_q10) >> 10;
558}
559
Yaowu Xuf883b422016-08-30 14:01:10 -0700560void av1_model_rd_from_var_lapndz(int64_t var, unsigned int n_log2,
561 unsigned int qstep, int *rate,
562 int64_t *dist) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700563 // This function models the rate and distortion for a Laplacian
564 // source with given variance when quantized with a uniform quantizer
565 // with given stepsize. The closed form expressions are in:
566 // Hang and Chen, "Source Model for transform video coder and its
567 // application - Part I: Fundamental Theory", IEEE Trans. Circ.
568 // Sys. for Video Tech., April 1997.
569 if (var == 0) {
570 *rate = 0;
571 *dist = 0;
572 } else {
573 int d_q10, r_q10;
574 static const uint32_t MAX_XSQ_Q10 = 245727;
575 const uint64_t xsq_q10_64 =
576 (((uint64_t)qstep * qstep << (n_log2 + 10)) + (var >> 1)) / var;
Yaowu Xuf883b422016-08-30 14:01:10 -0700577 const int xsq_q10 = (int)AOMMIN(xsq_q10_64, MAX_XSQ_Q10);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700578 model_rd_norm(xsq_q10, &r_q10, &d_q10);
Yaowu Xuf883b422016-08-30 14:01:10 -0700579 *rate = ROUND_POWER_OF_TWO(r_q10 << n_log2, 10 - AV1_PROB_COST_SHIFT);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700580 *dist = (var * (int64_t)d_q10 + 512) >> 10;
581 }
582}
583
584static void get_entropy_contexts_plane(
585 BLOCK_SIZE plane_bsize, TX_SIZE tx_size, const struct macroblockd_plane *pd,
586 ENTROPY_CONTEXT t_above[2 * MAX_MIB_SIZE],
587 ENTROPY_CONTEXT t_left[2 * MAX_MIB_SIZE]) {
Jingning Han9eef06d2016-12-05 12:39:34 -0800588 const int num_4x4_w = block_size_wide[plane_bsize] >> tx_size_wide_log2[0];
589 const int num_4x4_h = block_size_high[plane_bsize] >> tx_size_high_log2[0];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700590 const ENTROPY_CONTEXT *const above = pd->above_context;
591 const ENTROPY_CONTEXT *const left = pd->left_context;
592
Angie Chiangfb42c7f2017-06-01 18:36:18 -0700593#if CONFIG_LV_MAP
594 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
595 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
596 return;
597#endif // CONFIG_LV_MAP
598
Yaowu Xuc27fc142016-08-22 16:08:15 -0700599 int i;
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800600
Timothy B. Terriberryfe67ed62017-04-26 16:53:47 -0700601#if CONFIG_CHROMA_2X2
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800602 switch (tx_size) {
Jingning Han39772c12016-12-01 12:47:05 -0800603 case TX_2X2:
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800604 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
605 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
606 break;
607 case TX_4X4:
608 for (i = 0; i < num_4x4_w; i += 2)
609 t_above[i] = !!*(const uint16_t *)&above[i];
610 for (i = 0; i < num_4x4_h; i += 2)
611 t_left[i] = !!*(const uint16_t *)&left[i];
612 break;
613 case TX_8X8:
614 for (i = 0; i < num_4x4_w; i += 4)
615 t_above[i] = !!*(const uint32_t *)&above[i];
616 for (i = 0; i < num_4x4_h; i += 4)
617 t_left[i] = !!*(const uint32_t *)&left[i];
618 break;
619 case TX_16X16:
620 for (i = 0; i < num_4x4_w; i += 8)
621 t_above[i] = !!*(const uint64_t *)&above[i];
622 for (i = 0; i < num_4x4_h; i += 8)
623 t_left[i] = !!*(const uint64_t *)&left[i];
624 break;
625 case TX_32X32:
626 for (i = 0; i < num_4x4_w; i += 16)
627 t_above[i] =
628 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
629 for (i = 0; i < num_4x4_h; i += 16)
630 t_left[i] =
631 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
632 break;
Urvang Joshi4c6d4362017-05-11 12:35:46 -0700633#if CONFIG_TX64X64
634 case TX_64X64:
635 for (i = 0; i < num_4x4_w; i += 32)
636 t_above[i] =
637 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8] |
638 *(const uint64_t *)&above[i + 16] |
639 *(const uint64_t *)&above[i + 24]);
640 for (i = 0; i < num_4x4_h; i += 32)
641 t_left[i] =
642 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8] |
643 *(const uint64_t *)&left[i + 16] |
644 *(const uint64_t *)&left[i + 24]);
645 break;
646#endif // CONFIG_TX64X64
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800647 case TX_4X8:
648 for (i = 0; i < num_4x4_w; i += 2)
649 t_above[i] = !!*(const uint16_t *)&above[i];
650 for (i = 0; i < num_4x4_h; i += 4)
651 t_left[i] = !!*(const uint32_t *)&left[i];
652 break;
653 case TX_8X4:
654 for (i = 0; i < num_4x4_w; i += 4)
655 t_above[i] = !!*(const uint32_t *)&above[i];
656 for (i = 0; i < num_4x4_h; i += 2)
657 t_left[i] = !!*(const uint16_t *)&left[i];
658 break;
659 case TX_8X16:
660 for (i = 0; i < num_4x4_w; i += 4)
661 t_above[i] = !!*(const uint32_t *)&above[i];
662 for (i = 0; i < num_4x4_h; i += 8)
663 t_left[i] = !!*(const uint64_t *)&left[i];
664 break;
665 case TX_16X8:
666 for (i = 0; i < num_4x4_w; i += 8)
667 t_above[i] = !!*(const uint64_t *)&above[i];
668 for (i = 0; i < num_4x4_h; i += 4)
669 t_left[i] = !!*(const uint32_t *)&left[i];
670 break;
671 case TX_16X32:
672 for (i = 0; i < num_4x4_w; i += 8)
673 t_above[i] = !!*(const uint64_t *)&above[i];
674 for (i = 0; i < num_4x4_h; i += 16)
675 t_left[i] =
676 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
677 break;
678 case TX_32X16:
679 for (i = 0; i < num_4x4_w; i += 16)
680 t_above[i] =
681 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
682 for (i = 0; i < num_4x4_h; i += 8)
683 t_left[i] = !!*(const uint64_t *)&left[i];
Jingning Han0f6a60a2017-01-20 09:25:40 -0800684 break;
Yue Chend6bdd462017-07-19 16:05:43 -0700685#if CONFIG_RECT_TX_EXT && (CONFIG_EXT_TX || CONFIG_VAR_TX)
Yue Chen56e226e2017-05-02 16:21:40 -0700686 case TX_4X16:
687 for (i = 0; i < num_4x4_w; i += 2)
688 t_above[i] = !!*(const uint16_t *)&above[i];
689 for (i = 0; i < num_4x4_h; i += 8)
690 t_left[i] = !!*(const uint64_t *)&left[i];
691 break;
692 case TX_16X4:
693 for (i = 0; i < num_4x4_w; i += 8)
694 t_above[i] = !!*(const uint64_t *)&above[i];
695 for (i = 0; i < num_4x4_h; i += 2)
696 t_left[i] = !!*(const uint16_t *)&left[i];
697 break;
698 case TX_8X32:
699 for (i = 0; i < num_4x4_w; i += 4)
700 t_above[i] = !!*(const uint32_t *)&above[i];
701 for (i = 0; i < num_4x4_h; i += 16)
702 t_left[i] =
703 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
704 break;
705 case TX_32X8:
706 for (i = 0; i < num_4x4_w; i += 16)
707 t_above[i] =
708 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
709 for (i = 0; i < num_4x4_h; i += 4)
710 t_left[i] = !!*(const uint32_t *)&left[i];
711 break;
Yue Chend6bdd462017-07-19 16:05:43 -0700712#endif
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800713
714 default: assert(0 && "Invalid transform size."); break;
715 }
716 return;
Timothy B. Terriberryfe67ed62017-04-26 16:53:47 -0700717#endif // CONFIG_CHROMA_2X2
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800718
719 switch (tx_size) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700720 case TX_4X4:
721 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
722 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
723 break;
724 case TX_8X8:
725 for (i = 0; i < num_4x4_w; i += 2)
726 t_above[i] = !!*(const uint16_t *)&above[i];
727 for (i = 0; i < num_4x4_h; i += 2)
728 t_left[i] = !!*(const uint16_t *)&left[i];
729 break;
730 case TX_16X16:
731 for (i = 0; i < num_4x4_w; i += 4)
732 t_above[i] = !!*(const uint32_t *)&above[i];
733 for (i = 0; i < num_4x4_h; i += 4)
734 t_left[i] = !!*(const uint32_t *)&left[i];
735 break;
736 case TX_32X32:
737 for (i = 0; i < num_4x4_w; i += 8)
738 t_above[i] = !!*(const uint64_t *)&above[i];
739 for (i = 0; i < num_4x4_h; i += 8)
740 t_left[i] = !!*(const uint64_t *)&left[i];
741 break;
Debargha Mukherjee153e1f82016-11-17 09:59:14 -0800742#if CONFIG_TX64X64
743 case TX_64X64:
744 for (i = 0; i < num_4x4_w; i += 16)
745 t_above[i] =
746 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
747 for (i = 0; i < num_4x4_h; i += 16)
Debargha Mukherjee932cf692016-11-18 08:14:10 -0800748 t_left[i] =
749 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
Debargha Mukherjee153e1f82016-11-17 09:59:14 -0800750 break;
751#endif // CONFIG_TX64X64
Yaowu Xuc27fc142016-08-22 16:08:15 -0700752 case TX_4X8:
753 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
754 for (i = 0; i < num_4x4_h; i += 2)
755 t_left[i] = !!*(const uint16_t *)&left[i];
756 break;
757 case TX_8X4:
758 for (i = 0; i < num_4x4_w; i += 2)
759 t_above[i] = !!*(const uint16_t *)&above[i];
760 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
761 break;
762 case TX_8X16:
763 for (i = 0; i < num_4x4_w; i += 2)
764 t_above[i] = !!*(const uint16_t *)&above[i];
765 for (i = 0; i < num_4x4_h; i += 4)
766 t_left[i] = !!*(const uint32_t *)&left[i];
767 break;
768 case TX_16X8:
769 for (i = 0; i < num_4x4_w; i += 4)
770 t_above[i] = !!*(const uint32_t *)&above[i];
771 for (i = 0; i < num_4x4_h; i += 2)
772 t_left[i] = !!*(const uint16_t *)&left[i];
773 break;
774 case TX_16X32:
775 for (i = 0; i < num_4x4_w; i += 4)
776 t_above[i] = !!*(const uint32_t *)&above[i];
777 for (i = 0; i < num_4x4_h; i += 8)
778 t_left[i] = !!*(const uint64_t *)&left[i];
779 break;
780 case TX_32X16:
781 for (i = 0; i < num_4x4_w; i += 8)
782 t_above[i] = !!*(const uint64_t *)&above[i];
783 for (i = 0; i < num_4x4_h; i += 4)
784 t_left[i] = !!*(const uint32_t *)&left[i];
785 break;
Yue Chend6bdd462017-07-19 16:05:43 -0700786#if CONFIG_RECT_TX_EXT && (CONFIG_EXT_TX || CONFIG_VAR_TX)
Yue Chen56e226e2017-05-02 16:21:40 -0700787 case TX_4X16:
788 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
789 for (i = 0; i < num_4x4_h; i += 4)
790 t_left[i] = !!*(const uint32_t *)&left[i];
791 break;
792 case TX_16X4:
793 for (i = 0; i < num_4x4_w; i += 4)
794 t_above[i] = !!*(const uint32_t *)&above[i];
795 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
796 break;
797 case TX_8X32:
798 for (i = 0; i < num_4x4_w; i += 2)
799 t_above[i] = !!*(const uint16_t *)&above[i];
800 for (i = 0; i < num_4x4_h; i += 8)
801 t_left[i] = !!*(const uint64_t *)&left[i];
802 break;
803 case TX_32X8:
804 for (i = 0; i < num_4x4_w; i += 8)
805 t_above[i] = !!*(const uint64_t *)&above[i];
806 for (i = 0; i < num_4x4_h; i += 2)
807 t_left[i] = !!*(const uint16_t *)&left[i];
808 break;
Yue Chend6bdd462017-07-19 16:05:43 -0700809#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700810 default: assert(0 && "Invalid transform size."); break;
811 }
812}
813
Yaowu Xuf883b422016-08-30 14:01:10 -0700814void av1_get_entropy_contexts(BLOCK_SIZE bsize, TX_SIZE tx_size,
815 const struct macroblockd_plane *pd,
816 ENTROPY_CONTEXT t_above[2 * MAX_MIB_SIZE],
817 ENTROPY_CONTEXT t_left[2 * MAX_MIB_SIZE]) {
Timothy B. Terriberry81ec2612017-04-26 16:53:47 -0700818#if CONFIG_CHROMA_SUB8X8
Timothy B. Terriberry32b8d462017-05-22 12:02:56 -0700819 const BLOCK_SIZE plane_bsize =
820 AOMMAX(BLOCK_4X4, get_plane_block_size(bsize, pd));
821#else
Yaowu Xuc27fc142016-08-22 16:08:15 -0700822 const BLOCK_SIZE plane_bsize = get_plane_block_size(bsize, pd);
Timothy B. Terriberry32b8d462017-05-22 12:02:56 -0700823#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700824 get_entropy_contexts_plane(plane_bsize, tx_size, pd, t_above, t_left);
825}
826
Urvang Joshi52648442016-10-13 17:27:51 -0700827void av1_mv_pred(const AV1_COMP *cpi, MACROBLOCK *x, uint8_t *ref_y_buffer,
Yaowu Xuf883b422016-08-30 14:01:10 -0700828 int ref_y_stride, int ref_frame, BLOCK_SIZE block_size) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700829 int i;
830 int zero_seen = 0;
831 int best_index = 0;
832 int best_sad = INT_MAX;
833 int this_sad = INT_MAX;
834 int max_mv = 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700835 uint8_t *src_y_ptr = x->plane[0].src.buf;
836 uint8_t *ref_y_ptr;
Thomas Daede07438572017-05-10 11:22:33 -0700837 MV pred_mv[MAX_MV_REF_CANDIDATES + 1];
Debargha Mukherjeed80d63f2017-05-17 15:53:27 -0700838 int num_mv_refs = 0;
839
840 pred_mv[num_mv_refs++] = x->mbmi_ext->ref_mvs[ref_frame][0].as_mv;
841 if (x->mbmi_ext->ref_mvs[ref_frame][0].as_int !=
842 x->mbmi_ext->ref_mvs[ref_frame][1].as_int) {
843 pred_mv[num_mv_refs++] = x->mbmi_ext->ref_mvs[ref_frame][1].as_mv;
Thomas Daede07438572017-05-10 11:22:33 -0700844 }
Debargha Mukherjeed80d63f2017-05-17 15:53:27 -0700845 if (cpi->sf.adaptive_motion_search && block_size < x->max_partition_size)
846 pred_mv[num_mv_refs++] = x->pred_mv[ref_frame];
847
Yaowu Xuc27fc142016-08-22 16:08:15 -0700848 assert(num_mv_refs <= (int)(sizeof(pred_mv) / sizeof(pred_mv[0])));
Debargha Mukherjeed80d63f2017-05-17 15:53:27 -0700849
Yaowu Xuc27fc142016-08-22 16:08:15 -0700850 // Get the sad for each candidate reference mv.
851 for (i = 0; i < num_mv_refs; ++i) {
852 const MV *this_mv = &pred_mv[i];
853 int fp_row, fp_col;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700854 fp_row = (this_mv->row + 3 + (this_mv->row >= 0)) >> 3;
855 fp_col = (this_mv->col + 3 + (this_mv->col >= 0)) >> 3;
Yaowu Xuf883b422016-08-30 14:01:10 -0700856 max_mv = AOMMAX(max_mv, AOMMAX(abs(this_mv->row), abs(this_mv->col)) >> 3);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700857
858 if (fp_row == 0 && fp_col == 0 && zero_seen) continue;
859 zero_seen |= (fp_row == 0 && fp_col == 0);
860
861 ref_y_ptr = &ref_y_buffer[ref_y_stride * fp_row + fp_col];
862 // Find sad for current vector.
863 this_sad = cpi->fn_ptr[block_size].sdf(src_y_ptr, x->plane[0].src.stride,
864 ref_y_ptr, ref_y_stride);
865 // Note if it is the best so far.
866 if (this_sad < best_sad) {
867 best_sad = this_sad;
868 best_index = i;
869 }
870 }
871
872 // Note the index of the mv that worked best in the reference list.
873 x->mv_best_ref_index[ref_frame] = best_index;
874 x->max_mv_context[ref_frame] = max_mv;
875 x->pred_mv_sad[ref_frame] = best_sad;
876}
877
Yaowu Xuf883b422016-08-30 14:01:10 -0700878void av1_setup_pred_block(const MACROBLOCKD *xd,
879 struct buf_2d dst[MAX_MB_PLANE],
880 const YV12_BUFFER_CONFIG *src, int mi_row, int mi_col,
881 const struct scale_factors *scale,
882 const struct scale_factors *scale_uv) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700883 int i;
884
885 dst[0].buf = src->y_buffer;
886 dst[0].stride = src->y_stride;
887 dst[1].buf = src->u_buffer;
888 dst[2].buf = src->v_buffer;
889 dst[1].stride = dst[2].stride = src->uv_stride;
890
891 for (i = 0; i < MAX_MB_PLANE; ++i) {
Jingning Han91d9a792017-04-18 12:01:52 -0700892 setup_pred_plane(dst + i, xd->mi[0]->mbmi.sb_type, dst[i].buf,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700893 i ? src->uv_crop_width : src->y_crop_width,
894 i ? src->uv_crop_height : src->y_crop_height,
895 dst[i].stride, mi_row, mi_col, i ? scale_uv : scale,
896 xd->plane[i].subsampling_x, xd->plane[i].subsampling_y);
897 }
898}
899
Yaowu Xuf883b422016-08-30 14:01:10 -0700900int av1_raster_block_offset(BLOCK_SIZE plane_bsize, int raster_block,
901 int stride) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700902 const int bw = b_width_log2_lookup[plane_bsize];
903 const int y = 4 * (raster_block >> bw);
904 const int x = 4 * (raster_block & ((1 << bw) - 1));
905 return y * stride + x;
906}
907
Yaowu Xuf883b422016-08-30 14:01:10 -0700908int16_t *av1_raster_block_offset_int16(BLOCK_SIZE plane_bsize, int raster_block,
909 int16_t *base) {
Jingning Hanae5cfde2016-11-30 12:01:44 -0800910 const int stride = block_size_wide[plane_bsize];
Yaowu Xuf883b422016-08-30 14:01:10 -0700911 return base + av1_raster_block_offset(plane_bsize, raster_block, stride);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700912}
913
Yaowu Xuf883b422016-08-30 14:01:10 -0700914YV12_BUFFER_CONFIG *av1_get_scaled_ref_frame(const AV1_COMP *cpi,
915 int ref_frame) {
916 const AV1_COMMON *const cm = &cpi->common;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700917 const int scaled_idx = cpi->scaled_ref_idx[ref_frame - 1];
918 const int ref_idx = get_ref_frame_buf_idx(cpi, ref_frame);
919 return (scaled_idx != ref_idx && scaled_idx != INVALID_IDX)
920 ? &cm->buffer_pool->frame_bufs[scaled_idx].buf
921 : NULL;
922}
923
924#if CONFIG_DUAL_FILTER
Yue Chenb23d00a2017-07-28 17:01:21 -0700925int av1_get_switchable_rate(const AV1_COMMON *const cm, MACROBLOCK *x,
926 const MACROBLOCKD *xd) {
Angie Chiang75c22092016-10-25 12:19:16 -0700927 if (cm->interp_filter == SWITCHABLE) {
928 const MB_MODE_INFO *const mbmi = &xd->mi[0]->mbmi;
929 int inter_filter_cost = 0;
930 int dir;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700931
Angie Chiang75c22092016-10-25 12:19:16 -0700932 for (dir = 0; dir < 2; ++dir) {
933 if (has_subpel_mv_component(xd->mi[0], xd, dir) ||
934 (mbmi->ref_frame[1] > INTRA_FRAME &&
935 has_subpel_mv_component(xd->mi[0], xd, dir + 2))) {
936 const int ctx = av1_get_pred_context_switchable_interp(xd, dir);
937 inter_filter_cost +=
Yue Chenb23d00a2017-07-28 17:01:21 -0700938 x->switchable_interp_costs[ctx][mbmi->interp_filter[dir]];
Angie Chiang75c22092016-10-25 12:19:16 -0700939 }
Yaowu Xuc27fc142016-08-22 16:08:15 -0700940 }
Angie Chiang75c22092016-10-25 12:19:16 -0700941 return SWITCHABLE_INTERP_RATE_FACTOR * inter_filter_cost;
942 } else {
943 return 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700944 }
Yaowu Xuc27fc142016-08-22 16:08:15 -0700945}
946#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700947int av1_get_switchable_rate(const AV1_COMMON *const cm, MACROBLOCK *x,
948 const MACROBLOCKD *xd) {
Angie Chiang75c22092016-10-25 12:19:16 -0700949 if (cm->interp_filter == SWITCHABLE) {
Angie Chiang1733f6b2017-01-05 09:52:20 -0800950 const MB_MODE_INFO *const mbmi = &xd->mi[0]->mbmi;
951 const int ctx = av1_get_pred_context_switchable_interp(xd);
952 return SWITCHABLE_INTERP_RATE_FACTOR *
Yue Chenb23d00a2017-07-28 17:01:21 -0700953 x->switchable_interp_costs[ctx][mbmi->interp_filter];
Angie Chiang75c22092016-10-25 12:19:16 -0700954 }
955 return 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700956}
957#endif
958
Yaowu Xuf883b422016-08-30 14:01:10 -0700959void av1_set_rd_speed_thresholds(AV1_COMP *cpi) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700960 int i;
961 RD_OPT *const rd = &cpi->rd;
962 SPEED_FEATURES *const sf = &cpi->sf;
963
964 // Set baseline threshold values.
Thomas Daede6eca8352017-03-17 14:14:12 -0700965 for (i = 0; i < MAX_MODES; ++i) rd->thresh_mult[i] = cpi->oxcf.mode == 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700966
967 if (sf->adaptive_rd_thresh) {
968 rd->thresh_mult[THR_NEARESTMV] = 300;
969#if CONFIG_EXT_REFS
970 rd->thresh_mult[THR_NEARESTL2] = 300;
971 rd->thresh_mult[THR_NEARESTL3] = 300;
972 rd->thresh_mult[THR_NEARESTB] = 300;
Zoe Liue9b15e22017-07-19 15:53:01 -0700973#if CONFIG_ALTREF2
974 rd->thresh_mult[THR_NEARESTA2] = 300;
975#endif // CONFIG_ALTREF2
Yaowu Xuc27fc142016-08-22 16:08:15 -0700976#endif // CONFIG_EXT_REFS
977 rd->thresh_mult[THR_NEARESTA] = 300;
978 rd->thresh_mult[THR_NEARESTG] = 300;
979 } else {
980 rd->thresh_mult[THR_NEARESTMV] = 0;
981#if CONFIG_EXT_REFS
982 rd->thresh_mult[THR_NEARESTL2] = 0;
983 rd->thresh_mult[THR_NEARESTL3] = 0;
984 rd->thresh_mult[THR_NEARESTB] = 0;
Zoe Liue9b15e22017-07-19 15:53:01 -0700985#if CONFIG_ALTREF2
986 rd->thresh_mult[THR_NEARESTA2] = 0;
987#endif // CONFIG_ALTREF2
Yaowu Xuc27fc142016-08-22 16:08:15 -0700988#endif // CONFIG_EXT_REFS
989 rd->thresh_mult[THR_NEARESTA] = 0;
990 rd->thresh_mult[THR_NEARESTG] = 0;
991 }
992
993 rd->thresh_mult[THR_DC] += 1000;
994
995 rd->thresh_mult[THR_NEWMV] += 1000;
996#if CONFIG_EXT_REFS
997 rd->thresh_mult[THR_NEWL2] += 1000;
998 rd->thresh_mult[THR_NEWL3] += 1000;
999 rd->thresh_mult[THR_NEWB] += 1000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001000#if CONFIG_ALTREF2
1001 rd->thresh_mult[THR_NEWA2] = 1000;
1002#endif // CONFIG_ALTREF2
Yaowu Xuc27fc142016-08-22 16:08:15 -07001003#endif // CONFIG_EXT_REFS
1004 rd->thresh_mult[THR_NEWA] += 1000;
1005 rd->thresh_mult[THR_NEWG] += 1000;
1006
1007 rd->thresh_mult[THR_NEARMV] += 1000;
1008#if CONFIG_EXT_REFS
1009 rd->thresh_mult[THR_NEARL2] += 1000;
1010 rd->thresh_mult[THR_NEARL3] += 1000;
1011 rd->thresh_mult[THR_NEARB] += 1000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001012#if CONFIG_ALTREF2
1013 rd->thresh_mult[THR_NEARA2] = 1000;
1014#endif // CONFIG_ALTREF2
Yaowu Xuc27fc142016-08-22 16:08:15 -07001015#endif // CONFIG_EXT_REFS
1016 rd->thresh_mult[THR_NEARA] += 1000;
1017 rd->thresh_mult[THR_NEARG] += 1000;
1018
Yaowu Xuc27fc142016-08-22 16:08:15 -07001019 rd->thresh_mult[THR_ZEROMV] += 2000;
1020#if CONFIG_EXT_REFS
1021 rd->thresh_mult[THR_ZEROL2] += 2000;
1022 rd->thresh_mult[THR_ZEROL3] += 2000;
1023 rd->thresh_mult[THR_ZEROB] += 2000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001024#if CONFIG_ALTREF2
1025 rd->thresh_mult[THR_ZEROA2] = 2000;
1026#endif // CONFIG_ALTREF2
Yaowu Xuc27fc142016-08-22 16:08:15 -07001027#endif // CONFIG_EXT_REFS
1028 rd->thresh_mult[THR_ZEROG] += 2000;
1029 rd->thresh_mult[THR_ZEROA] += 2000;
1030
1031 rd->thresh_mult[THR_TM] += 1000;
1032
1033#if CONFIG_EXT_INTER
1034
Zoe Liu85b66462017-04-20 14:28:19 -07001035#if CONFIG_COMPOUND_SINGLEREF
1036 rd->thresh_mult[THR_SR_NEAREST_NEARMV] += 1200;
1037#if CONFIG_EXT_REFS
1038 rd->thresh_mult[THR_SR_NEAREST_NEARL2] += 1200;
1039 rd->thresh_mult[THR_SR_NEAREST_NEARL3] += 1200;
1040 rd->thresh_mult[THR_SR_NEAREST_NEARB] += 1200;
1041#endif // CONFIG_EXT_REFS
1042 rd->thresh_mult[THR_SR_NEAREST_NEARA] += 1200;
1043 rd->thresh_mult[THR_SR_NEAREST_NEARG] += 1200;
1044
1045 /*
1046 rd->thresh_mult[THR_SR_NEAREST_NEWMV] += 1200;
1047#if CONFIG_EXT_REFS
1048 rd->thresh_mult[THR_SR_NEAREST_NEWL2] += 1200;
1049 rd->thresh_mult[THR_SR_NEAREST_NEWL3] += 1200;
1050 rd->thresh_mult[THR_SR_NEAREST_NEWB] += 1200;
1051#endif // CONFIG_EXT_REFS
1052 rd->thresh_mult[THR_SR_NEAREST_NEWA] += 1200;
1053 rd->thresh_mult[THR_SR_NEAREST_NEWG] += 1200;*/
1054
1055 rd->thresh_mult[THR_SR_NEAR_NEWMV] += 1500;
1056#if CONFIG_EXT_REFS
1057 rd->thresh_mult[THR_SR_NEAR_NEWL2] += 1500;
1058 rd->thresh_mult[THR_SR_NEAR_NEWL3] += 1500;
1059 rd->thresh_mult[THR_SR_NEAR_NEWB] += 1500;
1060#endif // CONFIG_EXT_REFS
1061 rd->thresh_mult[THR_SR_NEAR_NEWA] += 1500;
1062 rd->thresh_mult[THR_SR_NEAR_NEWG] += 1500;
1063
1064 rd->thresh_mult[THR_SR_ZERO_NEWMV] += 2000;
1065#if CONFIG_EXT_REFS
1066 rd->thresh_mult[THR_SR_ZERO_NEWL2] += 2000;
1067 rd->thresh_mult[THR_SR_ZERO_NEWL3] += 2000;
1068 rd->thresh_mult[THR_SR_ZERO_NEWB] += 2000;
1069#endif // CONFIG_EXT_REFS
1070 rd->thresh_mult[THR_SR_ZERO_NEWA] += 2000;
1071 rd->thresh_mult[THR_SR_ZERO_NEWG] += 2000;
1072
1073 rd->thresh_mult[THR_SR_NEW_NEWMV] += 1700;
1074#if CONFIG_EXT_REFS
1075 rd->thresh_mult[THR_SR_NEW_NEWL2] += 1700;
1076 rd->thresh_mult[THR_SR_NEW_NEWL3] += 1700;
1077 rd->thresh_mult[THR_SR_NEW_NEWB] += 1700;
1078#endif // CONFIG_EXT_REFS
1079 rd->thresh_mult[THR_SR_NEW_NEWA] += 1700;
1080 rd->thresh_mult[THR_SR_NEW_NEWG] += 1700;
1081#endif // CONFIG_COMPOUND_SINGLEREF
1082
Yaowu Xuc27fc142016-08-22 16:08:15 -07001083 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLA] += 1000;
1084#if CONFIG_EXT_REFS
1085 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL2A] += 1000;
1086 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL3A] += 1000;
1087#endif // CONFIG_EXT_REFS
1088 rd->thresh_mult[THR_COMP_NEAREST_NEARESTGA] += 1000;
1089#if CONFIG_EXT_REFS
1090 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLB] += 1000;
1091 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL2B] += 1000;
1092 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL3B] += 1000;
1093 rd->thresh_mult[THR_COMP_NEAREST_NEARESTGB] += 1000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001094#if CONFIG_ALTREF2
1095 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLA2] += 1000;
1096 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL2A2] += 1000;
1097 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL3A2] += 1000;
1098 rd->thresh_mult[THR_COMP_NEAREST_NEARESTGA2] += 1000;
1099#endif // CONFIG_ALTREF2
Zoe Liuc082bbc2017-05-17 13:31:37 -07001100
1101#if CONFIG_EXT_COMP_REFS
1102 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLL2] += 1000;
Zoe Liufcf5fa22017-06-26 16:00:38 -07001103 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLL3] += 1000;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001104 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLG] += 1000;
1105 rd->thresh_mult[THR_COMP_NEAREST_NEARESTBA] += 1000;
1106#endif // CONFIG_EXT_COMP_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001107#endif // CONFIG_EXT_REFS
1108
1109#else // CONFIG_EXT_INTER
1110
1111 rd->thresh_mult[THR_COMP_NEARESTLA] += 1000;
1112#if CONFIG_EXT_REFS
1113 rd->thresh_mult[THR_COMP_NEARESTL2A] += 1000;
1114 rd->thresh_mult[THR_COMP_NEARESTL3A] += 1000;
1115#endif // CONFIG_EXT_REFS
1116 rd->thresh_mult[THR_COMP_NEARESTGA] += 1000;
1117#if CONFIG_EXT_REFS
1118 rd->thresh_mult[THR_COMP_NEARESTLB] += 1000;
1119 rd->thresh_mult[THR_COMP_NEARESTL2B] += 1000;
1120 rd->thresh_mult[THR_COMP_NEARESTL3B] += 1000;
1121 rd->thresh_mult[THR_COMP_NEARESTGB] += 1000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001122#if CONFIG_ALTREF2
1123 rd->thresh_mult[THR_COMP_NEARESTLA2] += 1000;
1124 rd->thresh_mult[THR_COMP_NEARESTL2A2] += 1000;
1125 rd->thresh_mult[THR_COMP_NEARESTL3A2] += 1000;
1126 rd->thresh_mult[THR_COMP_NEARESTGA2] += 1000;
1127#endif // CONFIG_ALTREF2
1128
Zoe Liuc082bbc2017-05-17 13:31:37 -07001129#if CONFIG_EXT_COMP_REFS
1130 rd->thresh_mult[THR_COMP_NEARESTLL2] += 1000;
Zoe Liufcf5fa22017-06-26 16:00:38 -07001131 rd->thresh_mult[THR_COMP_NEARESTLL3] += 1000;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001132 rd->thresh_mult[THR_COMP_NEARESTLG] += 1000;
1133 rd->thresh_mult[THR_COMP_NEARESTBA] += 1000;
1134#endif // CONFIG_EXT_COMP_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001135#endif // CONFIG_EXT_REFS
1136
1137#endif // CONFIG_EXT_INTER
1138
1139#if CONFIG_EXT_INTER
1140
Yaowu Xuc27fc142016-08-22 16:08:15 -07001141 rd->thresh_mult[THR_COMP_NEAR_NEARLA] += 1200;
1142 rd->thresh_mult[THR_COMP_NEAREST_NEWLA] += 1500;
1143 rd->thresh_mult[THR_COMP_NEW_NEARESTLA] += 1500;
1144 rd->thresh_mult[THR_COMP_NEAR_NEWLA] += 1700;
1145 rd->thresh_mult[THR_COMP_NEW_NEARLA] += 1700;
1146 rd->thresh_mult[THR_COMP_NEW_NEWLA] += 2000;
1147 rd->thresh_mult[THR_COMP_ZERO_ZEROLA] += 2500;
1148
1149#if CONFIG_EXT_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001150 rd->thresh_mult[THR_COMP_NEAR_NEARL2A] += 1200;
1151 rd->thresh_mult[THR_COMP_NEAREST_NEWL2A] += 1500;
1152 rd->thresh_mult[THR_COMP_NEW_NEARESTL2A] += 1500;
1153 rd->thresh_mult[THR_COMP_NEAR_NEWL2A] += 1700;
1154 rd->thresh_mult[THR_COMP_NEW_NEARL2A] += 1700;
1155 rd->thresh_mult[THR_COMP_NEW_NEWL2A] += 2000;
1156 rd->thresh_mult[THR_COMP_ZERO_ZEROL2A] += 2500;
1157
Yaowu Xuc27fc142016-08-22 16:08:15 -07001158 rd->thresh_mult[THR_COMP_NEAR_NEARL3A] += 1200;
1159 rd->thresh_mult[THR_COMP_NEAREST_NEWL3A] += 1500;
1160 rd->thresh_mult[THR_COMP_NEW_NEARESTL3A] += 1500;
1161 rd->thresh_mult[THR_COMP_NEAR_NEWL3A] += 1700;
1162 rd->thresh_mult[THR_COMP_NEW_NEARL3A] += 1700;
1163 rd->thresh_mult[THR_COMP_NEW_NEWL3A] += 2000;
1164 rd->thresh_mult[THR_COMP_ZERO_ZEROL3A] += 2500;
1165#endif // CONFIG_EXT_REFS
1166
Yaowu Xuc27fc142016-08-22 16:08:15 -07001167 rd->thresh_mult[THR_COMP_NEAR_NEARGA] += 1200;
1168 rd->thresh_mult[THR_COMP_NEAREST_NEWGA] += 1500;
1169 rd->thresh_mult[THR_COMP_NEW_NEARESTGA] += 1500;
1170 rd->thresh_mult[THR_COMP_NEAR_NEWGA] += 1700;
1171 rd->thresh_mult[THR_COMP_NEW_NEARGA] += 1700;
1172 rd->thresh_mult[THR_COMP_NEW_NEWGA] += 2000;
1173 rd->thresh_mult[THR_COMP_ZERO_ZEROGA] += 2500;
1174
1175#if CONFIG_EXT_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001176 rd->thresh_mult[THR_COMP_NEAR_NEARLB] += 1200;
1177 rd->thresh_mult[THR_COMP_NEAREST_NEWLB] += 1500;
1178 rd->thresh_mult[THR_COMP_NEW_NEARESTLB] += 1500;
1179 rd->thresh_mult[THR_COMP_NEAR_NEWLB] += 1700;
1180 rd->thresh_mult[THR_COMP_NEW_NEARLB] += 1700;
1181 rd->thresh_mult[THR_COMP_NEW_NEWLB] += 2000;
1182 rd->thresh_mult[THR_COMP_ZERO_ZEROLB] += 2500;
1183
Yaowu Xuc27fc142016-08-22 16:08:15 -07001184 rd->thresh_mult[THR_COMP_NEAR_NEARL2B] += 1200;
1185 rd->thresh_mult[THR_COMP_NEAREST_NEWL2B] += 1500;
1186 rd->thresh_mult[THR_COMP_NEW_NEARESTL2B] += 1500;
1187 rd->thresh_mult[THR_COMP_NEAR_NEWL2B] += 1700;
1188 rd->thresh_mult[THR_COMP_NEW_NEARL2B] += 1700;
1189 rd->thresh_mult[THR_COMP_NEW_NEWL2B] += 2000;
1190 rd->thresh_mult[THR_COMP_ZERO_ZEROL2B] += 2500;
1191
Yaowu Xuc27fc142016-08-22 16:08:15 -07001192 rd->thresh_mult[THR_COMP_NEAR_NEARL3B] += 1200;
1193 rd->thresh_mult[THR_COMP_NEAREST_NEWL3B] += 1500;
1194 rd->thresh_mult[THR_COMP_NEW_NEARESTL3B] += 1500;
1195 rd->thresh_mult[THR_COMP_NEAR_NEWL3B] += 1700;
1196 rd->thresh_mult[THR_COMP_NEW_NEARL3B] += 1700;
1197 rd->thresh_mult[THR_COMP_NEW_NEWL3B] += 2000;
1198 rd->thresh_mult[THR_COMP_ZERO_ZEROL3B] += 2500;
1199
Yaowu Xuc27fc142016-08-22 16:08:15 -07001200 rd->thresh_mult[THR_COMP_NEAR_NEARGB] += 1200;
1201 rd->thresh_mult[THR_COMP_NEAREST_NEWGB] += 1500;
1202 rd->thresh_mult[THR_COMP_NEW_NEARESTGB] += 1500;
1203 rd->thresh_mult[THR_COMP_NEAR_NEWGB] += 1700;
1204 rd->thresh_mult[THR_COMP_NEW_NEARGB] += 1700;
1205 rd->thresh_mult[THR_COMP_NEW_NEWGB] += 2000;
1206 rd->thresh_mult[THR_COMP_ZERO_ZEROGB] += 2500;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001207
Zoe Liue9b15e22017-07-19 15:53:01 -07001208#if CONFIG_ALTREF2
1209 rd->thresh_mult[THR_COMP_NEAR_NEARLA2] += 1200;
1210 rd->thresh_mult[THR_COMP_NEAREST_NEWLA2] += 1500;
1211 rd->thresh_mult[THR_COMP_NEW_NEARESTLA2] += 1500;
1212 rd->thresh_mult[THR_COMP_NEAR_NEWLA2] += 1700;
1213 rd->thresh_mult[THR_COMP_NEW_NEARLA2] += 1700;
1214 rd->thresh_mult[THR_COMP_NEW_NEWLA2] += 2000;
1215 rd->thresh_mult[THR_COMP_ZERO_ZEROLA2] += 2500;
1216
1217 rd->thresh_mult[THR_COMP_NEAR_NEARL2A2] += 1200;
1218 rd->thresh_mult[THR_COMP_NEAREST_NEWL2A2] += 1500;
1219 rd->thresh_mult[THR_COMP_NEW_NEARESTL2A2] += 1500;
1220 rd->thresh_mult[THR_COMP_NEAR_NEWL2A2] += 1700;
1221 rd->thresh_mult[THR_COMP_NEW_NEARL2A2] += 1700;
1222 rd->thresh_mult[THR_COMP_NEW_NEWL2A2] += 2000;
1223 rd->thresh_mult[THR_COMP_ZERO_ZEROL2A2] += 2500;
1224
1225 rd->thresh_mult[THR_COMP_NEAR_NEARL3A2] += 1200;
1226 rd->thresh_mult[THR_COMP_NEAREST_NEWL3A2] += 1500;
1227 rd->thresh_mult[THR_COMP_NEW_NEARESTL3A2] += 1500;
1228 rd->thresh_mult[THR_COMP_NEAR_NEWL3A2] += 1700;
1229 rd->thresh_mult[THR_COMP_NEW_NEARL3A2] += 1700;
1230 rd->thresh_mult[THR_COMP_NEW_NEWL3A2] += 2000;
1231 rd->thresh_mult[THR_COMP_ZERO_ZEROL3A2] += 2500;
1232
1233 rd->thresh_mult[THR_COMP_NEAR_NEARGA2] += 1200;
1234 rd->thresh_mult[THR_COMP_NEAREST_NEWGA2] += 1500;
1235 rd->thresh_mult[THR_COMP_NEW_NEARESTGA2] += 1500;
1236 rd->thresh_mult[THR_COMP_NEAR_NEWGA2] += 1700;
1237 rd->thresh_mult[THR_COMP_NEW_NEARGA2] += 1700;
1238 rd->thresh_mult[THR_COMP_NEW_NEWGA2] += 2000;
1239 rd->thresh_mult[THR_COMP_ZERO_ZEROGA2] += 2500;
1240#endif // CONFIG_ALTREF2
1241
Zoe Liuc082bbc2017-05-17 13:31:37 -07001242#if CONFIG_EXT_COMP_REFS
Zoe Liuc082bbc2017-05-17 13:31:37 -07001243 rd->thresh_mult[THR_COMP_NEAR_NEARLL2] += 1200;
1244 rd->thresh_mult[THR_COMP_NEAREST_NEWLL2] += 1500;
1245 rd->thresh_mult[THR_COMP_NEW_NEARESTLL2] += 1500;
1246 rd->thresh_mult[THR_COMP_NEAR_NEWLL2] += 1700;
1247 rd->thresh_mult[THR_COMP_NEW_NEARLL2] += 1700;
1248 rd->thresh_mult[THR_COMP_NEW_NEWLL2] += 2000;
1249 rd->thresh_mult[THR_COMP_ZERO_ZEROLL2] += 2500;
1250
Zoe Liufcf5fa22017-06-26 16:00:38 -07001251 rd->thresh_mult[THR_COMP_NEAR_NEARLL3] += 1200;
1252 rd->thresh_mult[THR_COMP_NEAREST_NEWLL3] += 1500;
1253 rd->thresh_mult[THR_COMP_NEW_NEARESTLL3] += 1500;
1254 rd->thresh_mult[THR_COMP_NEAR_NEWLL3] += 1700;
1255 rd->thresh_mult[THR_COMP_NEW_NEARLL3] += 1700;
1256 rd->thresh_mult[THR_COMP_NEW_NEWLL3] += 2000;
1257 rd->thresh_mult[THR_COMP_ZERO_ZEROLL3] += 2500;
1258
Zoe Liuc082bbc2017-05-17 13:31:37 -07001259 rd->thresh_mult[THR_COMP_NEAR_NEARLG] += 1200;
1260 rd->thresh_mult[THR_COMP_NEAREST_NEWLG] += 1500;
1261 rd->thresh_mult[THR_COMP_NEW_NEARESTLG] += 1500;
1262 rd->thresh_mult[THR_COMP_NEAR_NEWLG] += 1700;
1263 rd->thresh_mult[THR_COMP_NEW_NEARLG] += 1700;
1264 rd->thresh_mult[THR_COMP_NEW_NEWLG] += 2000;
1265 rd->thresh_mult[THR_COMP_ZERO_ZEROLG] += 2500;
1266
Zoe Liuc082bbc2017-05-17 13:31:37 -07001267 rd->thresh_mult[THR_COMP_NEAR_NEARBA] += 1200;
1268 rd->thresh_mult[THR_COMP_NEAREST_NEWBA] += 1500;
1269 rd->thresh_mult[THR_COMP_NEW_NEARESTBA] += 1500;
1270 rd->thresh_mult[THR_COMP_NEAR_NEWBA] += 1700;
1271 rd->thresh_mult[THR_COMP_NEW_NEARBA] += 1700;
1272 rd->thresh_mult[THR_COMP_NEW_NEWBA] += 2000;
1273 rd->thresh_mult[THR_COMP_ZERO_ZEROBA] += 2500;
1274#endif // CONFIG_EXT_COMP_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001275#endif // CONFIG_EXT_REFS
1276
1277#else // CONFIG_EXT_INTER
1278
1279 rd->thresh_mult[THR_COMP_NEARLA] += 1500;
1280 rd->thresh_mult[THR_COMP_NEWLA] += 2000;
1281#if CONFIG_EXT_REFS
1282 rd->thresh_mult[THR_COMP_NEARL2A] += 1500;
1283 rd->thresh_mult[THR_COMP_NEWL2A] += 2000;
1284 rd->thresh_mult[THR_COMP_NEARL3A] += 1500;
1285 rd->thresh_mult[THR_COMP_NEWL3A] += 2000;
1286#endif // CONFIG_EXT_REFS
1287 rd->thresh_mult[THR_COMP_NEARGA] += 1500;
1288 rd->thresh_mult[THR_COMP_NEWGA] += 2000;
1289
1290#if CONFIG_EXT_REFS
1291 rd->thresh_mult[THR_COMP_NEARLB] += 1500;
1292 rd->thresh_mult[THR_COMP_NEWLB] += 2000;
1293 rd->thresh_mult[THR_COMP_NEARL2B] += 1500;
1294 rd->thresh_mult[THR_COMP_NEWL2B] += 2000;
1295 rd->thresh_mult[THR_COMP_NEARL3B] += 1500;
1296 rd->thresh_mult[THR_COMP_NEWL3B] += 2000;
1297 rd->thresh_mult[THR_COMP_NEARGB] += 1500;
1298 rd->thresh_mult[THR_COMP_NEWGB] += 2000;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001299
Zoe Liue9b15e22017-07-19 15:53:01 -07001300#if CONFIG_ALTREF2
1301 rd->thresh_mult[THR_COMP_NEARLA2] += 1500;
1302 rd->thresh_mult[THR_COMP_NEWLA2] += 2000;
1303 rd->thresh_mult[THR_COMP_NEARL2A2] += 1500;
1304 rd->thresh_mult[THR_COMP_NEWL2A2] += 2000;
1305 rd->thresh_mult[THR_COMP_NEARL3A2] += 1500;
1306 rd->thresh_mult[THR_COMP_NEWL3A2] += 2000;
1307 rd->thresh_mult[THR_COMP_NEARGA2] += 1500;
1308 rd->thresh_mult[THR_COMP_NEWGA2] += 2000;
1309#endif // CONFIG_ALTREF2
1310
Zoe Liuc082bbc2017-05-17 13:31:37 -07001311#if CONFIG_EXT_COMP_REFS
1312 rd->thresh_mult[THR_COMP_NEARLL2] += 1500;
1313 rd->thresh_mult[THR_COMP_NEWLL2] += 2000;
Zoe Liufcf5fa22017-06-26 16:00:38 -07001314 rd->thresh_mult[THR_COMP_NEARLL3] += 1500;
1315 rd->thresh_mult[THR_COMP_NEWLL3] += 2000;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001316 rd->thresh_mult[THR_COMP_NEARLG] += 1500;
1317 rd->thresh_mult[THR_COMP_NEWLG] += 2000;
1318 rd->thresh_mult[THR_COMP_NEARBA] += 1500;
1319 rd->thresh_mult[THR_COMP_NEWBA] += 2000;
1320#endif // CONFIG_EXT_COMP_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001321#endif // CONFIG_EXT_REFS
1322
1323 rd->thresh_mult[THR_COMP_ZEROLA] += 2500;
1324#if CONFIG_EXT_REFS
1325 rd->thresh_mult[THR_COMP_ZEROL2A] += 2500;
1326 rd->thresh_mult[THR_COMP_ZEROL3A] += 2500;
1327#endif // CONFIG_EXT_REFS
1328 rd->thresh_mult[THR_COMP_ZEROGA] += 2500;
1329
1330#if CONFIG_EXT_REFS
1331 rd->thresh_mult[THR_COMP_ZEROLB] += 2500;
1332 rd->thresh_mult[THR_COMP_ZEROL2B] += 2500;
1333 rd->thresh_mult[THR_COMP_ZEROL3B] += 2500;
1334 rd->thresh_mult[THR_COMP_ZEROGB] += 2500;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001335
Zoe Liue9b15e22017-07-19 15:53:01 -07001336#if CONFIG_ALTREF2
1337 rd->thresh_mult[THR_COMP_ZEROLA2] += 2500;
1338 rd->thresh_mult[THR_COMP_ZEROL2A2] += 2500;
1339 rd->thresh_mult[THR_COMP_ZEROL3A2] += 2500;
1340 rd->thresh_mult[THR_COMP_ZEROGA2] += 2500;
1341#endif // CONFIG_ALTREF2
1342
Zoe Liuc082bbc2017-05-17 13:31:37 -07001343#if CONFIG_EXT_COMP_REFS
1344 rd->thresh_mult[THR_COMP_ZEROLL2] += 2500;
Zoe Liufcf5fa22017-06-26 16:00:38 -07001345 rd->thresh_mult[THR_COMP_ZEROLL3] += 2500;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001346 rd->thresh_mult[THR_COMP_ZEROLG] += 2500;
1347 rd->thresh_mult[THR_COMP_ZEROBA] += 2500;
1348#endif // CONFIG_EXT_COMP_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001349#endif // CONFIG_EXT_REFS
1350
1351#endif // CONFIG_EXT_INTER
1352
1353 rd->thresh_mult[THR_H_PRED] += 2000;
1354 rd->thresh_mult[THR_V_PRED] += 2000;
1355 rd->thresh_mult[THR_D135_PRED] += 2500;
1356 rd->thresh_mult[THR_D207_PRED] += 2500;
1357 rd->thresh_mult[THR_D153_PRED] += 2500;
1358 rd->thresh_mult[THR_D63_PRED] += 2500;
1359 rd->thresh_mult[THR_D117_PRED] += 2500;
1360 rd->thresh_mult[THR_D45_PRED] += 2500;
1361
1362#if CONFIG_EXT_INTER
1363 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROL] += 1500;
1364 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTL] += 1500;
1365 rd->thresh_mult[THR_COMP_INTERINTRA_NEARL] += 1500;
1366 rd->thresh_mult[THR_COMP_INTERINTRA_NEWL] += 2000;
1367
1368#if CONFIG_EXT_REFS
1369 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROL2] += 1500;
1370 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTL2] += 1500;
1371 rd->thresh_mult[THR_COMP_INTERINTRA_NEARL2] += 1500;
1372 rd->thresh_mult[THR_COMP_INTERINTRA_NEWL2] += 2000;
1373
1374 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROL3] += 1500;
1375 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTL3] += 1500;
1376 rd->thresh_mult[THR_COMP_INTERINTRA_NEARL3] += 1500;
1377 rd->thresh_mult[THR_COMP_INTERINTRA_NEWL3] += 2000;
1378#endif // CONFIG_EXT_REFS
1379
1380 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROG] += 1500;
1381 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTG] += 1500;
1382 rd->thresh_mult[THR_COMP_INTERINTRA_NEARG] += 1500;
1383 rd->thresh_mult[THR_COMP_INTERINTRA_NEWG] += 2000;
1384
1385#if CONFIG_EXT_REFS
1386 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROB] += 1500;
1387 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTB] += 1500;
1388 rd->thresh_mult[THR_COMP_INTERINTRA_NEARB] += 1500;
1389 rd->thresh_mult[THR_COMP_INTERINTRA_NEWB] += 2000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001390
1391#if CONFIG_ALTREF2
1392 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROA2] += 1500;
1393 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTA2] += 1500;
1394 rd->thresh_mult[THR_COMP_INTERINTRA_NEARA2] += 1500;
1395 rd->thresh_mult[THR_COMP_INTERINTRA_NEWA2] += 2000;
1396#endif // CONFIG_ALTREF2
Yaowu Xuc27fc142016-08-22 16:08:15 -07001397#endif // CONFIG_EXT_REFS
1398
1399 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROA] += 1500;
1400 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTA] += 1500;
1401 rd->thresh_mult[THR_COMP_INTERINTRA_NEARA] += 1500;
1402 rd->thresh_mult[THR_COMP_INTERINTRA_NEWA] += 2000;
1403#endif // CONFIG_EXT_INTER
1404}
1405
Yaowu Xuf883b422016-08-30 14:01:10 -07001406void av1_set_rd_speed_thresholds_sub8x8(AV1_COMP *cpi) {
Thomas Daede6eca8352017-03-17 14:14:12 -07001407 static const int thresh_mult[MAX_REFS] = {
Yaowu Xuc27fc142016-08-22 16:08:15 -07001408#if CONFIG_EXT_REFS
Thomas Daede6eca8352017-03-17 14:14:12 -07001409 2500,
1410 2500,
1411 2500,
1412 2500,
Zoe Liue9b15e22017-07-19 15:53:01 -07001413#if CONFIG_ALTREF2
1414 2500,
1415#endif // CONFIG_ALTREF2
Thomas Daede6eca8352017-03-17 14:14:12 -07001416 2500,
1417 2500,
1418 4500,
1419 4500,
1420 4500,
1421 4500,
1422 4500,
1423 4500,
1424 4500,
1425 4500,
Zoe Liue9b15e22017-07-19 15:53:01 -07001426#if CONFIG_ALTREF2
1427 4500,
1428 4500,
1429 4500,
1430 4500,
1431#endif // CONFIG_ALTREF2
Thomas Daede6eca8352017-03-17 14:14:12 -07001432 2500
Zoe Liue9b15e22017-07-19 15:53:01 -07001433#else // !CONFIG_EXT_REFS
Thomas Daede6eca8352017-03-17 14:14:12 -07001434 2500,
1435 2500,
1436 2500,
1437 4500,
1438 4500,
1439 2500
Yaowu Xuc27fc142016-08-22 16:08:15 -07001440#endif // CONFIG_EXT_REFS
1441 };
1442 RD_OPT *const rd = &cpi->rd;
Thomas Daede6eca8352017-03-17 14:14:12 -07001443 memcpy(rd->thresh_mult_sub8x8, thresh_mult, sizeof(thresh_mult));
Yaowu Xuc27fc142016-08-22 16:08:15 -07001444}
1445
Yaowu Xuf883b422016-08-30 14:01:10 -07001446void av1_update_rd_thresh_fact(const AV1_COMMON *const cm,
1447 int (*factor_buf)[MAX_MODES], int rd_thresh,
1448 int bsize, int best_mode_index) {
Yaowu Xuc27fc142016-08-22 16:08:15 -07001449 if (rd_thresh > 0) {
Jingning Han9104bed2016-12-14 09:38:00 -08001450#if CONFIG_CB4X4
1451 const int top_mode = MAX_MODES;
1452#else
Yaowu Xuc27fc142016-08-22 16:08:15 -07001453 const int top_mode = bsize < BLOCK_8X8 ? MAX_REFS : MAX_MODES;
Jingning Han9104bed2016-12-14 09:38:00 -08001454#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -07001455 int mode;
1456 for (mode = 0; mode < top_mode; ++mode) {
Yaowu Xuf883b422016-08-30 14:01:10 -07001457 const BLOCK_SIZE min_size = AOMMAX(bsize - 1, BLOCK_4X4);
Urvang Joshicb586f32016-09-20 11:36:33 -07001458 const BLOCK_SIZE max_size = AOMMIN(bsize + 2, (int)cm->sb_size);
Yaowu Xuc27fc142016-08-22 16:08:15 -07001459 BLOCK_SIZE bs;
1460 for (bs = min_size; bs <= max_size; ++bs) {
1461 int *const fact = &factor_buf[bs][mode];
1462 if (mode == best_mode_index) {
1463 *fact -= (*fact >> 4);
1464 } else {
Yaowu Xuf883b422016-08-30 14:01:10 -07001465 *fact = AOMMIN(*fact + RD_THRESH_INC, rd_thresh * RD_THRESH_MAX_FACT);
Yaowu Xuc27fc142016-08-22 16:08:15 -07001466 }
1467 }
1468 }
1469 }
1470}
1471
Yaowu Xuf883b422016-08-30 14:01:10 -07001472int av1_get_intra_cost_penalty(int qindex, int qdelta,
1473 aom_bit_depth_t bit_depth) {
1474 const int q = av1_dc_quant(qindex, qdelta, bit_depth);
Sebastien Alaiwan71e87842017-04-12 16:03:28 +02001475#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -07001476 switch (bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -07001477 case AOM_BITS_8: return 20 * q;
1478 case AOM_BITS_10: return 5 * q;
1479 case AOM_BITS_12: return ROUND_POWER_OF_TWO(5 * q, 2);
Yaowu Xuc27fc142016-08-22 16:08:15 -07001480 default:
Yaowu Xuf883b422016-08-30 14:01:10 -07001481 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -07001482 return -1;
1483 }
1484#else
1485 return 20 * q;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +02001486#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -07001487}