blob: 285adfa263e5b7d8b18b89c8d415831dbd454ca7 [file] [log] [blame]
Yaowu Xuc27fc142016-08-22 16:08:15 -07001/*
Yaowu Xu2ab7ff02016-09-02 12:04:54 -07002 * Copyright (c) 2016, Alliance for Open Media. All rights reserved
Yaowu Xuc27fc142016-08-22 16:08:15 -07003 *
Yaowu Xu2ab7ff02016-09-02 12:04:54 -07004 * This source code is subject to the terms of the BSD 2 Clause License and
5 * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
6 * was not distributed with this source code in the LICENSE file, you can
7 * obtain it at www.aomedia.org/license/software. If the Alliance for Open
8 * Media Patent License 1.0 was not distributed with this source code in the
9 * PATENTS file, you can obtain it at www.aomedia.org/license/patent.
Yaowu Xuc27fc142016-08-22 16:08:15 -070010 */
11
Yaowu Xuf883b422016-08-30 14:01:10 -070012#ifndef AV1_COMMON_BLOCKD_H_
13#define AV1_COMMON_BLOCKD_H_
Yaowu Xuc27fc142016-08-22 16:08:15 -070014
Yaowu Xuf883b422016-08-30 14:01:10 -070015#include "./aom_config.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070016
Yaowu Xuf883b422016-08-30 14:01:10 -070017#include "aom_dsp/aom_dsp_common.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070018#include "aom_ports/mem.h"
19#include "aom_scale/yv12config.h"
20
21#include "av1/common/common_data.h"
22#include "av1/common/quant_common.h"
23#include "av1/common/entropy.h"
24#include "av1/common/entropymode.h"
25#include "av1/common/mv.h"
26#include "av1/common/scale.h"
27#include "av1/common/seg_common.h"
28#include "av1/common/tile_common.h"
Yushin Cho77bba8d2016-11-04 16:36:56 -070029#if CONFIG_PVQ
30#include "av1/common/pvq.h"
31#include "av1/common/pvq_state.h"
32#include "av1/decoder/decint.h"
33#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -070034
35#ifdef __cplusplus
36extern "C" {
37#endif
38
39#define MAX_MB_PLANE 3
40
David Barkerac37fa32016-12-02 12:30:21 +000041#if CONFIG_EXT_INTER
42// Should we try rectangular interintra predictions?
43#define USE_RECT_INTERINTRA 1
Sarah Parkerb9f757c2017-01-06 17:12:24 -080044
Debargha Mukherjee1edf9a32017-01-07 18:54:20 -080045#if CONFIG_COMPOUND_SEGMENT
46
47// Set COMPOUND_SEGMENT_TYPE to one of the three
48// 0: Uniform
49// 1: Difference weighted
50#define COMPOUND_SEGMENT_TYPE 1
51
52#if COMPOUND_SEGMENT_TYPE == 0
53#define MAX_SEG_MASK_BITS 1
Sarah Parkerb9f757c2017-01-06 17:12:24 -080054// SEG_MASK_TYPES should not surpass 1 << MAX_SEG_MASK_BITS
55typedef enum {
56 UNIFORM_45 = 0,
57 UNIFORM_45_INV,
Sarah Parkerb9f757c2017-01-06 17:12:24 -080058 SEG_MASK_TYPES,
59} SEG_MASK_TYPE;
Debargha Mukherjee1edf9a32017-01-07 18:54:20 -080060
61#elif COMPOUND_SEGMENT_TYPE == 1
62#define MAX_SEG_MASK_BITS 1
63// SEG_MASK_TYPES should not surpass 1 << MAX_SEG_MASK_BITS
64typedef enum {
65 DIFFWTD_45 = 0,
66 DIFFWTD_45_INV,
67 SEG_MASK_TYPES,
68} SEG_MASK_TYPE;
69
70#endif // COMPOUND_SEGMENT_TYPE
Sarah Parkerb9f757c2017-01-06 17:12:24 -080071#endif // CONFIG_COMPOUND_SEGMENT
Debargha Mukherjee1edf9a32017-01-07 18:54:20 -080072#endif // CONFIG_EXT_INTER
David Barkerac37fa32016-12-02 12:30:21 +000073
Yaowu Xuc27fc142016-08-22 16:08:15 -070074typedef enum {
75 KEY_FRAME = 0,
76 INTER_FRAME = 1,
77 FRAME_TYPES,
78} FRAME_TYPE;
79
Yaowu Xuc27fc142016-08-22 16:08:15 -070080static INLINE int is_inter_mode(PREDICTION_MODE mode) {
81#if CONFIG_EXT_INTER
82 return mode >= NEARESTMV && mode <= NEW_NEWMV;
83#else
84 return mode >= NEARESTMV && mode <= NEWMV;
85#endif // CONFIG_EXT_INTER
86}
87
Yushin Cho77bba8d2016-11-04 16:36:56 -070088#if CONFIG_PVQ
89typedef struct PVQ_INFO {
90 int theta[PVQ_MAX_PARTITIONS];
91 int max_theta[PVQ_MAX_PARTITIONS];
92 int qg[PVQ_MAX_PARTITIONS];
93 int k[PVQ_MAX_PARTITIONS];
Yushin Cho48f84db2016-11-07 21:20:17 -080094 od_coeff y[OD_TXSIZE_MAX * OD_TXSIZE_MAX];
Yushin Cho77bba8d2016-11-04 16:36:56 -070095 int nb_bands;
96 int off[PVQ_MAX_PARTITIONS];
97 int size[PVQ_MAX_PARTITIONS];
98 int skip_rest;
99 int skip_dir;
100 int bs; // log of the block size minus two,
101 // i.e. equivalent to aom's TX_SIZE
102 int ac_dc_coded; // block skip info, indicating whether DC/AC is coded.
103 // bit0: DC coded, bit1 : AC coded (1 means coded)
104 tran_low_t dq_dc_residue;
105} PVQ_INFO;
106
107typedef struct PVQ_QUEUE {
108 PVQ_INFO *buf; // buffer for pvq info, stored in encoding order
109 int curr_pos; // curr position to write PVQ_INFO
110 int buf_len; // allocated buffer length
111 int last_pos; // last written position of PVQ_INFO in a tile
112} PVQ_QUEUE;
113#endif
114
David Barkerac37fa32016-12-02 12:30:21 +0000115typedef struct {
116 uint8_t *plane[MAX_MB_PLANE];
117 int stride[MAX_MB_PLANE];
118} BUFFER_SET;
119
Yaowu Xuc27fc142016-08-22 16:08:15 -0700120#if CONFIG_EXT_INTER
121static INLINE int is_inter_singleref_mode(PREDICTION_MODE mode) {
122 return mode >= NEARESTMV && mode <= NEWFROMNEARMV;
123}
124
125static INLINE int is_inter_compound_mode(PREDICTION_MODE mode) {
126 return mode >= NEAREST_NEARESTMV && mode <= NEW_NEWMV;
127}
128
129static INLINE PREDICTION_MODE compound_ref0_mode(PREDICTION_MODE mode) {
130 static PREDICTION_MODE lut[MB_MODE_COUNT] = {
Urvang Joshi102245d2016-11-28 13:05:36 -0800131 MB_MODE_COUNT, // DC_PRED
132 MB_MODE_COUNT, // V_PRED
133 MB_MODE_COUNT, // H_PRED
134 MB_MODE_COUNT, // D45_PRED
135 MB_MODE_COUNT, // D135_PRED
136 MB_MODE_COUNT, // D117_PRED
137 MB_MODE_COUNT, // D153_PRED
138 MB_MODE_COUNT, // D207_PRED
139 MB_MODE_COUNT, // D63_PRED
140#if CONFIG_ALT_INTRA
141 MB_MODE_COUNT, // SMOOTH_PRED
142#endif // CONFIG_ALT_INTRA
143 MB_MODE_COUNT, // TM_PRED
144 MB_MODE_COUNT, // NEARESTMV
145 MB_MODE_COUNT, // NEARMV
146 MB_MODE_COUNT, // ZEROMV
147 MB_MODE_COUNT, // NEWMV
148 MB_MODE_COUNT, // NEWFROMNEARMV
149 NEARESTMV, // NEAREST_NEARESTMV
150 NEARESTMV, // NEAREST_NEARMV
151 NEARMV, // NEAR_NEARESTMV
152 NEARMV, // NEAR_NEARMV
153 NEARESTMV, // NEAREST_NEWMV
154 NEWMV, // NEW_NEARESTMV
155 NEARMV, // NEAR_NEWMV
156 NEWMV, // NEW_NEARMV
157 ZEROMV, // ZERO_ZEROMV
158 NEWMV, // NEW_NEWMV
Yaowu Xuc27fc142016-08-22 16:08:15 -0700159 };
160 assert(is_inter_compound_mode(mode));
161 return lut[mode];
162}
163
164static INLINE PREDICTION_MODE compound_ref1_mode(PREDICTION_MODE mode) {
165 static PREDICTION_MODE lut[MB_MODE_COUNT] = {
Urvang Joshi102245d2016-11-28 13:05:36 -0800166 MB_MODE_COUNT, // DC_PRED
167 MB_MODE_COUNT, // V_PRED
168 MB_MODE_COUNT, // H_PRED
169 MB_MODE_COUNT, // D45_PRED
170 MB_MODE_COUNT, // D135_PRED
171 MB_MODE_COUNT, // D117_PRED
172 MB_MODE_COUNT, // D153_PRED
173 MB_MODE_COUNT, // D207_PRED
174 MB_MODE_COUNT, // D63_PRED
175#if CONFIG_ALT_INTRA
176 MB_MODE_COUNT, // SMOOTH_PRED
177#endif // CONFIG_ALT_INTRA
178 MB_MODE_COUNT, // TM_PRED
179 MB_MODE_COUNT, // NEARESTMV
180 MB_MODE_COUNT, // NEARMV
181 MB_MODE_COUNT, // ZEROMV
182 MB_MODE_COUNT, // NEWMV
183 MB_MODE_COUNT, // NEWFROMNEARMV
184 NEARESTMV, // NEAREST_NEARESTMV
185 NEARMV, // NEAREST_NEARMV
186 NEARESTMV, // NEAR_NEARESTMV
187 NEARMV, // NEAR_NEARMV
188 NEWMV, // NEAREST_NEWMV
189 NEARESTMV, // NEW_NEARESTMV
190 NEWMV, // NEAR_NEWMV
191 NEARMV, // NEW_NEARMV
192 ZEROMV, // ZERO_ZEROMV
193 NEWMV, // NEW_NEWMV
Yaowu Xuc27fc142016-08-22 16:08:15 -0700194 };
195 assert(is_inter_compound_mode(mode));
196 return lut[mode];
197}
198
199static INLINE int have_newmv_in_inter_mode(PREDICTION_MODE mode) {
200 return (mode == NEWMV || mode == NEWFROMNEARMV || mode == NEW_NEWMV ||
201 mode == NEAREST_NEWMV || mode == NEW_NEARESTMV ||
202 mode == NEAR_NEWMV || mode == NEW_NEARMV);
203}
Sarah Parker6fdc8532016-11-16 17:47:13 -0800204
Sarah Parker6fdc8532016-11-16 17:47:13 -0800205static INLINE int is_masked_compound_type(COMPOUND_TYPE type) {
Sarah Parker569edda2016-12-14 14:57:38 -0800206#if CONFIG_COMPOUND_SEGMENT
207 return (type == COMPOUND_WEDGE || type == COMPOUND_SEG);
208#else
Sarah Parker6fdc8532016-11-16 17:47:13 -0800209 return (type == COMPOUND_WEDGE);
Sarah Parker569edda2016-12-14 14:57:38 -0800210#endif // CONFIG_COMPOUND_SEGMENT
Sarah Parker6fdc8532016-11-16 17:47:13 -0800211}
Yaowu Xuc27fc142016-08-22 16:08:15 -0700212#else
213
214static INLINE int have_newmv_in_inter_mode(PREDICTION_MODE mode) {
215 return (mode == NEWMV);
216}
217#endif // CONFIG_EXT_INTER
218
219/* For keyframes, intra block modes are predicted by the (already decoded)
220 modes for the Y blocks to the left and above us; for interframes, there
221 is a single probability table. */
222
223typedef struct {
224 PREDICTION_MODE as_mode;
225 int_mv as_mv[2]; // first, second inter predictor motion vectors
226#if CONFIG_REF_MV
Yaowu Xuf5bbbfa2016-09-26 09:13:38 -0700227 int_mv pred_mv[2];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700228#endif
229#if CONFIG_EXT_INTER
230 int_mv ref_mv[2];
231#endif // CONFIG_EXT_INTER
232} b_mode_info;
233
234typedef int8_t MV_REFERENCE_FRAME;
235
Urvang Joshib100db72016-10-12 16:28:56 -0700236#if CONFIG_PALETTE
Yaowu Xuc27fc142016-08-22 16:08:15 -0700237typedef struct {
238 // Number of base colors for Y (0) and UV (1)
239 uint8_t palette_size[2];
240// Value of base colors for Y, U, and V
Yaowu Xuf883b422016-08-30 14:01:10 -0700241#if CONFIG_AOM_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700242 uint16_t palette_colors[3 * PALETTE_MAX_SIZE];
243#else
244 uint8_t palette_colors[3 * PALETTE_MAX_SIZE];
Yaowu Xuf883b422016-08-30 14:01:10 -0700245#endif // CONFIG_AOM_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700246 // Only used by encoder to store the color index of the top left pixel.
247 // TODO(huisu): move this to encoder
248 uint8_t palette_first_color_idx[2];
249} PALETTE_MODE_INFO;
Urvang Joshib100db72016-10-12 16:28:56 -0700250#endif // CONFIG_PALETTE
Yaowu Xuc27fc142016-08-22 16:08:15 -0700251
hui su5db97432016-10-14 16:10:14 -0700252#if CONFIG_FILTER_INTRA
Yaowu Xuc27fc142016-08-22 16:08:15 -0700253typedef struct {
254 // 1: an ext intra mode is used; 0: otherwise.
hui su5db97432016-10-14 16:10:14 -0700255 uint8_t use_filter_intra_mode[PLANE_TYPES];
256 FILTER_INTRA_MODE filter_intra_mode[PLANE_TYPES];
257} FILTER_INTRA_MODE_INFO;
258#endif // CONFIG_FILTER_INTRA
Yaowu Xuc27fc142016-08-22 16:08:15 -0700259
Angie Chiang9a44f5f2016-11-06 12:19:06 -0800260#if CONFIG_VAR_TX
Angie Chiang7c2b7f22016-11-07 16:00:00 -0800261#if CONFIG_RD_DEBUG
Angie Chiang9a44f5f2016-11-06 12:19:06 -0800262#define TXB_COEFF_COST_MAP_SIZE (2 * MAX_MIB_SIZE)
Angie Chiang7c2b7f22016-11-07 16:00:00 -0800263#endif
264#endif
Angie Chiang9a44f5f2016-11-06 12:19:06 -0800265
266// TODO(angiebird): Merge RD_COST and RD_STATS
267typedef struct RD_STATS {
268 int rate;
269 int64_t dist;
270 int64_t sse;
271 int skip;
272#if CONFIG_RD_DEBUG
273 int txb_coeff_cost[MAX_MB_PLANE];
Angie Chiang3963d632016-11-10 18:41:40 -0800274#if CONFIG_VAR_TX
Angie Chiang9a44f5f2016-11-06 12:19:06 -0800275 int txb_coeff_cost_map[MAX_MB_PLANE][TXB_COEFF_COST_MAP_SIZE]
276 [TXB_COEFF_COST_MAP_SIZE];
Angie Chiang3963d632016-11-10 18:41:40 -0800277#endif // CONFIG_VAR_TX
278#endif // CONFIG_RD_DEBUG
Angie Chiang9a44f5f2016-11-06 12:19:06 -0800279} RD_STATS;
Angie Chiang9a44f5f2016-11-06 12:19:06 -0800280
Sarah Parker6fdc8532016-11-16 17:47:13 -0800281#if CONFIG_EXT_INTER
282typedef struct {
283 COMPOUND_TYPE type;
284 int wedge_index;
285 int wedge_sign;
Sarah Parker569edda2016-12-14 14:57:38 -0800286#if CONFIG_COMPOUND_SEGMENT
Sarah Parkerb9f757c2017-01-06 17:12:24 -0800287 SEG_MASK_TYPE mask_type;
288 DECLARE_ALIGNED(16, uint8_t, seg_mask[2 * MAX_SB_SQUARE]);
Sarah Parker569edda2016-12-14 14:57:38 -0800289#endif // CONFIG_COMPOUND_SEGMENT
Sarah Parker6fdc8532016-11-16 17:47:13 -0800290} INTERINTER_COMPOUND_DATA;
291#endif // CONFIG_EXT_INTER
292
Yaowu Xuc27fc142016-08-22 16:08:15 -0700293// This structure now relates to 8x8 block regions.
294typedef struct {
295 // Common for both INTER and INTRA blocks
296 BLOCK_SIZE sb_type;
297 PREDICTION_MODE mode;
298 TX_SIZE tx_size;
299#if CONFIG_VAR_TX
300 // TODO(jingning): This effectively assigned a separate entry for each
301 // 8x8 block. Apparently it takes much more space than needed.
302 TX_SIZE inter_tx_size[MAX_MIB_SIZE][MAX_MIB_SIZE];
Jingning Hane67b38a2016-11-04 10:30:00 -0700303 TX_SIZE min_tx_size;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700304#endif
305 int8_t skip;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700306 int8_t segment_id;
307#if CONFIG_SUPERTX
308 // Minimum of all segment IDs under the current supertx block.
309 int8_t segment_id_supertx;
310#endif // CONFIG_SUPERTX
311 int8_t seg_id_predicted; // valid only when temporal_update is enabled
312
313 // Only for INTRA blocks
314 PREDICTION_MODE uv_mode;
Urvang Joshib100db72016-10-12 16:28:56 -0700315#if CONFIG_PALETTE
Yaowu Xuc27fc142016-08-22 16:08:15 -0700316 PALETTE_MODE_INFO palette_mode_info;
Urvang Joshib100db72016-10-12 16:28:56 -0700317#endif // CONFIG_PALETTE
Yaowu Xuc27fc142016-08-22 16:08:15 -0700318
319// Only for INTER blocks
320#if CONFIG_DUAL_FILTER
James Zern7b9407a2016-05-18 23:48:05 -0700321 InterpFilter interp_filter[4];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700322#else
James Zern7b9407a2016-05-18 23:48:05 -0700323 InterpFilter interp_filter;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700324#endif
325 MV_REFERENCE_FRAME ref_frame[2];
326 TX_TYPE tx_type;
327
hui su5db97432016-10-14 16:10:14 -0700328#if CONFIG_FILTER_INTRA
329 FILTER_INTRA_MODE_INFO filter_intra_mode_info;
330#endif // CONFIG_FILTER_INTRA
Yaowu Xuc27fc142016-08-22 16:08:15 -0700331#if CONFIG_EXT_INTRA
hui sueda3d762016-12-06 16:58:23 -0800332 // The actual prediction angle is the base angle + (angle_delta * step).
Yaowu Xuc27fc142016-08-22 16:08:15 -0700333 int8_t angle_delta[2];
hui sueda3d762016-12-06 16:58:23 -0800334#if CONFIG_INTRA_INTERP
Yaowu Xuc27fc142016-08-22 16:08:15 -0700335 // To-Do (huisu): this may be replaced by interp_filter
336 INTRA_FILTER intra_filter;
hui sueda3d762016-12-06 16:58:23 -0800337#endif // CONFIG_INTRA_INTERP
Yaowu Xuc27fc142016-08-22 16:08:15 -0700338#endif // CONFIG_EXT_INTRA
339
340#if CONFIG_EXT_INTER
341 INTERINTRA_MODE interintra_mode;
342 // TODO(debargha): Consolidate these flags
343 int use_wedge_interintra;
344 int interintra_wedge_index;
345 int interintra_wedge_sign;
Sarah Parker6fdc8532016-11-16 17:47:13 -0800346 INTERINTER_COMPOUND_DATA interinter_compound_data;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700347#endif // CONFIG_EXT_INTER
Yue Chencb60b182016-10-13 15:18:22 -0700348 MOTION_MODE motion_mode;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700349 int_mv mv[2];
350 int_mv pred_mv[2];
351#if CONFIG_REF_MV
352 uint8_t ref_mv_idx;
353#endif
354#if CONFIG_EXT_PARTITION_TYPES
355 PARTITION_TYPE partition;
356#endif
357#if CONFIG_NEW_QUANT
358 int dq_off_index;
359 int send_dq_bit;
360#endif // CONFIG_NEW_QUANT
361 /* deringing gain *per-superblock* */
362 int8_t dering_gain;
Arild Fuldseth07441162016-08-15 15:07:52 +0200363#if CONFIG_DELTA_Q
364 int current_q_index;
365#endif
Angie Chiangd4022822016-11-02 18:30:25 -0700366#if CONFIG_RD_DEBUG
Angie Chiang9a44f5f2016-11-06 12:19:06 -0800367 RD_STATS rd_stats;
Angie Chiangd4022822016-11-02 18:30:25 -0700368 int mi_row;
369 int mi_col;
370#endif
Yue Chen69f18e12016-09-08 14:48:15 -0700371#if CONFIG_WARPED_MOTION
372 int num_proj_ref[2];
373 WarpedMotionParams wm_params[2];
374#endif // CONFIG_WARPED_MOTION
Ryan Lei7386eda2016-12-08 21:08:31 -0800375#if CONFIG_DEBLOCKING_ACROSS_TILES
376 TILE_BOUNDARY_TYPE tile_boundary_info;
377#endif // CONFIG_DEBLOCKING_ACROSS_TILES
Yaowu Xuc27fc142016-08-22 16:08:15 -0700378} MB_MODE_INFO;
379
380typedef struct MODE_INFO {
381 MB_MODE_INFO mbmi;
382 b_mode_info bmi[4];
383} MODE_INFO;
384
385static INLINE PREDICTION_MODE get_y_mode(const MODE_INFO *mi, int block) {
Jingning Hand7d20472016-12-14 11:13:48 -0800386#if CONFIG_CB4X4
387 (void)block;
388 return mi->mbmi.mode;
389#else
Yaowu Xuc27fc142016-08-22 16:08:15 -0700390 return mi->mbmi.sb_type < BLOCK_8X8 ? mi->bmi[block].as_mode : mi->mbmi.mode;
Jingning Hand7d20472016-12-14 11:13:48 -0800391#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700392}
393
394static INLINE int is_inter_block(const MB_MODE_INFO *mbmi) {
395 return mbmi->ref_frame[0] > INTRA_FRAME;
396}
397
398static INLINE int has_second_ref(const MB_MODE_INFO *mbmi) {
399 return mbmi->ref_frame[1] > INTRA_FRAME;
400}
401
Yaowu Xuf883b422016-08-30 14:01:10 -0700402PREDICTION_MODE av1_left_block_mode(const MODE_INFO *cur_mi,
403 const MODE_INFO *left_mi, int b);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700404
Yaowu Xuf883b422016-08-30 14:01:10 -0700405PREDICTION_MODE av1_above_block_mode(const MODE_INFO *cur_mi,
406 const MODE_INFO *above_mi, int b);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700407
408enum mv_precision { MV_PRECISION_Q3, MV_PRECISION_Q4 };
409
410struct buf_2d {
411 uint8_t *buf;
412 uint8_t *buf0;
413 int width;
414 int height;
415 int stride;
416};
417
418typedef struct macroblockd_plane {
419 tran_low_t *dqcoeff;
420 PLANE_TYPE plane_type;
421 int subsampling_x;
422 int subsampling_y;
423 struct buf_2d dst;
424 struct buf_2d pre[2];
425 ENTROPY_CONTEXT *above_context;
426 ENTROPY_CONTEXT *left_context;
427 int16_t seg_dequant[MAX_SEGMENTS][2];
428#if CONFIG_NEW_QUANT
clang-format67948d32016-09-07 22:40:40 -0700429 dequant_val_type_nuq seg_dequant_nuq[MAX_SEGMENTS][QUANT_PROFILES]
430 [COEF_BANDS];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700431#endif
Urvang Joshib100db72016-10-12 16:28:56 -0700432#if CONFIG_PALETTE
Yaowu Xuc27fc142016-08-22 16:08:15 -0700433 uint8_t *color_index_map;
Urvang Joshib100db72016-10-12 16:28:56 -0700434#endif // CONFIG_PALETTE
Yaowu Xuc27fc142016-08-22 16:08:15 -0700435
436 // number of 4x4s in current block
437 uint16_t n4_w, n4_h;
438 // log2 of n4_w, n4_h
439 uint8_t n4_wl, n4_hl;
Jingning Hanc47fe6c2016-10-21 16:40:47 -0700440 // block size in pixels
441 uint8_t width, height;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700442
443#if CONFIG_AOM_QM
444 const qm_val_t *seg_iqmatrix[MAX_SEGMENTS][2][TX_SIZES];
445#endif
446 // encoder
447 const int16_t *dequant;
448#if CONFIG_NEW_QUANT
449 const dequant_val_type_nuq *dequant_val_nuq[QUANT_PROFILES];
450#endif // CONFIG_NEW_QUANT
451#if CONFIG_AOM_QM
452 const qm_val_t *seg_qmatrix[MAX_SEGMENTS][2][TX_SIZES];
453#endif
Yushin Cho77bba8d2016-11-04 16:36:56 -0700454
455#if CONFIG_PVQ
456 DECLARE_ALIGNED(16, int16_t, pred[MAX_SB_SQUARE]);
457 // PVQ: forward transformed predicted image, a reference for PVQ.
458 tran_low_t *pvq_ref_coeff;
459#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700460} MACROBLOCKD_PLANE;
461
Jingning Han3468df12016-12-05 17:53:16 -0800462#define BLOCK_OFFSET(x, i) \
463 ((x) + (i) * (1 << (tx_size_wide_log2[0] + tx_size_high_log2[0])))
Yaowu Xuc27fc142016-08-22 16:08:15 -0700464
465typedef struct RefBuffer {
466 // TODO(dkovalev): idx is not really required and should be removed, now it
Yaowu Xuf883b422016-08-30 14:01:10 -0700467 // is used in av1_onyxd_if.c
Yaowu Xuc27fc142016-08-22 16:08:15 -0700468 int idx;
469 YV12_BUFFER_CONFIG *buf;
470 struct scale_factors sf;
471} RefBuffer;
472
473typedef struct macroblockd {
474 struct macroblockd_plane plane[MAX_MB_PLANE];
475 uint8_t bmode_blocks_wl;
476 uint8_t bmode_blocks_hl;
477
478 FRAME_COUNTS *counts;
479 TileInfo tile;
480
481 int mi_stride;
482
483 MODE_INFO **mi;
484 MODE_INFO *left_mi;
485 MODE_INFO *above_mi;
486 MB_MODE_INFO *left_mbmi;
487 MB_MODE_INFO *above_mbmi;
488
489 int up_available;
490 int left_available;
491
Yaowu Xuf883b422016-08-30 14:01:10 -0700492 const aom_prob (*partition_probs)[PARTITION_TYPES - 1];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700493
494 /* Distance of MB away from frame edges */
495 int mb_to_left_edge;
496 int mb_to_right_edge;
497 int mb_to_top_edge;
498 int mb_to_bottom_edge;
499
500 FRAME_CONTEXT *fc;
501
502 /* pointers to reference frames */
Urvang Joshi52648442016-10-13 17:27:51 -0700503 const RefBuffer *block_refs[2];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700504
505 /* pointer to current frame */
506 const YV12_BUFFER_CONFIG *cur_buf;
507
508 ENTROPY_CONTEXT *above_context[MAX_MB_PLANE];
509 ENTROPY_CONTEXT left_context[MAX_MB_PLANE][2 * MAX_MIB_SIZE];
510
511 PARTITION_CONTEXT *above_seg_context;
512 PARTITION_CONTEXT left_seg_context[MAX_MIB_SIZE];
513
514#if CONFIG_VAR_TX
515 TXFM_CONTEXT *above_txfm_context;
516 TXFM_CONTEXT *left_txfm_context;
517 TXFM_CONTEXT left_txfm_context_buffer[MAX_MIB_SIZE];
518
519 TX_SIZE max_tx_size;
520#if CONFIG_SUPERTX
521 TX_SIZE supertx_size;
522#endif
523#endif
524
Jingning Hanff6ee6a2016-12-07 09:55:21 -0800525 // block dimension in the unit of mode_info.
Yaowu Xuc27fc142016-08-22 16:08:15 -0700526 uint8_t n8_w, n8_h;
527
528#if CONFIG_REF_MV
529 uint8_t ref_mv_count[MODE_CTX_REF_FRAMES];
530 CANDIDATE_MV ref_mv_stack[MODE_CTX_REF_FRAMES][MAX_REF_MV_STACK_SIZE];
531 uint8_t is_sec_rect;
532#endif
533
Yushin Cho77bba8d2016-11-04 16:36:56 -0700534#if CONFIG_PVQ
535 daala_dec_ctx daala_dec;
536#endif
Yaowu Xuf883b422016-08-30 14:01:10 -0700537#if CONFIG_AOM_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700538 /* Bit depth: 8, 10, 12 */
539 int bd;
540#endif
541
Debargha Mukherjee3c42c092016-09-29 09:17:36 -0700542 int qindex[MAX_SEGMENTS];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700543 int lossless[MAX_SEGMENTS];
544 int corrupted;
545
Yaowu Xuf883b422016-08-30 14:01:10 -0700546 struct aom_internal_error_info *error_info;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700547#if CONFIG_GLOBAL_MOTION
David Barkercf3d0b02016-11-10 10:14:49 +0000548 WarpedMotionParams *global_motion;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700549#endif // CONFIG_GLOBAL_MOTION
Arild Fuldseth07441162016-08-15 15:07:52 +0200550#if CONFIG_DELTA_Q
551 int prev_qindex;
552 int delta_qindex;
553 int current_qindex;
554#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700555} MACROBLOCKD;
556
557static INLINE BLOCK_SIZE get_subsize(BLOCK_SIZE bsize,
558 PARTITION_TYPE partition) {
559 if (partition == PARTITION_INVALID)
Urvang Joshicb586f32016-09-20 11:36:33 -0700560 return BLOCK_INVALID;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700561 else
562 return subsize_lookup[partition][bsize];
563}
564
565static const TX_TYPE intra_mode_to_tx_type_context[INTRA_MODES] = {
566 DCT_DCT, // DC
567 ADST_DCT, // V
568 DCT_ADST, // H
569 DCT_DCT, // D45
570 ADST_ADST, // D135
571 ADST_DCT, // D117
572 DCT_ADST, // D153
573 DCT_ADST, // D207
574 ADST_DCT, // D63
Urvang Joshi6be4a542016-11-03 15:24:05 -0700575#if CONFIG_ALT_INTRA
576 ADST_ADST, // SMOOTH
577#endif // CONFIG_ALT_INTRA
Yaowu Xuc27fc142016-08-22 16:08:15 -0700578 ADST_ADST, // TM
579};
580
581#if CONFIG_SUPERTX
582static INLINE int supertx_enabled(const MB_MODE_INFO *mbmi) {
Jingning Han93531242016-12-20 11:54:36 -0800583 TX_SIZE max_tx_size = txsize_sqr_map[mbmi->tx_size];
584 return tx_size_wide[max_tx_size] >
585 AOMMIN(block_size_wide[mbmi->sb_type], block_size_high[mbmi->sb_type]);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700586}
587#endif // CONFIG_SUPERTX
588
Yaowu Xuc27fc142016-08-22 16:08:15 -0700589#if CONFIG_EXT_TX
Debargha Mukherjee5a488a62016-11-22 22:24:10 -0800590
Yaowu Xuc27fc142016-08-22 16:08:15 -0700591#define ALLOW_INTRA_EXT_TX 1
Yaowu Xuc27fc142016-08-22 16:08:15 -0700592
593static const int num_ext_tx_set_inter[EXT_TX_SETS_INTER] = { 1, 16, 12, 2 };
594static const int num_ext_tx_set_intra[EXT_TX_SETS_INTRA] = { 1, 7, 5 };
595
Yaowu Xuc27fc142016-08-22 16:08:15 -0700596static INLINE int get_ext_tx_set(TX_SIZE tx_size, BLOCK_SIZE bs, int is_inter) {
597 tx_size = txsize_sqr_map[tx_size];
Jingning Han1a00cff2016-12-28 14:53:14 -0800598#if CONFIG_CB4X4
599 (void)bs;
600 if (tx_size > TX_32X32) return 0;
601#else
Yaowu Xuc27fc142016-08-22 16:08:15 -0700602 if (tx_size > TX_32X32 || bs < BLOCK_8X8) return 0;
Jingning Han1a00cff2016-12-28 14:53:14 -0800603#endif
Debargha Mukherjee3b52b3a2016-08-30 15:55:23 -0700604 if (tx_size == TX_32X32) return is_inter ? 3 : 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700605 return (tx_size == TX_16X16 ? 2 : 1);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700606}
607
Debargha Mukherjee5a488a62016-11-22 22:24:10 -0800608static const int use_intra_ext_tx_for_txsize[EXT_TX_SETS_INTRA]
609 [EXT_TX_SIZES] = {
Jingning Han1a00cff2016-12-28 14:53:14 -0800610#if CONFIG_CB4X4
611 { 1, 1, 1, 1, 1 }, // unused
612 { 0, 1, 1, 0, 0 },
613 { 0, 0, 0, 1, 0 },
614#else
Debargha Mukherjee5a488a62016-11-22 22:24:10 -0800615 { 1, 1, 1, 1 }, // unused
616 { 1, 1, 0, 0 },
617 { 0, 0, 1, 0 },
Jingning Han1a00cff2016-12-28 14:53:14 -0800618#endif // CONFIG_CB4X4
Debargha Mukherjee5a488a62016-11-22 22:24:10 -0800619 };
Yaowu Xuc27fc142016-08-22 16:08:15 -0700620
Debargha Mukherjee5a488a62016-11-22 22:24:10 -0800621static const int use_inter_ext_tx_for_txsize[EXT_TX_SETS_INTER]
622 [EXT_TX_SIZES] = {
Jingning Han1a00cff2016-12-28 14:53:14 -0800623#if CONFIG_CB4X4
624 { 1, 1, 1, 1, 1 }, // unused
625 { 0, 1, 1, 0, 0 },
626 { 0, 0, 0, 1, 0 },
627 { 0, 0, 0, 0, 1 },
628#else
Debargha Mukherjee5a488a62016-11-22 22:24:10 -0800629 { 1, 1, 1, 1 }, // unused
630 { 1, 1, 0, 0 },
631 { 0, 0, 1, 0 },
632 { 0, 0, 0, 1 },
Jingning Han1a00cff2016-12-28 14:53:14 -0800633#endif // CONFIG_CB4X4
Debargha Mukherjee5a488a62016-11-22 22:24:10 -0800634 };
Yaowu Xuc27fc142016-08-22 16:08:15 -0700635
636// Transform types used in each intra set
637static const int ext_tx_used_intra[EXT_TX_SETS_INTRA][TX_TYPES] = {
638 { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
639 { 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0 },
640 { 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 },
641};
642
643// Transform types used in each inter set
644static const int ext_tx_used_inter[EXT_TX_SETS_INTER][TX_TYPES] = {
645 { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
646 { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 },
647 { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 },
648 { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 },
649};
650
651// 1D Transforms used in inter set, this needs to be changed if
652// ext_tx_used_inter is changed
653static const int ext_tx_used_inter_1D[EXT_TX_SETS_INTER][TX_TYPES_1D] = {
654 { 1, 0, 0, 0 }, { 1, 1, 1, 1 }, { 1, 1, 1, 1 }, { 1, 0, 0, 1 },
655};
656
657static INLINE int get_ext_tx_types(TX_SIZE tx_size, BLOCK_SIZE bs,
658 int is_inter) {
659 const int set = get_ext_tx_set(tx_size, bs, is_inter);
660 return is_inter ? num_ext_tx_set_inter[set] : num_ext_tx_set_intra[set];
661}
662
663#if CONFIG_RECT_TX
664static INLINE int is_rect_tx_allowed_bsize(BLOCK_SIZE bsize) {
665 static const char LUT[BLOCK_SIZES] = {
666 0, // BLOCK_4X4
667 1, // BLOCK_4X8
668 1, // BLOCK_8X4
669 0, // BLOCK_8X8
670 1, // BLOCK_8X16
671 1, // BLOCK_16X8
672 0, // BLOCK_16X16
673 1, // BLOCK_16X32
674 1, // BLOCK_32X16
675 0, // BLOCK_32X32
676 0, // BLOCK_32X64
677 0, // BLOCK_64X32
678 0, // BLOCK_64X64
679#if CONFIG_EXT_PARTITION
680 0, // BLOCK_64X128
681 0, // BLOCK_128X64
682 0, // BLOCK_128X128
683#endif // CONFIG_EXT_PARTITION
684 };
685
686 return LUT[bsize];
687}
688
Yue Chen49587a72016-09-28 17:09:47 -0700689static INLINE int is_rect_tx_allowed(const MACROBLOCKD *xd,
690 const MB_MODE_INFO *mbmi) {
Urvang Joshifeb925f2016-12-05 10:37:29 -0800691 return is_rect_tx_allowed_bsize(mbmi->sb_type) &&
Yue Chen49587a72016-09-28 17:09:47 -0700692 !xd->lossless[mbmi->segment_id];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700693}
694
695static INLINE int is_rect_tx(TX_SIZE tx_size) { return tx_size >= TX_SIZES; }
696#endif // CONFIG_RECT_TX
697#endif // CONFIG_EXT_TX
698
699static INLINE TX_SIZE tx_size_from_tx_mode(BLOCK_SIZE bsize, TX_MODE tx_mode,
700 int is_inter) {
701 const TX_SIZE largest_tx_size = tx_mode_to_biggest_tx_size[tx_mode];
Urvang Joshifeb925f2016-12-05 10:37:29 -0800702#if CONFIG_VAR_TX || (CONFIG_EXT_TX && CONFIG_RECT_TX)
703 const TX_SIZE max_rect_tx_size = max_txsize_rect_lookup[bsize];
Jingning Han70e5f3f2016-11-09 17:03:07 -0800704#else
Yaowu Xuc27fc142016-08-22 16:08:15 -0700705 const TX_SIZE max_tx_size = max_txsize_lookup[bsize];
Urvang Joshifeb925f2016-12-05 10:37:29 -0800706#endif // CONFIG_VAR_TX || (CONFIG_EXT_TX && CONFIG_RECT_TX)
707 (void)is_inter;
708#if CONFIG_VAR_TX
709#if CONFIG_CB4X4
710 if (bsize == BLOCK_4X4)
711 return AOMMIN(max_txsize_lookup[bsize], largest_tx_size);
712#else
713 if (bsize < BLOCK_8X8)
714 return AOMMIN(max_txsize_lookup[bsize], largest_tx_size);
Jingning Han70e5f3f2016-11-09 17:03:07 -0800715#endif
Urvang Joshifeb925f2016-12-05 10:37:29 -0800716 if (txsize_sqr_map[max_rect_tx_size] <= largest_tx_size)
717 return max_rect_tx_size;
718 else
719 return largest_tx_size;
720#elif CONFIG_EXT_TX && CONFIG_RECT_TX
721 if (txsize_sqr_up_map[max_rect_tx_size] <= largest_tx_size) {
722 return max_rect_tx_size;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700723 } else {
Urvang Joshifeb925f2016-12-05 10:37:29 -0800724 return largest_tx_size;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700725 }
726#else
Yaowu Xuf883b422016-08-30 14:01:10 -0700727 return AOMMIN(max_tx_size, largest_tx_size);
Urvang Joshifeb925f2016-12-05 10:37:29 -0800728#endif // CONFIG_VAR_TX
Yaowu Xuc27fc142016-08-22 16:08:15 -0700729}
730
hui su5db97432016-10-14 16:10:14 -0700731#if CONFIG_FILTER_INTRA
Yaowu Xuc27fc142016-08-22 16:08:15 -0700732static const TX_TYPE filter_intra_mode_to_tx_type_lookup[FILTER_INTRA_MODES] = {
733 DCT_DCT, // FILTER_DC
734 ADST_DCT, // FILTER_V
735 DCT_ADST, // FILTER_H
736 DCT_DCT, // FILTER_D45
737 ADST_ADST, // FILTER_D135
738 ADST_DCT, // FILTER_D117
739 DCT_ADST, // FILTER_D153
740 DCT_ADST, // FILTER_D207
741 ADST_DCT, // FILTER_D63
742 ADST_ADST, // FILTER_TM
743};
hui su5db97432016-10-14 16:10:14 -0700744#endif // CONFIG_FILTER_INTRA
Yaowu Xuc27fc142016-08-22 16:08:15 -0700745
hui su5db97432016-10-14 16:10:14 -0700746#if CONFIG_EXT_INTRA
hui su45dc5972016-12-08 17:42:50 -0800747#define MAX_ANGLE_DELTA_UV 2
748#define ANGLE_STEP_UV 4
749
750static const uint8_t av1_angle_step_y[TX_SIZES] = {
751 0, 4, 3, 3,
752};
753static const uint8_t av1_max_angle_delta_y[TX_SIZES] = {
754 0, 2, 3, 3,
755};
756
hui su5db97432016-10-14 16:10:14 -0700757extern const int16_t dr_intra_derivative[90];
758static const uint8_t mode_to_angle_map[INTRA_MODES] = {
759 0, 90, 180, 45, 135, 111, 157, 203, 67, 0,
760};
761
hui su45dc5972016-12-08 17:42:50 -0800762static INLINE int av1_get_angle_step(BLOCK_SIZE sb_type, int plane) {
763 const TX_SIZE max_tx_size = max_txsize_lookup[sb_type];
764 return plane ? ANGLE_STEP_UV : av1_angle_step_y[max_tx_size];
765}
766
767static INLINE int av1_get_max_angle_delta(BLOCK_SIZE sb_type, int plane) {
768 const TX_SIZE max_tx_size = max_txsize_lookup[sb_type];
769 return plane ? MAX_ANGLE_DELTA_UV : av1_max_angle_delta_y[max_tx_size];
770}
771
hui sueda3d762016-12-06 16:58:23 -0800772#if CONFIG_INTRA_INTERP
hui su5db97432016-10-14 16:10:14 -0700773// Returns whether filter selection is needed for a given
774// intra prediction angle.
Yaowu Xuf883b422016-08-30 14:01:10 -0700775int av1_is_intra_filter_switchable(int angle);
hui sueda3d762016-12-06 16:58:23 -0800776#endif // CONFIG_INTRA_INTERP
Yaowu Xuc27fc142016-08-22 16:08:15 -0700777#endif // CONFIG_EXT_INTRA
778
779#if CONFIG_EXT_TILE
780#define FIXED_TX_TYPE 1
781#else
782#define FIXED_TX_TYPE 0
783#endif
784
785static INLINE TX_TYPE get_default_tx_type(PLANE_TYPE plane_type,
786 const MACROBLOCKD *xd, int block_idx,
787 TX_SIZE tx_size) {
788 const MB_MODE_INFO *const mbmi = &xd->mi[0]->mbmi;
789
790 if (is_inter_block(mbmi) || plane_type != PLANE_TYPE_Y ||
791 xd->lossless[mbmi->segment_id] || tx_size >= TX_32X32)
792 return DCT_DCT;
793
794 return intra_mode_to_tx_type_context[plane_type == PLANE_TYPE_Y
795 ? get_y_mode(xd->mi[0], block_idx)
796 : mbmi->uv_mode];
797}
798
799static INLINE TX_TYPE get_tx_type(PLANE_TYPE plane_type, const MACROBLOCKD *xd,
800 int block_idx, TX_SIZE tx_size) {
801 const MODE_INFO *const mi = xd->mi[0];
802 const MB_MODE_INFO *const mbmi = &mi->mbmi;
803
804 if (FIXED_TX_TYPE)
805 return get_default_tx_type(plane_type, xd, block_idx, tx_size);
806
hui su5db97432016-10-14 16:10:14 -0700807#if CONFIG_EXT_INTRA || CONFIG_FILTER_INTRA
Yaowu Xuc27fc142016-08-22 16:08:15 -0700808 if (!is_inter_block(mbmi)) {
hui su5db97432016-10-14 16:10:14 -0700809#if CONFIG_FILTER_INTRA
810 const int use_filter_intra_mode_info =
811 mbmi->filter_intra_mode_info.use_filter_intra_mode[plane_type];
812 const FILTER_INTRA_MODE filter_intra_mode =
813 mbmi->filter_intra_mode_info.filter_intra_mode[plane_type];
814#endif // CONFIG_FILTER_INTRA
815#if CONFIG_EXT_INTRA
Yaowu Xuc27fc142016-08-22 16:08:15 -0700816 const PREDICTION_MODE mode = (plane_type == PLANE_TYPE_Y)
817 ? get_y_mode(mi, block_idx)
818 : mbmi->uv_mode;
hui su5db97432016-10-14 16:10:14 -0700819#endif // CONFIG_EXT_INTRA
Yaowu Xuc27fc142016-08-22 16:08:15 -0700820
821 if (xd->lossless[mbmi->segment_id] || tx_size >= TX_32X32) return DCT_DCT;
822
823#if CONFIG_EXT_TX
824#if ALLOW_INTRA_EXT_TX
825 if (mbmi->sb_type >= BLOCK_8X8 && plane_type == PLANE_TYPE_Y)
826 return mbmi->tx_type;
827#endif // ALLOW_INTRA_EXT_TX
828#endif // CONFIG_EXT_TX
829
hui su5db97432016-10-14 16:10:14 -0700830#if CONFIG_FILTER_INTRA
831 if (use_filter_intra_mode_info)
832 return filter_intra_mode_to_tx_type_lookup[filter_intra_mode];
833#endif // CONFIG_FILTER_INTRA
834#if CONFIG_EXT_INTRA
hui su45dc5972016-12-08 17:42:50 -0800835#if CONFIG_ALT_INTRA
836 if (mode == SMOOTH_PRED) return ADST_ADST;
837#endif // CONFIG_ALT_INTRA
838 if (mode == DC_PRED) return DCT_DCT;
839 if (mode == TM_PRED) return ADST_ADST;
840 {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700841 int angle = mode_to_angle_map[mode];
hui su45dc5972016-12-08 17:42:50 -0800842 const int angle_step = av1_get_angle_step(mbmi->sb_type, (int)plane_type);
843 assert(mode == D45_PRED || mode == D63_PRED || mode == D117_PRED ||
844 mode == D135_PRED || mode == D153_PRED || mode == D207_PRED ||
845 mode == V_PRED || mode == H_PRED);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700846 if (mbmi->sb_type >= BLOCK_8X8)
hui su45dc5972016-12-08 17:42:50 -0800847 angle += mbmi->angle_delta[plane_type] * angle_step;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700848 assert(angle > 0 && angle < 270);
849 if (angle == 135)
850 return ADST_ADST;
851 else if (angle < 45 || angle > 225)
852 return DCT_DCT;
853 else if (angle < 135)
854 return ADST_DCT;
855 else
856 return DCT_ADST;
857 }
Yaowu Xuc27fc142016-08-22 16:08:15 -0700858#endif // CONFIG_EXT_INTRA
hui su5db97432016-10-14 16:10:14 -0700859 }
860#endif // CONFIG_EXT_INTRA || CONFIG_FILTER_INTRA
Yaowu Xuc27fc142016-08-22 16:08:15 -0700861
862#if CONFIG_EXT_TX
Yaowu Xuc27fc142016-08-22 16:08:15 -0700863 if (xd->lossless[mbmi->segment_id] || txsize_sqr_map[tx_size] > TX_32X32 ||
864 (txsize_sqr_map[tx_size] >= TX_32X32 && !is_inter_block(mbmi)))
Yaowu Xuc27fc142016-08-22 16:08:15 -0700865 return DCT_DCT;
Jingning Han8260d8b2016-12-28 13:48:43 -0800866 if (mbmi->sb_type >= BLOCK_8X8 || CONFIG_CB4X4) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700867 if (plane_type == PLANE_TYPE_Y) {
868#if !ALLOW_INTRA_EXT_TX
869 if (is_inter_block(mbmi))
870#endif // ALLOW_INTRA_EXT_TX
871 return mbmi->tx_type;
872 }
Jingning Han1a00cff2016-12-28 14:53:14 -0800873
874 if (is_inter_block(mbmi)) {
875// UV Inter only
876#if CONFIG_CB4X4
877 if (tx_size < TX_4X4) return DCT_DCT;
878#endif
Debargha Mukherjee5a488a62016-11-22 22:24:10 -0800879 return (mbmi->tx_type == IDTX && txsize_sqr_map[tx_size] >= TX_32X32)
Yaowu Xuc27fc142016-08-22 16:08:15 -0700880 ? DCT_DCT
881 : mbmi->tx_type;
Jingning Han1a00cff2016-12-28 14:53:14 -0800882 }
Yaowu Xuc27fc142016-08-22 16:08:15 -0700883 }
884
Jingning Han8260d8b2016-12-28 13:48:43 -0800885#if CONFIG_CB4X4
Jingning Han1a00cff2016-12-28 14:53:14 -0800886 if (tx_size < TX_4X4)
887 return DCT_DCT;
888 else
889 return intra_mode_to_tx_type_context[mbmi->uv_mode];
Jingning Han8260d8b2016-12-28 13:48:43 -0800890#endif
891
Yaowu Xuc27fc142016-08-22 16:08:15 -0700892 // Sub8x8-Inter/Intra OR UV-Intra
893 if (is_inter_block(mbmi)) // Sub8x8-Inter
894 return DCT_DCT;
895 else // Sub8x8 Intra OR UV-Intra
896 return intra_mode_to_tx_type_context[plane_type == PLANE_TYPE_Y
897 ? get_y_mode(mi, block_idx)
898 : mbmi->uv_mode];
899#else // CONFIG_EXT_TX
900 (void)block_idx;
901 if (plane_type != PLANE_TYPE_Y || xd->lossless[mbmi->segment_id] ||
902 txsize_sqr_map[tx_size] >= TX_32X32)
903 return DCT_DCT;
904 return mbmi->tx_type;
905#endif // CONFIG_EXT_TX
906}
907
Yaowu Xuf883b422016-08-30 14:01:10 -0700908void av1_setup_block_planes(MACROBLOCKD *xd, int ss_x, int ss_y);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700909
Jingning Han4e1737a2016-10-25 16:05:02 -0700910static INLINE int tx_size_to_depth(const TX_SIZE tx_size) {
911 return (int)(tx_size - TX_4X4);
912}
913
914static INLINE TX_SIZE depth_to_tx_size(const int depth) {
915 return (TX_SIZE)(depth + TX_4X4);
916}
917
Yaowu Xuc27fc142016-08-22 16:08:15 -0700918static INLINE TX_SIZE get_uv_tx_size(const MB_MODE_INFO *mbmi,
919 const struct macroblockd_plane *pd) {
Debargha Mukherjee2f123402016-08-30 17:43:38 -0700920 TX_SIZE uv_txsize;
Jingning Han93531242016-12-20 11:54:36 -0800921#if CONFIG_CB4X4
922 assert(mbmi->tx_size > TX_2X2);
923#endif
924
Yaowu Xuc27fc142016-08-22 16:08:15 -0700925#if CONFIG_SUPERTX
926 if (supertx_enabled(mbmi))
927 return uvsupertx_size_lookup[txsize_sqr_map[mbmi->tx_size]]
928 [pd->subsampling_x][pd->subsampling_y];
929#endif // CONFIG_SUPERTX
Jingning Hancabd9892016-12-01 12:28:42 -0800930
Debargha Mukherjee2f123402016-08-30 17:43:38 -0700931 uv_txsize = uv_txsize_lookup[mbmi->sb_type][mbmi->tx_size][pd->subsampling_x]
932 [pd->subsampling_y];
933 assert(uv_txsize != TX_INVALID);
934 return uv_txsize;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700935}
936
937static INLINE BLOCK_SIZE
938get_plane_block_size(BLOCK_SIZE bsize, const struct macroblockd_plane *pd) {
939 return ss_size_lookup[bsize][pd->subsampling_x][pd->subsampling_y];
940}
941
942static INLINE void reset_skip_context(MACROBLOCKD *xd, BLOCK_SIZE bsize) {
943 int i;
944 for (i = 0; i < MAX_MB_PLANE; i++) {
945 struct macroblockd_plane *const pd = &xd->plane[i];
946 const BLOCK_SIZE plane_bsize = get_plane_block_size(bsize, pd);
Jingning Hanb49004d2016-12-05 09:37:29 -0800947 const int txs_wide = block_size_wide[plane_bsize] >> tx_size_wide_log2[0];
948 const int txs_high = block_size_high[plane_bsize] >> tx_size_high_log2[0];
949 memset(pd->above_context, 0, sizeof(ENTROPY_CONTEXT) * txs_wide);
950 memset(pd->left_context, 0, sizeof(ENTROPY_CONTEXT) * txs_high);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700951 }
952}
953
954typedef void (*foreach_transformed_block_visitor)(int plane, int block,
955 int blk_row, int blk_col,
956 BLOCK_SIZE plane_bsize,
957 TX_SIZE tx_size, void *arg);
958
Yaowu Xuf883b422016-08-30 14:01:10 -0700959void av1_foreach_transformed_block_in_plane(
Yaowu Xuc27fc142016-08-22 16:08:15 -0700960 const MACROBLOCKD *const xd, BLOCK_SIZE bsize, int plane,
961 foreach_transformed_block_visitor visit, void *arg);
962
Yaowu Xuf883b422016-08-30 14:01:10 -0700963void av1_foreach_transformed_block(const MACROBLOCKD *const xd,
964 BLOCK_SIZE bsize,
965 foreach_transformed_block_visitor visit,
966 void *arg);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700967
iole moccagattaf25a4cf2016-11-11 23:57:57 -0800968#if CONFIG_COEF_INTERLEAVE
969static INLINE int get_max_4x4_size(int num_4x4, int mb_to_edge,
970 int subsampling) {
971 return num_4x4 + (mb_to_edge >= 0 ? 0 : mb_to_edge >> (5 + subsampling));
972}
973
974void av1_foreach_transformed_block_interleave(
975 const MACROBLOCKD *const xd, BLOCK_SIZE bsize,
976 foreach_transformed_block_visitor visit, void *arg);
977#endif
978
Yaowu Xuf883b422016-08-30 14:01:10 -0700979void av1_set_contexts(const MACROBLOCKD *xd, struct macroblockd_plane *pd,
Jingning Haneee43152016-12-05 09:58:45 -0800980 int plane, TX_SIZE tx_size, int has_eob, int aoff,
981 int loff);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700982
983#if CONFIG_EXT_INTER
984static INLINE int is_interintra_allowed_bsize(const BLOCK_SIZE bsize) {
David Barkerac37fa32016-12-02 12:30:21 +0000985#if !USE_RECT_INTERINTRA
986 if (block_size_wide[bsize] != block_size_high[bsize]) return 0;
987#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700988 // TODO(debargha): Should this be bsize < BLOCK_LARGEST?
989 return (bsize >= BLOCK_8X8) && (bsize < BLOCK_64X64);
990}
991
992static INLINE int is_interintra_allowed_mode(const PREDICTION_MODE mode) {
993 return (mode >= NEARESTMV) && (mode <= NEWMV);
994}
995
996static INLINE int is_interintra_allowed_ref(const MV_REFERENCE_FRAME rf[2]) {
997 return (rf[0] > INTRA_FRAME) && (rf[1] <= INTRA_FRAME);
998}
999
1000static INLINE int is_interintra_allowed(const MB_MODE_INFO *mbmi) {
1001 return is_interintra_allowed_bsize(mbmi->sb_type) &&
1002 is_interintra_allowed_mode(mbmi->mode) &&
1003 is_interintra_allowed_ref(mbmi->ref_frame);
1004}
1005
1006static INLINE int is_interintra_allowed_bsize_group(const int group) {
1007 int i;
1008 for (i = 0; i < BLOCK_SIZES; i++) {
Urvang Joshicb586f32016-09-20 11:36:33 -07001009 if (size_group_lookup[i] == group &&
1010 is_interintra_allowed_bsize((BLOCK_SIZE)i)) {
Yaowu Xuc27fc142016-08-22 16:08:15 -07001011 return 1;
Urvang Joshicb586f32016-09-20 11:36:33 -07001012 }
Yaowu Xuc27fc142016-08-22 16:08:15 -07001013 }
1014 return 0;
1015}
1016
1017static INLINE int is_interintra_pred(const MB_MODE_INFO *mbmi) {
1018 return (mbmi->ref_frame[1] == INTRA_FRAME) && is_interintra_allowed(mbmi);
1019}
1020#endif // CONFIG_EXT_INTER
1021
Yue Chencb60b182016-10-13 15:18:22 -07001022#if CONFIG_MOTION_VAR || CONFIG_WARPED_MOTION
1023static INLINE int is_motion_variation_allowed_bsize(BLOCK_SIZE bsize) {
1024 return (bsize >= BLOCK_8X8);
1025}
1026
Yue Chen69f18e12016-09-08 14:48:15 -07001027static INLINE MOTION_MODE motion_mode_allowed(const MB_MODE_INFO *mbmi) {
Yaowu Xuc27fc142016-08-22 16:08:15 -07001028#if CONFIG_EXT_INTER
Yue Chen69f18e12016-09-08 14:48:15 -07001029 if (is_motion_variation_allowed_bsize(mbmi->sb_type) &&
1030 is_inter_mode(mbmi->mode) && mbmi->ref_frame[1] != INTRA_FRAME) {
Yaowu Xuc27fc142016-08-22 16:08:15 -07001031#else
Yue Chen69f18e12016-09-08 14:48:15 -07001032 if (is_motion_variation_allowed_bsize(mbmi->sb_type) &&
1033 is_inter_mode(mbmi->mode)) {
Yaowu Xuc27fc142016-08-22 16:08:15 -07001034#endif // CONFIG_EXT_INTER
Yue Chen69f18e12016-09-08 14:48:15 -07001035#if CONFIG_WARPED_MOTION
1036 if (!has_second_ref(mbmi) && mbmi->num_proj_ref[0] >= 3)
1037 return WARPED_CAUSAL;
1038 else
1039#endif // CONFIG_WARPED_MOTION
1040#if CONFIG_MOTION_VAR
1041 return OBMC_CAUSAL;
1042#else
1043 return SIMPLE_TRANSLATION;
1044#endif // CONFIG_MOTION_VAR
1045 } else {
1046 return SIMPLE_TRANSLATION;
1047 }
Yaowu Xuc27fc142016-08-22 16:08:15 -07001048}
1049
Yue Chencb60b182016-10-13 15:18:22 -07001050#if CONFIG_MOTION_VAR
Yaowu Xuc27fc142016-08-22 16:08:15 -07001051static INLINE int is_neighbor_overlappable(const MB_MODE_INFO *mbmi) {
1052 return (is_inter_block(mbmi));
1053}
Yue Chencb60b182016-10-13 15:18:22 -07001054#endif // CONFIG_MOTION_VAR
1055#endif // CONFIG_MOTION_VAR || CONFIG_WARPED_MOTION
Yaowu Xuc27fc142016-08-22 16:08:15 -07001056
1057#ifdef __cplusplus
1058} // extern "C"
1059#endif
1060
Yaowu Xuf883b422016-08-30 14:01:10 -07001061#endif // AV1_COMMON_BLOCKD_H_