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Yaowu Xuc27fc142016-08-22 16:08:15 -07001/*
Yaowu Xu2ab7ff02016-09-02 12:04:54 -07002 * Copyright (c) 2016, Alliance for Open Media. All rights reserved
Yaowu Xuc27fc142016-08-22 16:08:15 -07003 *
Yaowu Xu2ab7ff02016-09-02 12:04:54 -07004 * This source code is subject to the terms of the BSD 2 Clause License and
5 * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
6 * was not distributed with this source code in the LICENSE file, you can
7 * obtain it at www.aomedia.org/license/software. If the Alliance for Open
8 * Media Patent License 1.0 was not distributed with this source code in the
9 * PATENTS file, you can obtain it at www.aomedia.org/license/patent.
Yaowu Xuc27fc142016-08-22 16:08:15 -070010 */
11
12#include <assert.h>
13#include <math.h>
14#include <stdio.h>
15
Yaowu Xuf883b422016-08-30 14:01:10 -070016#include "./av1_rtcd.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070017
Yaowu Xuf883b422016-08-30 14:01:10 -070018#include "aom_dsp/aom_dsp_common.h"
19#include "aom_mem/aom_mem.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070020#include "aom_ports/bitops.h"
21#include "aom_ports/mem.h"
22#include "aom_ports/system_state.h"
23
24#include "av1/common/common.h"
25#include "av1/common/entropy.h"
26#include "av1/common/entropymode.h"
27#include "av1/common/mvref_common.h"
28#include "av1/common/pred_common.h"
29#include "av1/common/quant_common.h"
30#include "av1/common/reconinter.h"
31#include "av1/common/reconintra.h"
32#include "av1/common/seg_common.h"
33
Tom Finegan17ce8b12017-02-08 12:46:31 -080034#include "av1/encoder/av1_quantize.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070035#include "av1/encoder/cost.h"
36#include "av1/encoder/encodemb.h"
37#include "av1/encoder/encodemv.h"
38#include "av1/encoder/encoder.h"
39#include "av1/encoder/mcomp.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070040#include "av1/encoder/ratectrl.h"
41#include "av1/encoder/rd.h"
42#include "av1/encoder/tokenize.h"
43
44#define RD_THRESH_POW 1.25
45
46// Factor to weigh the rate for switchable interp filters.
47#define SWITCHABLE_INTERP_RATE_FACTOR 1
48
Yaowu Xuc27fc142016-08-22 16:08:15 -070049// The baseline rd thresholds for breaking out of the rd loop for
50// certain modes are assumed to be based on 8x8 blocks.
51// This table is used to correct for block size.
52// The factors here are << 2 (2 = x0.5, 32 = x8 etc).
Rupert Swarbrick93c39e92017-07-12 11:11:02 +010053static const uint8_t rd_thresh_block_size_factor[BLOCK_SIZES_ALL] = {
Timothy B. Terriberry81ec2612017-04-26 16:53:47 -070054#if CONFIG_CHROMA_2X2 || CONFIG_CHROMA_SUB8X8
Jingning Hanf1702dd2016-11-30 21:17:59 -080055 2, 2, 2,
56#endif
Rupert Swarbrick72678572017-08-02 12:05:26 +010057 2, 3, 3, 4, 6, 6, 8, 12, 12, 16, 24, 24, 32,
Yaowu Xuc27fc142016-08-22 16:08:15 -070058#if CONFIG_EXT_PARTITION
Rupert Swarbrick93c39e92017-07-12 11:11:02 +010059 48, 48, 64,
Yaowu Xuc27fc142016-08-22 16:08:15 -070060#endif // CONFIG_EXT_PARTITION
Rupert Swarbrick72678572017-08-02 12:05:26 +010061 4, 4, 8, 8, 16, 16
Yaowu Xuc27fc142016-08-22 16:08:15 -070062};
63
Yue Chenb23d00a2017-07-28 17:01:21 -070064void av1_fill_mode_rates(AV1_COMMON *const cm, MACROBLOCK *x,
65 FRAME_CONTEXT *fc) {
Yaowu Xuc27fc142016-08-22 16:08:15 -070066 int i, j;
67
Yue Chenb23d00a2017-07-28 17:01:21 -070068 if (cm->frame_type == KEY_FRAME) {
Yue Chenb23d00a2017-07-28 17:01:21 -070069 for (i = 0; i < PARTITION_CONTEXTS_PRIMARY; ++i)
Yue Chenba47c842017-08-02 16:07:59 -070070 av1_cost_tokens_from_cdf(x->partition_cost[i], fc->partition_cdf[i],
71 NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -070072#if CONFIG_UNPOISON_PARTITION_CTX
73 for (; i < PARTITION_CONTEXTS_PRIMARY + PARTITION_BLOCK_SIZES; ++i) {
74 aom_prob p = fc->partition_prob[i][PARTITION_VERT];
75 assert(p > 0);
76 x->partition_cost[i][PARTITION_NONE] = INT_MAX;
77 x->partition_cost[i][PARTITION_HORZ] = INT_MAX;
78 x->partition_cost[i][PARTITION_VERT] = av1_cost_bit(p, 0);
79 x->partition_cost[i][PARTITION_SPLIT] = av1_cost_bit(p, 1);
80 }
81 for (; i < PARTITION_CONTEXTS_PRIMARY + 2 * PARTITION_BLOCK_SIZES; ++i) {
82 aom_prob p = fc->partition_prob[i][PARTITION_HORZ];
83 assert(p > 0);
84 x->partition_cost[i][PARTITION_NONE] = INT_MAX;
85 x->partition_cost[i][PARTITION_HORZ] = av1_cost_bit(p, 0);
86 x->partition_cost[i][PARTITION_VERT] = INT_MAX;
87 x->partition_cost[i][PARTITION_SPLIT] = av1_cost_bit(p, 1);
88 }
89 x->partition_cost[PARTITION_CONTEXTS][PARTITION_NONE] = INT_MAX;
90 x->partition_cost[PARTITION_CONTEXTS][PARTITION_HORZ] = INT_MAX;
91 x->partition_cost[PARTITION_CONTEXTS][PARTITION_VERT] = INT_MAX;
92 x->partition_cost[PARTITION_CONTEXTS][PARTITION_SPLIT] = 0;
93#endif // CONFIG_UNPOISON_PARTITION_CTX
94 }
95
Yaowu Xuc27fc142016-08-22 16:08:15 -070096 for (i = 0; i < INTRA_MODES; ++i)
97 for (j = 0; j < INTRA_MODES; ++j)
Yue Chenb23d00a2017-07-28 17:01:21 -070098 av1_cost_tokens_from_cdf(x->y_mode_costs[i][j], av1_kf_y_mode_cdf[i][j],
Nathan E. Egge693eedd2017-06-29 20:01:58 -040099 av1_intra_mode_inv);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700100
101 for (i = 0; i < BLOCK_SIZE_GROUPS; ++i)
Yue Chenb23d00a2017-07-28 17:01:21 -0700102 av1_cost_tokens_from_cdf(x->mbmode_cost[i], fc->y_mode_cdf[i],
Nathan E. Egge693eedd2017-06-29 20:01:58 -0400103 av1_intra_mode_inv);
Luc Trudeau6e1cd782017-06-21 13:52:36 -0400104 const int *uv_mode_inv_map =
105#if CONFIG_CFL
106 // CfL codes the uv_mode without reordering it
107 NULL;
108#else
109 av1_intra_mode_inv;
110#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700111 for (i = 0; i < INTRA_MODES; ++i)
Yue Chenb23d00a2017-07-28 17:01:21 -0700112 av1_cost_tokens_from_cdf(x->intra_uv_mode_cost[i], fc->uv_mode_cdf[i],
Luc Trudeau6e1cd782017-06-21 13:52:36 -0400113 uv_mode_inv_map);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700114
115 for (i = 0; i < SWITCHABLE_FILTER_CONTEXTS; ++i)
Yue Chenba47c842017-08-02 16:07:59 -0700116 av1_cost_tokens_from_cdf(x->switchable_interp_costs[i],
117 fc->switchable_interp_cdf[i],
118 av1_switchable_interp_inv);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700119
120 for (i = 0; i < PALETTE_BLOCK_SIZES; ++i) {
Yue Chenb23d00a2017-07-28 17:01:21 -0700121 av1_cost_tokens_from_cdf(x->palette_y_size_cost[i],
hui su466ae062017-07-25 16:55:51 -0700122 fc->palette_y_size_cdf[i], NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700123 av1_cost_tokens_from_cdf(x->palette_uv_size_cost[i],
hui su466ae062017-07-25 16:55:51 -0700124 fc->palette_uv_size_cdf[i], NULL);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700125 }
126
Alex Converse92109812017-02-22 10:21:40 -0800127 for (i = 0; i < PALETTE_SIZES; ++i) {
Urvang Joshi23a61112017-01-30 14:59:27 -0800128 for (j = 0; j < PALETTE_COLOR_INDEX_CONTEXTS; ++j) {
Yue Chenb23d00a2017-07-28 17:01:21 -0700129 av1_cost_tokens_from_cdf(x->palette_y_color_cost[i][j],
hui su466ae062017-07-25 16:55:51 -0700130 fc->palette_y_color_index_cdf[i][j], NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700131 av1_cost_tokens_from_cdf(x->palette_uv_color_cost[i][j],
hui su466ae062017-07-25 16:55:51 -0700132 fc->palette_uv_color_index_cdf[i][j], NULL);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700133 }
Urvang Joshib100db72016-10-12 16:28:56 -0700134 }
Yaowu Xuc27fc142016-08-22 16:08:15 -0700135
David Michael Barr38e560c2017-08-16 21:46:37 +0900136#if CONFIG_CFL
137 int sign_cost[CFL_JOINT_SIGNS];
138 av1_cost_tokens_from_cdf(sign_cost, fc->cfl_sign_cdf, NULL);
139 for (int joint_sign = 0; joint_sign < CFL_JOINT_SIGNS; joint_sign++) {
140 const aom_cdf_prob *cdf_u = fc->cfl_alpha_cdf[CFL_CONTEXT_U(joint_sign)];
141 const aom_cdf_prob *cdf_v = fc->cfl_alpha_cdf[CFL_CONTEXT_V(joint_sign)];
142 int *cost_u = x->cfl_cost[joint_sign][CFL_PRED_U];
143 int *cost_v = x->cfl_cost[joint_sign][CFL_PRED_V];
144 if (CFL_SIGN_U(joint_sign) == CFL_SIGN_ZERO)
145 memset(cost_u, 0, CFL_ALPHABET_SIZE * sizeof(*cost_u));
146 else
147 av1_cost_tokens_from_cdf(cost_u, cdf_u, NULL);
148 if (CFL_SIGN_V(joint_sign) == CFL_SIGN_ZERO)
149 memset(cost_v, 0, CFL_ALPHABET_SIZE * sizeof(*cost_v));
150 else
151 av1_cost_tokens_from_cdf(cost_v, cdf_v, NULL);
152 for (int u = 0; u < CFL_ALPHABET_SIZE; u++)
153 cost_u[u] += sign_cost[joint_sign];
154 }
155#endif // CONFIG_CFL
156
Jingning Hanaae72a62016-10-25 15:35:29 -0700157 for (i = 0; i < MAX_TX_DEPTH; ++i)
Yaowu Xuc27fc142016-08-22 16:08:15 -0700158 for (j = 0; j < TX_SIZE_CONTEXTS; ++j)
Yue Chenba47c842017-08-02 16:07:59 -0700159 av1_cost_tokens_from_cdf(x->tx_size_cost[i][j], fc->tx_size_cdf[i][j],
160 NULL);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700161
162#if CONFIG_EXT_TX
163 for (i = TX_4X4; i < EXT_TX_SIZES; ++i) {
164 int s;
165 for (s = 1; s < EXT_TX_SETS_INTER; ++s) {
166 if (use_inter_ext_tx_for_txsize[s][i]) {
Yue Chenba47c842017-08-02 16:07:59 -0700167 av1_cost_tokens_from_cdf(x->inter_tx_type_costs[s][i],
168 fc->inter_ext_tx_cdf[s][i],
169 av1_ext_tx_inter_inv[s]);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700170 }
171 }
172 for (s = 1; s < EXT_TX_SETS_INTRA; ++s) {
173 if (use_intra_ext_tx_for_txsize[s][i]) {
174 for (j = 0; j < INTRA_MODES; ++j)
Yue Chenba47c842017-08-02 16:07:59 -0700175 av1_cost_tokens_from_cdf(x->intra_tx_type_costs[s][i][j],
176 fc->intra_ext_tx_cdf[s][i][j],
177 av1_ext_tx_intra_inv[s]);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700178 }
179 }
180 }
181#else
182 for (i = TX_4X4; i < EXT_TX_SIZES; ++i) {
183 for (j = 0; j < TX_TYPES; ++j)
Yue Chenba47c842017-08-02 16:07:59 -0700184 av1_cost_tokens_from_cdf(x->intra_tx_type_costs[i][j],
185 fc->intra_ext_tx_cdf[i][j], av1_ext_tx_inv);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700186 }
187 for (i = TX_4X4; i < EXT_TX_SIZES; ++i) {
Yue Chenba47c842017-08-02 16:07:59 -0700188 av1_cost_tokens_from_cdf(x->inter_tx_type_costs[i], fc->inter_ext_tx_cdf[i],
189 av1_ext_tx_inv);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700190 }
191#endif // CONFIG_EXT_TX
192#if CONFIG_EXT_INTRA
hui sueda3d762016-12-06 16:58:23 -0800193#if CONFIG_INTRA_INTERP
Yaowu Xuc27fc142016-08-22 16:08:15 -0700194 for (i = 0; i < INTRA_FILTERS + 1; ++i)
Yue Chenba47c842017-08-02 16:07:59 -0700195 av1_cost_tokens_from_cdf(x->intra_filter_cost[i], fc->intra_filter_cdf[i],
196 NULL);
hui sueda3d762016-12-06 16:58:23 -0800197#endif // CONFIG_INTRA_INTERP
Yaowu Xuc27fc142016-08-22 16:08:15 -0700198#endif // CONFIG_EXT_INTRA
Debargha Mukherjee5cd2ab92016-09-08 15:15:17 -0700199#if CONFIG_LOOP_RESTORATION
Yue Chenb23d00a2017-07-28 17:01:21 -0700200 av1_cost_tokens(x->switchable_restore_cost, fc->switchable_restore_prob,
Debargha Mukherjee5cd2ab92016-09-08 15:15:17 -0700201 av1_switchable_restore_tree);
202#endif // CONFIG_LOOP_RESTORATION
Yue Chenb23d00a2017-07-28 17:01:21 -0700203
204 if (!frame_is_intra_only(cm)) {
205 for (i = 0; i < NEWMV_MODE_CONTEXTS; ++i) {
Yue Chenba47c842017-08-02 16:07:59 -0700206#if CONFIG_NEW_MULTISYMBOL
207 av1_cost_tokens_from_cdf(x->newmv_mode_cost[i], fc->newmv_cdf[i], NULL);
208#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700209 x->newmv_mode_cost[i][0] = av1_cost_bit(fc->newmv_prob[i], 0);
210 x->newmv_mode_cost[i][1] = av1_cost_bit(fc->newmv_prob[i], 1);
Yue Chenba47c842017-08-02 16:07:59 -0700211#endif
Yue Chenb23d00a2017-07-28 17:01:21 -0700212 }
213
214 for (i = 0; i < ZEROMV_MODE_CONTEXTS; ++i) {
Yue Chenba47c842017-08-02 16:07:59 -0700215#if CONFIG_NEW_MULTISYMBOL
216 av1_cost_tokens_from_cdf(x->zeromv_mode_cost[i], fc->zeromv_cdf[i], NULL);
217#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700218 x->zeromv_mode_cost[i][0] = av1_cost_bit(fc->zeromv_prob[i], 0);
219 x->zeromv_mode_cost[i][1] = av1_cost_bit(fc->zeromv_prob[i], 1);
Yue Chenba47c842017-08-02 16:07:59 -0700220#endif
Yue Chenb23d00a2017-07-28 17:01:21 -0700221 }
222
223 for (i = 0; i < REFMV_MODE_CONTEXTS; ++i) {
Yue Chenba47c842017-08-02 16:07:59 -0700224#if CONFIG_NEW_MULTISYMBOL
225 av1_cost_tokens_from_cdf(x->refmv_mode_cost[i], fc->refmv_cdf[i], NULL);
226#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700227 x->refmv_mode_cost[i][0] = av1_cost_bit(fc->refmv_prob[i], 0);
228 x->refmv_mode_cost[i][1] = av1_cost_bit(fc->refmv_prob[i], 1);
Yue Chenba47c842017-08-02 16:07:59 -0700229#endif
Yue Chenb23d00a2017-07-28 17:01:21 -0700230 }
231
232 for (i = 0; i < DRL_MODE_CONTEXTS; ++i) {
Yue Chenba47c842017-08-02 16:07:59 -0700233#if CONFIG_NEW_MULTISYMBOL
234 av1_cost_tokens_from_cdf(x->drl_mode_cost0[i], fc->drl_cdf[i], NULL);
235#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700236 x->drl_mode_cost0[i][0] = av1_cost_bit(fc->drl_prob[i], 0);
237 x->drl_mode_cost0[i][1] = av1_cost_bit(fc->drl_prob[i], 1);
Yue Chenba47c842017-08-02 16:07:59 -0700238#endif
Yue Chenb23d00a2017-07-28 17:01:21 -0700239 }
240#if CONFIG_EXT_INTER
241 for (i = 0; i < INTER_MODE_CONTEXTS; ++i)
Yue Chenba47c842017-08-02 16:07:59 -0700242 av1_cost_tokens_from_cdf(x->inter_compound_mode_cost[i],
243 fc->inter_compound_mode_cdf[i], NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700244#if CONFIG_COMPOUND_SINGLEREF
245 for (i = 0; i < INTER_MODE_CONTEXTS; ++i)
Yue Chenba47c842017-08-02 16:07:59 -0700246 av1_cost_tokens_from_cdf(x->inter_singleref_comp_mode_cost[i],
247 fc->inter_singleref_comp_mode_cdf[i], NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700248#endif // CONFIG_COMPOUND_SINGLEREF
249#if CONFIG_INTERINTRA
250 for (i = 0; i < BLOCK_SIZE_GROUPS; ++i)
Yue Chenba47c842017-08-02 16:07:59 -0700251 av1_cost_tokens_from_cdf(x->interintra_mode_cost[i],
252 fc->interintra_mode_cdf[i], NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700253#endif // CONFIG_INTERINTRA
254#endif // CONFIG_EXT_INTER
255#if CONFIG_MOTION_VAR || CONFIG_WARPED_MOTION
256 for (i = BLOCK_8X8; i < BLOCK_SIZES_ALL; i++) {
Wei-Ting Lin060f7f22017-08-01 10:26:24 -0700257 av1_cost_tokens_from_cdf(x->motion_mode_cost[i], fc->motion_mode_cdf[i],
258 NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700259 }
260#if CONFIG_MOTION_VAR && CONFIG_WARPED_MOTION
261 for (i = BLOCK_8X8; i < BLOCK_SIZES_ALL; i++) {
Yue Chenba47c842017-08-02 16:07:59 -0700262#if CONFIG_NEW_MULTISYMBOL
263 av1_cost_tokens_from_cdf(x->motion_mode_cost1[i], fc->obmc_cdf[i], NULL);
264#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700265 x->motion_mode_cost1[i][0] = av1_cost_bit(fc->obmc_prob[i], 0);
266 x->motion_mode_cost1[i][1] = av1_cost_bit(fc->obmc_prob[i], 1);
Yue Chenba47c842017-08-02 16:07:59 -0700267#endif
Yue Chenb23d00a2017-07-28 17:01:21 -0700268 }
269#endif // CONFIG_MOTION_VAR && CONFIG_WARPED_MOTION
270#if CONFIG_MOTION_VAR && CONFIG_NCOBMC_ADAPT_WEIGHT
271 for (i = ADAPT_OVERLAP_BLOCK_8X8; i < ADAPT_OVERLAP_BLOCKS; ++i) {
Wei-Ting Lin060f7f22017-08-01 10:26:24 -0700272 av1_cost_tokens_from_cdf(x->ncobmc_mode_cost[i], fc->ncobmc_mode_cdf[i],
273 NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700274 }
275#endif // CONFIG_MOTION_VAR && CONFIG_NCOBMC_ADAPT_WEIGHT
276#endif // CONFIG_MOTION_VAR || CONFIG_WARPED_MOTION
277 }
Yaowu Xuc27fc142016-08-22 16:08:15 -0700278}
279
Yaowu Xuc27fc142016-08-22 16:08:15 -0700280// Values are now correlated to quantizer.
281static int sad_per_bit16lut_8[QINDEX_RANGE];
282static int sad_per_bit4lut_8[QINDEX_RANGE];
283
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200284#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700285static int sad_per_bit16lut_10[QINDEX_RANGE];
286static int sad_per_bit4lut_10[QINDEX_RANGE];
287static int sad_per_bit16lut_12[QINDEX_RANGE];
288static int sad_per_bit4lut_12[QINDEX_RANGE];
289#endif
290
291static void init_me_luts_bd(int *bit16lut, int *bit4lut, int range,
Yaowu Xuf883b422016-08-30 14:01:10 -0700292 aom_bit_depth_t bit_depth) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700293 int i;
294 // Initialize the sad lut tables using a formulaic calculation for now.
295 // This is to make it easier to resolve the impact of experimental changes
296 // to the quantizer tables.
297 for (i = 0; i < range; i++) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700298 const double q = av1_convert_qindex_to_q(i, bit_depth);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700299 bit16lut[i] = (int)(0.0418 * q + 2.4107);
300 bit4lut[i] = (int)(0.063 * q + 2.742);
301 }
302}
303
Yaowu Xuf883b422016-08-30 14:01:10 -0700304void av1_init_me_luts(void) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700305 init_me_luts_bd(sad_per_bit16lut_8, sad_per_bit4lut_8, QINDEX_RANGE,
Yaowu Xuf883b422016-08-30 14:01:10 -0700306 AOM_BITS_8);
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200307#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700308 init_me_luts_bd(sad_per_bit16lut_10, sad_per_bit4lut_10, QINDEX_RANGE,
Yaowu Xuf883b422016-08-30 14:01:10 -0700309 AOM_BITS_10);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700310 init_me_luts_bd(sad_per_bit16lut_12, sad_per_bit4lut_12, QINDEX_RANGE,
Yaowu Xuf883b422016-08-30 14:01:10 -0700311 AOM_BITS_12);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700312#endif
313}
314
315static const int rd_boost_factor[16] = { 64, 32, 32, 32, 24, 16, 12, 12,
316 8, 8, 4, 4, 2, 2, 1, 0 };
317static const int rd_frame_type_factor[FRAME_UPDATE_TYPES] = {
318 128, 144, 128, 128, 144,
319#if CONFIG_EXT_REFS
320 // TODO(zoeliu): To adjust further following factor values.
321 128, 128, 128
322 // TODO(weitinglin): We should investigate if the values should be the same
323 // as the value used by OVERLAY frame
324 ,
Zoe Liue9b15e22017-07-19 15:53:01 -0700325 144 // INTNL_OVERLAY_UPDATE
326#if CONFIG_ALTREF2
327 ,
328 128 // INTNL_ARF_UPDATE
329#endif // CONFIG_ALTREF2
Yaowu Xuc27fc142016-08-22 16:08:15 -0700330#endif // CONFIG_EXT_REFS
331};
332
Yaowu Xuf883b422016-08-30 14:01:10 -0700333int av1_compute_rd_mult(const AV1_COMP *cpi, int qindex) {
334 const int64_t q = av1_dc_quant(qindex, 0, cpi->common.bit_depth);
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200335#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700336 int64_t rdmult = 0;
337 switch (cpi->common.bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700338 case AOM_BITS_8: rdmult = 88 * q * q / 24; break;
339 case AOM_BITS_10: rdmult = ROUND_POWER_OF_TWO(88 * q * q / 24, 4); break;
340 case AOM_BITS_12: rdmult = ROUND_POWER_OF_TWO(88 * q * q / 24, 8); break;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700341 default:
Yaowu Xuf883b422016-08-30 14:01:10 -0700342 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -0700343 return -1;
344 }
345#else
346 int64_t rdmult = 88 * q * q / 24;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200347#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700348 if (cpi->oxcf.pass == 2 && (cpi->common.frame_type != KEY_FRAME)) {
349 const GF_GROUP *const gf_group = &cpi->twopass.gf_group;
350 const FRAME_UPDATE_TYPE frame_type = gf_group->update_type[gf_group->index];
Yaowu Xuf883b422016-08-30 14:01:10 -0700351 const int boost_index = AOMMIN(15, (cpi->rc.gfu_boost / 100));
Yaowu Xuc27fc142016-08-22 16:08:15 -0700352
353 rdmult = (rdmult * rd_frame_type_factor[frame_type]) >> 7;
354 rdmult += ((rdmult * rd_boost_factor[boost_index]) >> 7);
355 }
356 if (rdmult < 1) rdmult = 1;
357 return (int)rdmult;
358}
359
Yaowu Xuf883b422016-08-30 14:01:10 -0700360static int compute_rd_thresh_factor(int qindex, aom_bit_depth_t bit_depth) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700361 double q;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200362#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700363 switch (bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700364 case AOM_BITS_8: q = av1_dc_quant(qindex, 0, AOM_BITS_8) / 4.0; break;
365 case AOM_BITS_10: q = av1_dc_quant(qindex, 0, AOM_BITS_10) / 16.0; break;
366 case AOM_BITS_12: q = av1_dc_quant(qindex, 0, AOM_BITS_12) / 64.0; break;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700367 default:
Yaowu Xuf883b422016-08-30 14:01:10 -0700368 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -0700369 return -1;
370 }
371#else
372 (void)bit_depth;
Yaowu Xuf883b422016-08-30 14:01:10 -0700373 q = av1_dc_quant(qindex, 0, AOM_BITS_8) / 4.0;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200374#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700375 // TODO(debargha): Adjust the function below.
Yaowu Xuf883b422016-08-30 14:01:10 -0700376 return AOMMAX((int)(pow(q, RD_THRESH_POW) * 5.12), 8);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700377}
378
Yaowu Xuf883b422016-08-30 14:01:10 -0700379void av1_initialize_me_consts(const AV1_COMP *cpi, MACROBLOCK *x, int qindex) {
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200380#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700381 switch (cpi->common.bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700382 case AOM_BITS_8:
Yaowu Xuc27fc142016-08-22 16:08:15 -0700383 x->sadperbit16 = sad_per_bit16lut_8[qindex];
384 x->sadperbit4 = sad_per_bit4lut_8[qindex];
385 break;
Yaowu Xuf883b422016-08-30 14:01:10 -0700386 case AOM_BITS_10:
Yaowu Xuc27fc142016-08-22 16:08:15 -0700387 x->sadperbit16 = sad_per_bit16lut_10[qindex];
388 x->sadperbit4 = sad_per_bit4lut_10[qindex];
389 break;
Yaowu Xuf883b422016-08-30 14:01:10 -0700390 case AOM_BITS_12:
Yaowu Xuc27fc142016-08-22 16:08:15 -0700391 x->sadperbit16 = sad_per_bit16lut_12[qindex];
392 x->sadperbit4 = sad_per_bit4lut_12[qindex];
393 break;
394 default:
Yaowu Xuf883b422016-08-30 14:01:10 -0700395 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -0700396 }
397#else
398 (void)cpi;
399 x->sadperbit16 = sad_per_bit16lut_8[qindex];
400 x->sadperbit4 = sad_per_bit4lut_8[qindex];
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200401#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700402}
403
Yaowu Xuf883b422016-08-30 14:01:10 -0700404static void set_block_thresholds(const AV1_COMMON *cm, RD_OPT *rd) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700405 int i, bsize, segment_id;
406
407 for (segment_id = 0; segment_id < MAX_SEGMENTS; ++segment_id) {
408 const int qindex =
Yaowu Xuf883b422016-08-30 14:01:10 -0700409 clamp(av1_get_qindex(&cm->seg, segment_id, cm->base_qindex) +
Yaowu Xuc27fc142016-08-22 16:08:15 -0700410 cm->y_dc_delta_q,
411 0, MAXQ);
412 const int q = compute_rd_thresh_factor(qindex, cm->bit_depth);
413
Rupert Swarbrick93c39e92017-07-12 11:11:02 +0100414 for (bsize = 0; bsize < BLOCK_SIZES_ALL; ++bsize) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700415 // Threshold here seems unnecessarily harsh but fine given actual
416 // range of values used for cpi->sf.thresh_mult[].
417 const int t = q * rd_thresh_block_size_factor[bsize];
418 const int thresh_max = INT_MAX / t;
419
Jingning Han9104bed2016-12-14 09:38:00 -0800420#if CONFIG_CB4X4
421 for (i = 0; i < MAX_MODES; ++i)
422 rd->threshes[segment_id][bsize][i] = rd->thresh_mult[i] < thresh_max
423 ? rd->thresh_mult[i] * t / 4
424 : INT_MAX;
425#else
Yaowu Xuc27fc142016-08-22 16:08:15 -0700426 if (bsize >= BLOCK_8X8) {
427 for (i = 0; i < MAX_MODES; ++i)
428 rd->threshes[segment_id][bsize][i] = rd->thresh_mult[i] < thresh_max
429 ? rd->thresh_mult[i] * t / 4
430 : INT_MAX;
431 } else {
432 for (i = 0; i < MAX_REFS; ++i)
433 rd->threshes[segment_id][bsize][i] =
434 rd->thresh_mult_sub8x8[i] < thresh_max
435 ? rd->thresh_mult_sub8x8[i] * t / 4
436 : INT_MAX;
437 }
Jingning Han9104bed2016-12-14 09:38:00 -0800438#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700439 }
440 }
441}
442
Yaowu Xu4306b6e2016-09-27 12:55:32 -0700443void av1_set_mvcost(MACROBLOCK *x, MV_REFERENCE_FRAME ref_frame, int ref,
444 int ref_mv_idx) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700445 MB_MODE_INFO_EXT *mbmi_ext = x->mbmi_ext;
Yaowu Xu4306b6e2016-09-27 12:55:32 -0700446 int8_t rf_type = av1_ref_frame_type(x->e_mbd.mi[0]->mbmi.ref_frame);
447 int nmv_ctx = av1_nmv_ctx(mbmi_ext->ref_mv_count[rf_type],
448 mbmi_ext->ref_mv_stack[rf_type], ref, ref_mv_idx);
449 (void)ref_frame;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700450 x->mvcost = x->mv_cost_stack[nmv_ctx];
451 x->nmvjointcost = x->nmv_vec_cost[nmv_ctx];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700452}
Yaowu Xuc27fc142016-08-22 16:08:15 -0700453
Jingning Handfd72322017-08-09 14:04:12 -0700454#if CONFIG_LV_MAP
Jingning Han24b0cf92017-08-18 22:50:18 -0700455#if !LV_MAP_PROB
Jingning Handfd72322017-08-09 14:04:12 -0700456static void get_rate_cost(aom_prob p, int cost[2]) {
457 cost[0] = av1_cost_bit(p, 0);
458 cost[1] = av1_cost_bit(p, 1);
459}
Jingning Han24b0cf92017-08-18 22:50:18 -0700460#endif // !LV_MAP_PROB
Jingning Handfd72322017-08-09 14:04:12 -0700461
462void av1_fill_coeff_costs(MACROBLOCK *x, FRAME_CONTEXT *fc) {
463 for (TX_SIZE tx_size = 0; tx_size < TX_SIZES; ++tx_size) {
464 for (int plane = 0; plane < PLANE_TYPES; ++plane) {
465 LV_MAP_COEFF_COST *pcost = &x->coeff_costs[tx_size][plane];
466
Jingning Han24b0cf92017-08-18 22:50:18 -0700467#if LV_MAP_PROB
468 for (int ctx = 0; ctx < TXB_SKIP_CONTEXTS; ++ctx)
469 av1_cost_tokens_from_cdf(pcost->txb_skip_cost[ctx],
470 fc->txb_skip_cdf[tx_size][ctx], NULL);
471
472 for (int ctx = 0; ctx < SIG_COEF_CONTEXTS; ++ctx)
473 av1_cost_tokens_from_cdf(pcost->nz_map_cost[ctx],
474 fc->nz_map_cdf[tx_size][plane][ctx], NULL);
475
476 for (int ctx = 0; ctx < EOB_COEF_CONTEXTS; ++ctx)
477 av1_cost_tokens_from_cdf(pcost->eob_cost[ctx],
478 fc->eob_flag_cdf[tx_size][plane][ctx], NULL);
479
480 for (int ctx = 0; ctx < DC_SIGN_CONTEXTS; ++ctx)
481 av1_cost_tokens_from_cdf(pcost->dc_sign_cost[ctx],
482 fc->dc_sign_cdf[plane][ctx], NULL);
483
484 for (int layer = 0; layer < NUM_BASE_LEVELS; ++layer)
485 for (int ctx = 0; ctx < COEFF_BASE_CONTEXTS; ++ctx)
486 av1_cost_tokens_from_cdf(
487 pcost->base_cost[layer][ctx],
488 fc->coeff_base_cdf[tx_size][plane][layer][ctx], NULL);
489
490 for (int ctx = 0; ctx < LEVEL_CONTEXTS; ++ctx)
491 av1_cost_tokens_from_cdf(pcost->lps_cost[ctx],
492 fc->coeff_lps_cdf[tx_size][plane][ctx], NULL);
493#else
Jingning Handfd72322017-08-09 14:04:12 -0700494 for (int ctx = 0; ctx < TXB_SKIP_CONTEXTS; ++ctx)
495 get_rate_cost(fc->txb_skip[tx_size][ctx], pcost->txb_skip_cost[ctx]);
496
497 for (int ctx = 0; ctx < SIG_COEF_CONTEXTS; ++ctx)
498 get_rate_cost(fc->nz_map[tx_size][plane][ctx], pcost->nz_map_cost[ctx]);
499
500 for (int ctx = 0; ctx < EOB_COEF_CONTEXTS; ++ctx)
501 get_rate_cost(fc->eob_flag[tx_size][plane][ctx], pcost->eob_cost[ctx]);
502
503 for (int ctx = 0; ctx < DC_SIGN_CONTEXTS; ++ctx)
504 get_rate_cost(fc->dc_sign[plane][ctx], pcost->dc_sign_cost[ctx]);
505
506 for (int layer = 0; layer < NUM_BASE_LEVELS; ++layer)
507 for (int ctx = 0; ctx < COEFF_BASE_CONTEXTS; ++ctx)
508 get_rate_cost(fc->coeff_base[tx_size][plane][layer][ctx],
509 pcost->base_cost[layer][ctx]);
510
511 for (int ctx = 0; ctx < LEVEL_CONTEXTS; ++ctx)
512 get_rate_cost(fc->coeff_lps[tx_size][plane][ctx], pcost->lps_cost[ctx]);
Jingning Han24b0cf92017-08-18 22:50:18 -0700513#endif
Jingning Handfd72322017-08-09 14:04:12 -0700514 }
515 }
516}
517#endif
518
hui subd57abe2017-07-24 18:14:03 -0700519void av1_fill_token_costs_from_cdf(av1_coeff_cost *cost,
520 coeff_cdf_model (*cdf)[PLANE_TYPES]) {
hui suc0cf71d2017-07-20 16:38:50 -0700521 for (int tx = 0; tx < TX_SIZES; ++tx) {
522 for (int pt = 0; pt < PLANE_TYPES; ++pt) {
523 for (int rt = 0; rt < REF_TYPES; ++rt) {
524 for (int band = 0; band < COEF_BANDS; ++band) {
525 for (int ctx = 0; ctx < BAND_COEFF_CONTEXTS(band); ++ctx) {
526 av1_cost_tokens_from_cdf(cost[tx][pt][rt][band][ctx],
527 cdf[tx][pt][rt][band][ctx], NULL);
528 }
529 }
530 }
531 }
532 }
533}
534
Yaowu Xuf883b422016-08-30 14:01:10 -0700535void av1_initialize_rd_consts(AV1_COMP *cpi) {
536 AV1_COMMON *const cm = &cpi->common;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700537 MACROBLOCK *const x = &cpi->td.mb;
538 RD_OPT *const rd = &cpi->rd;
Jingning Hanb3b034d2016-11-29 17:57:14 -0800539 int nmv_ctx;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700540
Yaowu Xuf883b422016-08-30 14:01:10 -0700541 aom_clear_system_state();
Yaowu Xuc27fc142016-08-22 16:08:15 -0700542
Yaowu Xuf883b422016-08-30 14:01:10 -0700543 rd->RDMULT = av1_compute_rd_mult(cpi, cm->base_qindex + cm->y_dc_delta_q);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700544
545 set_error_per_bit(x, rd->RDMULT);
546
547 set_block_thresholds(cm, rd);
548
Jingning Hanb3b034d2016-11-29 17:57:14 -0800549 for (nmv_ctx = 0; nmv_ctx < NMV_CONTEXTS; ++nmv_ctx) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700550 av1_build_nmv_cost_table(
Jingning Hanb3b034d2016-11-29 17:57:14 -0800551 x->nmv_vec_cost[nmv_ctx],
552 cm->allow_high_precision_mv ? x->nmvcost_hp[nmv_ctx]
553 : x->nmvcost[nmv_ctx],
554 &cm->fc->nmvc[nmv_ctx], cm->allow_high_precision_mv);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700555 }
Jingning Hanb3b034d2016-11-29 17:57:14 -0800556 x->mvcost = x->mv_cost_stack[0];
557 x->nmvjointcost = x->nmv_vec_cost[0];
Jingning Hanb3b034d2016-11-29 17:57:14 -0800558
Alex Conversed5d9b6c2017-05-23 15:23:45 -0700559#if CONFIG_INTRABC
560 if (frame_is_intra_only(cm) && cm->allow_screen_content_tools &&
561 cpi->oxcf.pass != 1) {
562 av1_build_nmv_cost_table(
563 x->nmv_vec_cost[0],
564 cm->allow_high_precision_mv ? x->nmvcost_hp[0] : x->nmvcost[0],
565 &cm->fc->ndvc, MV_SUBPEL_NONE);
566 }
567#endif
568
Yue Chenb23d00a2017-07-28 17:01:21 -0700569#if CONFIG_GLOBAL_MOTION
hui subd57abe2017-07-24 18:14:03 -0700570 if (cpi->oxcf.pass != 1) {
Zoe Liubc030ee2017-07-31 15:20:46 -0700571 for (int i = 0; i < TRANS_TYPES; ++i)
Yue Chenb23d00a2017-07-28 17:01:21 -0700572 cpi->gmtype_cost[i] = (1 + (i > 0 ? GLOBAL_TYPE_BITS : 0))
573 << AV1_PROB_COST_SHIFT;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700574 }
hui subd57abe2017-07-24 18:14:03 -0700575#endif // CONFIG_GLOBAL_MOTION
Yaowu Xuc27fc142016-08-22 16:08:15 -0700576}
577
578static void model_rd_norm(int xsq_q10, int *r_q10, int *d_q10) {
579 // NOTE: The tables below must be of the same size.
580
581 // The functions described below are sampled at the four most significant
582 // bits of x^2 + 8 / 256.
583
584 // Normalized rate:
585 // This table models the rate for a Laplacian source with given variance
586 // when quantized with a uniform quantizer with given stepsize. The
587 // closed form expression is:
588 // Rn(x) = H(sqrt(r)) + sqrt(r)*[1 + H(r)/(1 - r)],
589 // where r = exp(-sqrt(2) * x) and x = qpstep / sqrt(variance),
590 // and H(x) is the binary entropy function.
591 static const int rate_tab_q10[] = {
592 65536, 6086, 5574, 5275, 5063, 4899, 4764, 4651, 4553, 4389, 4255, 4142,
593 4044, 3958, 3881, 3811, 3748, 3635, 3538, 3453, 3376, 3307, 3244, 3186,
594 3133, 3037, 2952, 2877, 2809, 2747, 2690, 2638, 2589, 2501, 2423, 2353,
595 2290, 2232, 2179, 2130, 2084, 2001, 1928, 1862, 1802, 1748, 1698, 1651,
596 1608, 1530, 1460, 1398, 1342, 1290, 1243, 1199, 1159, 1086, 1021, 963,
597 911, 864, 821, 781, 745, 680, 623, 574, 530, 490, 455, 424,
598 395, 345, 304, 269, 239, 213, 190, 171, 154, 126, 104, 87,
599 73, 61, 52, 44, 38, 28, 21, 16, 12, 10, 8, 6,
600 5, 3, 2, 1, 1, 1, 0, 0,
601 };
602 // Normalized distortion:
603 // This table models the normalized distortion for a Laplacian source
604 // with given variance when quantized with a uniform quantizer
605 // with given stepsize. The closed form expression is:
606 // Dn(x) = 1 - 1/sqrt(2) * x / sinh(x/sqrt(2))
607 // where x = qpstep / sqrt(variance).
608 // Note the actual distortion is Dn * variance.
609 static const int dist_tab_q10[] = {
610 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 4, 5,
611 5, 6, 7, 7, 8, 9, 11, 12, 13, 15, 16, 17,
612 18, 21, 24, 26, 29, 31, 34, 36, 39, 44, 49, 54,
613 59, 64, 69, 73, 78, 88, 97, 106, 115, 124, 133, 142,
614 151, 167, 184, 200, 215, 231, 245, 260, 274, 301, 327, 351,
615 375, 397, 418, 439, 458, 495, 528, 559, 587, 613, 637, 659,
616 680, 717, 749, 777, 801, 823, 842, 859, 874, 899, 919, 936,
617 949, 960, 969, 977, 983, 994, 1001, 1006, 1010, 1013, 1015, 1017,
618 1018, 1020, 1022, 1022, 1023, 1023, 1023, 1024,
619 };
620 static const int xsq_iq_q10[] = {
621 0, 4, 8, 12, 16, 20, 24, 28, 32,
622 40, 48, 56, 64, 72, 80, 88, 96, 112,
623 128, 144, 160, 176, 192, 208, 224, 256, 288,
624 320, 352, 384, 416, 448, 480, 544, 608, 672,
625 736, 800, 864, 928, 992, 1120, 1248, 1376, 1504,
626 1632, 1760, 1888, 2016, 2272, 2528, 2784, 3040, 3296,
627 3552, 3808, 4064, 4576, 5088, 5600, 6112, 6624, 7136,
628 7648, 8160, 9184, 10208, 11232, 12256, 13280, 14304, 15328,
629 16352, 18400, 20448, 22496, 24544, 26592, 28640, 30688, 32736,
630 36832, 40928, 45024, 49120, 53216, 57312, 61408, 65504, 73696,
631 81888, 90080, 98272, 106464, 114656, 122848, 131040, 147424, 163808,
632 180192, 196576, 212960, 229344, 245728,
633 };
634 const int tmp = (xsq_q10 >> 2) + 8;
635 const int k = get_msb(tmp) - 3;
636 const int xq = (k << 3) + ((tmp >> k) & 0x7);
637 const int one_q10 = 1 << 10;
638 const int a_q10 = ((xsq_q10 - xsq_iq_q10[xq]) << 10) >> (2 + k);
639 const int b_q10 = one_q10 - a_q10;
640 *r_q10 = (rate_tab_q10[xq] * b_q10 + rate_tab_q10[xq + 1] * a_q10) >> 10;
641 *d_q10 = (dist_tab_q10[xq] * b_q10 + dist_tab_q10[xq + 1] * a_q10) >> 10;
642}
643
Yaowu Xuf883b422016-08-30 14:01:10 -0700644void av1_model_rd_from_var_lapndz(int64_t var, unsigned int n_log2,
645 unsigned int qstep, int *rate,
646 int64_t *dist) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700647 // This function models the rate and distortion for a Laplacian
648 // source with given variance when quantized with a uniform quantizer
649 // with given stepsize. The closed form expressions are in:
650 // Hang and Chen, "Source Model for transform video coder and its
651 // application - Part I: Fundamental Theory", IEEE Trans. Circ.
652 // Sys. for Video Tech., April 1997.
653 if (var == 0) {
654 *rate = 0;
655 *dist = 0;
656 } else {
657 int d_q10, r_q10;
658 static const uint32_t MAX_XSQ_Q10 = 245727;
659 const uint64_t xsq_q10_64 =
660 (((uint64_t)qstep * qstep << (n_log2 + 10)) + (var >> 1)) / var;
Yaowu Xuf883b422016-08-30 14:01:10 -0700661 const int xsq_q10 = (int)AOMMIN(xsq_q10_64, MAX_XSQ_Q10);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700662 model_rd_norm(xsq_q10, &r_q10, &d_q10);
Yaowu Xuf883b422016-08-30 14:01:10 -0700663 *rate = ROUND_POWER_OF_TWO(r_q10 << n_log2, 10 - AV1_PROB_COST_SHIFT);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700664 *dist = (var * (int64_t)d_q10 + 512) >> 10;
665 }
666}
667
668static void get_entropy_contexts_plane(
669 BLOCK_SIZE plane_bsize, TX_SIZE tx_size, const struct macroblockd_plane *pd,
670 ENTROPY_CONTEXT t_above[2 * MAX_MIB_SIZE],
671 ENTROPY_CONTEXT t_left[2 * MAX_MIB_SIZE]) {
Jingning Han9eef06d2016-12-05 12:39:34 -0800672 const int num_4x4_w = block_size_wide[plane_bsize] >> tx_size_wide_log2[0];
673 const int num_4x4_h = block_size_high[plane_bsize] >> tx_size_high_log2[0];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700674 const ENTROPY_CONTEXT *const above = pd->above_context;
675 const ENTROPY_CONTEXT *const left = pd->left_context;
676
Angie Chiangfb42c7f2017-06-01 18:36:18 -0700677#if CONFIG_LV_MAP
678 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
679 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
680 return;
681#endif // CONFIG_LV_MAP
682
Yaowu Xuc27fc142016-08-22 16:08:15 -0700683 int i;
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800684
Timothy B. Terriberryfe67ed62017-04-26 16:53:47 -0700685#if CONFIG_CHROMA_2X2
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800686 switch (tx_size) {
Jingning Han39772c12016-12-01 12:47:05 -0800687 case TX_2X2:
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800688 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
689 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
690 break;
691 case TX_4X4:
692 for (i = 0; i < num_4x4_w; i += 2)
693 t_above[i] = !!*(const uint16_t *)&above[i];
694 for (i = 0; i < num_4x4_h; i += 2)
695 t_left[i] = !!*(const uint16_t *)&left[i];
696 break;
697 case TX_8X8:
698 for (i = 0; i < num_4x4_w; i += 4)
699 t_above[i] = !!*(const uint32_t *)&above[i];
700 for (i = 0; i < num_4x4_h; i += 4)
701 t_left[i] = !!*(const uint32_t *)&left[i];
702 break;
703 case TX_16X16:
704 for (i = 0; i < num_4x4_w; i += 8)
705 t_above[i] = !!*(const uint64_t *)&above[i];
706 for (i = 0; i < num_4x4_h; i += 8)
707 t_left[i] = !!*(const uint64_t *)&left[i];
708 break;
709 case TX_32X32:
710 for (i = 0; i < num_4x4_w; i += 16)
711 t_above[i] =
712 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
713 for (i = 0; i < num_4x4_h; i += 16)
714 t_left[i] =
715 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
716 break;
Urvang Joshi4c6d4362017-05-11 12:35:46 -0700717#if CONFIG_TX64X64
718 case TX_64X64:
719 for (i = 0; i < num_4x4_w; i += 32)
720 t_above[i] =
721 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8] |
722 *(const uint64_t *)&above[i + 16] |
723 *(const uint64_t *)&above[i + 24]);
724 for (i = 0; i < num_4x4_h; i += 32)
725 t_left[i] =
726 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8] |
727 *(const uint64_t *)&left[i + 16] |
728 *(const uint64_t *)&left[i + 24]);
729 break;
730#endif // CONFIG_TX64X64
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800731 case TX_4X8:
732 for (i = 0; i < num_4x4_w; i += 2)
733 t_above[i] = !!*(const uint16_t *)&above[i];
734 for (i = 0; i < num_4x4_h; i += 4)
735 t_left[i] = !!*(const uint32_t *)&left[i];
736 break;
737 case TX_8X4:
738 for (i = 0; i < num_4x4_w; i += 4)
739 t_above[i] = !!*(const uint32_t *)&above[i];
740 for (i = 0; i < num_4x4_h; i += 2)
741 t_left[i] = !!*(const uint16_t *)&left[i];
742 break;
743 case TX_8X16:
744 for (i = 0; i < num_4x4_w; i += 4)
745 t_above[i] = !!*(const uint32_t *)&above[i];
746 for (i = 0; i < num_4x4_h; i += 8)
747 t_left[i] = !!*(const uint64_t *)&left[i];
748 break;
749 case TX_16X8:
750 for (i = 0; i < num_4x4_w; i += 8)
751 t_above[i] = !!*(const uint64_t *)&above[i];
752 for (i = 0; i < num_4x4_h; i += 4)
753 t_left[i] = !!*(const uint32_t *)&left[i];
754 break;
755 case TX_16X32:
756 for (i = 0; i < num_4x4_w; i += 8)
757 t_above[i] = !!*(const uint64_t *)&above[i];
758 for (i = 0; i < num_4x4_h; i += 16)
759 t_left[i] =
760 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
761 break;
762 case TX_32X16:
763 for (i = 0; i < num_4x4_w; i += 16)
764 t_above[i] =
765 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
766 for (i = 0; i < num_4x4_h; i += 8)
767 t_left[i] = !!*(const uint64_t *)&left[i];
Jingning Han0f6a60a2017-01-20 09:25:40 -0800768 break;
Yue Chend6bdd462017-07-19 16:05:43 -0700769#if CONFIG_RECT_TX_EXT && (CONFIG_EXT_TX || CONFIG_VAR_TX)
Yue Chen56e226e2017-05-02 16:21:40 -0700770 case TX_4X16:
771 for (i = 0; i < num_4x4_w; i += 2)
772 t_above[i] = !!*(const uint16_t *)&above[i];
773 for (i = 0; i < num_4x4_h; i += 8)
774 t_left[i] = !!*(const uint64_t *)&left[i];
775 break;
776 case TX_16X4:
777 for (i = 0; i < num_4x4_w; i += 8)
778 t_above[i] = !!*(const uint64_t *)&above[i];
779 for (i = 0; i < num_4x4_h; i += 2)
780 t_left[i] = !!*(const uint16_t *)&left[i];
781 break;
782 case TX_8X32:
783 for (i = 0; i < num_4x4_w; i += 4)
784 t_above[i] = !!*(const uint32_t *)&above[i];
785 for (i = 0; i < num_4x4_h; i += 16)
786 t_left[i] =
787 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
788 break;
789 case TX_32X8:
790 for (i = 0; i < num_4x4_w; i += 16)
791 t_above[i] =
792 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
793 for (i = 0; i < num_4x4_h; i += 4)
794 t_left[i] = !!*(const uint32_t *)&left[i];
795 break;
Yue Chend6bdd462017-07-19 16:05:43 -0700796#endif
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800797
798 default: assert(0 && "Invalid transform size."); break;
799 }
800 return;
Timothy B. Terriberryfe67ed62017-04-26 16:53:47 -0700801#endif // CONFIG_CHROMA_2X2
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800802
803 switch (tx_size) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700804 case TX_4X4:
805 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
806 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
807 break;
808 case TX_8X8:
809 for (i = 0; i < num_4x4_w; i += 2)
810 t_above[i] = !!*(const uint16_t *)&above[i];
811 for (i = 0; i < num_4x4_h; i += 2)
812 t_left[i] = !!*(const uint16_t *)&left[i];
813 break;
814 case TX_16X16:
815 for (i = 0; i < num_4x4_w; i += 4)
816 t_above[i] = !!*(const uint32_t *)&above[i];
817 for (i = 0; i < num_4x4_h; i += 4)
818 t_left[i] = !!*(const uint32_t *)&left[i];
819 break;
820 case TX_32X32:
821 for (i = 0; i < num_4x4_w; i += 8)
822 t_above[i] = !!*(const uint64_t *)&above[i];
823 for (i = 0; i < num_4x4_h; i += 8)
824 t_left[i] = !!*(const uint64_t *)&left[i];
825 break;
Debargha Mukherjee153e1f82016-11-17 09:59:14 -0800826#if CONFIG_TX64X64
827 case TX_64X64:
828 for (i = 0; i < num_4x4_w; i += 16)
829 t_above[i] =
830 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
831 for (i = 0; i < num_4x4_h; i += 16)
Debargha Mukherjee932cf692016-11-18 08:14:10 -0800832 t_left[i] =
833 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
Debargha Mukherjee153e1f82016-11-17 09:59:14 -0800834 break;
835#endif // CONFIG_TX64X64
Yaowu Xuc27fc142016-08-22 16:08:15 -0700836 case TX_4X8:
837 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
838 for (i = 0; i < num_4x4_h; i += 2)
839 t_left[i] = !!*(const uint16_t *)&left[i];
840 break;
841 case TX_8X4:
842 for (i = 0; i < num_4x4_w; i += 2)
843 t_above[i] = !!*(const uint16_t *)&above[i];
844 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
845 break;
846 case TX_8X16:
847 for (i = 0; i < num_4x4_w; i += 2)
848 t_above[i] = !!*(const uint16_t *)&above[i];
849 for (i = 0; i < num_4x4_h; i += 4)
850 t_left[i] = !!*(const uint32_t *)&left[i];
851 break;
852 case TX_16X8:
853 for (i = 0; i < num_4x4_w; i += 4)
854 t_above[i] = !!*(const uint32_t *)&above[i];
855 for (i = 0; i < num_4x4_h; i += 2)
856 t_left[i] = !!*(const uint16_t *)&left[i];
857 break;
858 case TX_16X32:
859 for (i = 0; i < num_4x4_w; i += 4)
860 t_above[i] = !!*(const uint32_t *)&above[i];
861 for (i = 0; i < num_4x4_h; i += 8)
862 t_left[i] = !!*(const uint64_t *)&left[i];
863 break;
864 case TX_32X16:
865 for (i = 0; i < num_4x4_w; i += 8)
866 t_above[i] = !!*(const uint64_t *)&above[i];
867 for (i = 0; i < num_4x4_h; i += 4)
868 t_left[i] = !!*(const uint32_t *)&left[i];
869 break;
Yue Chend6bdd462017-07-19 16:05:43 -0700870#if CONFIG_RECT_TX_EXT && (CONFIG_EXT_TX || CONFIG_VAR_TX)
Yue Chen56e226e2017-05-02 16:21:40 -0700871 case TX_4X16:
872 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
873 for (i = 0; i < num_4x4_h; i += 4)
874 t_left[i] = !!*(const uint32_t *)&left[i];
875 break;
876 case TX_16X4:
877 for (i = 0; i < num_4x4_w; i += 4)
878 t_above[i] = !!*(const uint32_t *)&above[i];
879 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
880 break;
881 case TX_8X32:
882 for (i = 0; i < num_4x4_w; i += 2)
883 t_above[i] = !!*(const uint16_t *)&above[i];
884 for (i = 0; i < num_4x4_h; i += 8)
885 t_left[i] = !!*(const uint64_t *)&left[i];
886 break;
887 case TX_32X8:
888 for (i = 0; i < num_4x4_w; i += 8)
889 t_above[i] = !!*(const uint64_t *)&above[i];
890 for (i = 0; i < num_4x4_h; i += 2)
891 t_left[i] = !!*(const uint16_t *)&left[i];
892 break;
Yue Chend6bdd462017-07-19 16:05:43 -0700893#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700894 default: assert(0 && "Invalid transform size."); break;
895 }
896}
897
Yaowu Xuf883b422016-08-30 14:01:10 -0700898void av1_get_entropy_contexts(BLOCK_SIZE bsize, TX_SIZE tx_size,
899 const struct macroblockd_plane *pd,
900 ENTROPY_CONTEXT t_above[2 * MAX_MIB_SIZE],
901 ENTROPY_CONTEXT t_left[2 * MAX_MIB_SIZE]) {
Timothy B. Terriberry81ec2612017-04-26 16:53:47 -0700902#if CONFIG_CHROMA_SUB8X8
Timothy B. Terriberry32b8d462017-05-22 12:02:56 -0700903 const BLOCK_SIZE plane_bsize =
904 AOMMAX(BLOCK_4X4, get_plane_block_size(bsize, pd));
905#else
Yaowu Xuc27fc142016-08-22 16:08:15 -0700906 const BLOCK_SIZE plane_bsize = get_plane_block_size(bsize, pd);
Timothy B. Terriberry32b8d462017-05-22 12:02:56 -0700907#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700908 get_entropy_contexts_plane(plane_bsize, tx_size, pd, t_above, t_left);
909}
910
Urvang Joshi52648442016-10-13 17:27:51 -0700911void av1_mv_pred(const AV1_COMP *cpi, MACROBLOCK *x, uint8_t *ref_y_buffer,
Yaowu Xuf883b422016-08-30 14:01:10 -0700912 int ref_y_stride, int ref_frame, BLOCK_SIZE block_size) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700913 int i;
914 int zero_seen = 0;
915 int best_index = 0;
916 int best_sad = INT_MAX;
917 int this_sad = INT_MAX;
918 int max_mv = 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700919 uint8_t *src_y_ptr = x->plane[0].src.buf;
920 uint8_t *ref_y_ptr;
Thomas Daede07438572017-05-10 11:22:33 -0700921 MV pred_mv[MAX_MV_REF_CANDIDATES + 1];
Debargha Mukherjeed80d63f2017-05-17 15:53:27 -0700922 int num_mv_refs = 0;
923
924 pred_mv[num_mv_refs++] = x->mbmi_ext->ref_mvs[ref_frame][0].as_mv;
925 if (x->mbmi_ext->ref_mvs[ref_frame][0].as_int !=
926 x->mbmi_ext->ref_mvs[ref_frame][1].as_int) {
927 pred_mv[num_mv_refs++] = x->mbmi_ext->ref_mvs[ref_frame][1].as_mv;
Thomas Daede07438572017-05-10 11:22:33 -0700928 }
Debargha Mukherjeed80d63f2017-05-17 15:53:27 -0700929 if (cpi->sf.adaptive_motion_search && block_size < x->max_partition_size)
930 pred_mv[num_mv_refs++] = x->pred_mv[ref_frame];
931
Yaowu Xuc27fc142016-08-22 16:08:15 -0700932 assert(num_mv_refs <= (int)(sizeof(pred_mv) / sizeof(pred_mv[0])));
Debargha Mukherjeed80d63f2017-05-17 15:53:27 -0700933
Yaowu Xuc27fc142016-08-22 16:08:15 -0700934 // Get the sad for each candidate reference mv.
935 for (i = 0; i < num_mv_refs; ++i) {
936 const MV *this_mv = &pred_mv[i];
937 int fp_row, fp_col;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700938 fp_row = (this_mv->row + 3 + (this_mv->row >= 0)) >> 3;
939 fp_col = (this_mv->col + 3 + (this_mv->col >= 0)) >> 3;
Yaowu Xuf883b422016-08-30 14:01:10 -0700940 max_mv = AOMMAX(max_mv, AOMMAX(abs(this_mv->row), abs(this_mv->col)) >> 3);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700941
942 if (fp_row == 0 && fp_col == 0 && zero_seen) continue;
943 zero_seen |= (fp_row == 0 && fp_col == 0);
944
945 ref_y_ptr = &ref_y_buffer[ref_y_stride * fp_row + fp_col];
946 // Find sad for current vector.
947 this_sad = cpi->fn_ptr[block_size].sdf(src_y_ptr, x->plane[0].src.stride,
948 ref_y_ptr, ref_y_stride);
949 // Note if it is the best so far.
950 if (this_sad < best_sad) {
951 best_sad = this_sad;
952 best_index = i;
953 }
954 }
955
956 // Note the index of the mv that worked best in the reference list.
957 x->mv_best_ref_index[ref_frame] = best_index;
958 x->max_mv_context[ref_frame] = max_mv;
959 x->pred_mv_sad[ref_frame] = best_sad;
960}
961
Yaowu Xuf883b422016-08-30 14:01:10 -0700962void av1_setup_pred_block(const MACROBLOCKD *xd,
963 struct buf_2d dst[MAX_MB_PLANE],
964 const YV12_BUFFER_CONFIG *src, int mi_row, int mi_col,
965 const struct scale_factors *scale,
966 const struct scale_factors *scale_uv) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700967 int i;
968
969 dst[0].buf = src->y_buffer;
970 dst[0].stride = src->y_stride;
971 dst[1].buf = src->u_buffer;
972 dst[2].buf = src->v_buffer;
973 dst[1].stride = dst[2].stride = src->uv_stride;
974
975 for (i = 0; i < MAX_MB_PLANE; ++i) {
Jingning Han91d9a792017-04-18 12:01:52 -0700976 setup_pred_plane(dst + i, xd->mi[0]->mbmi.sb_type, dst[i].buf,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700977 i ? src->uv_crop_width : src->y_crop_width,
978 i ? src->uv_crop_height : src->y_crop_height,
979 dst[i].stride, mi_row, mi_col, i ? scale_uv : scale,
980 xd->plane[i].subsampling_x, xd->plane[i].subsampling_y);
981 }
982}
983
Yaowu Xuf883b422016-08-30 14:01:10 -0700984int av1_raster_block_offset(BLOCK_SIZE plane_bsize, int raster_block,
985 int stride) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700986 const int bw = b_width_log2_lookup[plane_bsize];
987 const int y = 4 * (raster_block >> bw);
988 const int x = 4 * (raster_block & ((1 << bw) - 1));
989 return y * stride + x;
990}
991
Yaowu Xuf883b422016-08-30 14:01:10 -0700992int16_t *av1_raster_block_offset_int16(BLOCK_SIZE plane_bsize, int raster_block,
993 int16_t *base) {
Jingning Hanae5cfde2016-11-30 12:01:44 -0800994 const int stride = block_size_wide[plane_bsize];
Yaowu Xuf883b422016-08-30 14:01:10 -0700995 return base + av1_raster_block_offset(plane_bsize, raster_block, stride);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700996}
997
Yaowu Xuf883b422016-08-30 14:01:10 -0700998YV12_BUFFER_CONFIG *av1_get_scaled_ref_frame(const AV1_COMP *cpi,
999 int ref_frame) {
1000 const AV1_COMMON *const cm = &cpi->common;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001001 const int scaled_idx = cpi->scaled_ref_idx[ref_frame - 1];
1002 const int ref_idx = get_ref_frame_buf_idx(cpi, ref_frame);
1003 return (scaled_idx != ref_idx && scaled_idx != INVALID_IDX)
1004 ? &cm->buffer_pool->frame_bufs[scaled_idx].buf
1005 : NULL;
1006}
1007
1008#if CONFIG_DUAL_FILTER
Yue Chenb23d00a2017-07-28 17:01:21 -07001009int av1_get_switchable_rate(const AV1_COMMON *const cm, MACROBLOCK *x,
1010 const MACROBLOCKD *xd) {
Angie Chiang75c22092016-10-25 12:19:16 -07001011 if (cm->interp_filter == SWITCHABLE) {
1012 const MB_MODE_INFO *const mbmi = &xd->mi[0]->mbmi;
1013 int inter_filter_cost = 0;
1014 int dir;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001015
Angie Chiang75c22092016-10-25 12:19:16 -07001016 for (dir = 0; dir < 2; ++dir) {
1017 if (has_subpel_mv_component(xd->mi[0], xd, dir) ||
1018 (mbmi->ref_frame[1] > INTRA_FRAME &&
1019 has_subpel_mv_component(xd->mi[0], xd, dir + 2))) {
1020 const int ctx = av1_get_pred_context_switchable_interp(xd, dir);
1021 inter_filter_cost +=
Yue Chenb23d00a2017-07-28 17:01:21 -07001022 x->switchable_interp_costs[ctx][mbmi->interp_filter[dir]];
Angie Chiang75c22092016-10-25 12:19:16 -07001023 }
Yaowu Xuc27fc142016-08-22 16:08:15 -07001024 }
Angie Chiang75c22092016-10-25 12:19:16 -07001025 return SWITCHABLE_INTERP_RATE_FACTOR * inter_filter_cost;
1026 } else {
1027 return 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001028 }
Yaowu Xuc27fc142016-08-22 16:08:15 -07001029}
1030#else
Yue Chenb23d00a2017-07-28 17:01:21 -07001031int av1_get_switchable_rate(const AV1_COMMON *const cm, MACROBLOCK *x,
1032 const MACROBLOCKD *xd) {
Angie Chiang75c22092016-10-25 12:19:16 -07001033 if (cm->interp_filter == SWITCHABLE) {
Angie Chiang1733f6b2017-01-05 09:52:20 -08001034 const MB_MODE_INFO *const mbmi = &xd->mi[0]->mbmi;
1035 const int ctx = av1_get_pred_context_switchable_interp(xd);
1036 return SWITCHABLE_INTERP_RATE_FACTOR *
Yue Chenb23d00a2017-07-28 17:01:21 -07001037 x->switchable_interp_costs[ctx][mbmi->interp_filter];
Angie Chiang75c22092016-10-25 12:19:16 -07001038 }
1039 return 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001040}
1041#endif
1042
Yaowu Xuf883b422016-08-30 14:01:10 -07001043void av1_set_rd_speed_thresholds(AV1_COMP *cpi) {
Yaowu Xuc27fc142016-08-22 16:08:15 -07001044 int i;
1045 RD_OPT *const rd = &cpi->rd;
1046 SPEED_FEATURES *const sf = &cpi->sf;
1047
1048 // Set baseline threshold values.
Thomas Daede6eca8352017-03-17 14:14:12 -07001049 for (i = 0; i < MAX_MODES; ++i) rd->thresh_mult[i] = cpi->oxcf.mode == 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001050
1051 if (sf->adaptive_rd_thresh) {
1052 rd->thresh_mult[THR_NEARESTMV] = 300;
1053#if CONFIG_EXT_REFS
1054 rd->thresh_mult[THR_NEARESTL2] = 300;
1055 rd->thresh_mult[THR_NEARESTL3] = 300;
1056 rd->thresh_mult[THR_NEARESTB] = 300;
Zoe Liue9b15e22017-07-19 15:53:01 -07001057#if CONFIG_ALTREF2
1058 rd->thresh_mult[THR_NEARESTA2] = 300;
1059#endif // CONFIG_ALTREF2
Yaowu Xuc27fc142016-08-22 16:08:15 -07001060#endif // CONFIG_EXT_REFS
1061 rd->thresh_mult[THR_NEARESTA] = 300;
1062 rd->thresh_mult[THR_NEARESTG] = 300;
1063 } else {
1064 rd->thresh_mult[THR_NEARESTMV] = 0;
1065#if CONFIG_EXT_REFS
1066 rd->thresh_mult[THR_NEARESTL2] = 0;
1067 rd->thresh_mult[THR_NEARESTL3] = 0;
1068 rd->thresh_mult[THR_NEARESTB] = 0;
Zoe Liue9b15e22017-07-19 15:53:01 -07001069#if CONFIG_ALTREF2
1070 rd->thresh_mult[THR_NEARESTA2] = 0;
1071#endif // CONFIG_ALTREF2
Yaowu Xuc27fc142016-08-22 16:08:15 -07001072#endif // CONFIG_EXT_REFS
1073 rd->thresh_mult[THR_NEARESTA] = 0;
1074 rd->thresh_mult[THR_NEARESTG] = 0;
1075 }
1076
1077 rd->thresh_mult[THR_DC] += 1000;
1078
1079 rd->thresh_mult[THR_NEWMV] += 1000;
1080#if CONFIG_EXT_REFS
1081 rd->thresh_mult[THR_NEWL2] += 1000;
1082 rd->thresh_mult[THR_NEWL3] += 1000;
1083 rd->thresh_mult[THR_NEWB] += 1000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001084#if CONFIG_ALTREF2
1085 rd->thresh_mult[THR_NEWA2] = 1000;
1086#endif // CONFIG_ALTREF2
Yaowu Xuc27fc142016-08-22 16:08:15 -07001087#endif // CONFIG_EXT_REFS
1088 rd->thresh_mult[THR_NEWA] += 1000;
1089 rd->thresh_mult[THR_NEWG] += 1000;
1090
1091 rd->thresh_mult[THR_NEARMV] += 1000;
1092#if CONFIG_EXT_REFS
1093 rd->thresh_mult[THR_NEARL2] += 1000;
1094 rd->thresh_mult[THR_NEARL3] += 1000;
1095 rd->thresh_mult[THR_NEARB] += 1000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001096#if CONFIG_ALTREF2
1097 rd->thresh_mult[THR_NEARA2] = 1000;
1098#endif // CONFIG_ALTREF2
Yaowu Xuc27fc142016-08-22 16:08:15 -07001099#endif // CONFIG_EXT_REFS
1100 rd->thresh_mult[THR_NEARA] += 1000;
1101 rd->thresh_mult[THR_NEARG] += 1000;
1102
Yaowu Xuc27fc142016-08-22 16:08:15 -07001103 rd->thresh_mult[THR_ZEROMV] += 2000;
1104#if CONFIG_EXT_REFS
1105 rd->thresh_mult[THR_ZEROL2] += 2000;
1106 rd->thresh_mult[THR_ZEROL3] += 2000;
1107 rd->thresh_mult[THR_ZEROB] += 2000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001108#if CONFIG_ALTREF2
1109 rd->thresh_mult[THR_ZEROA2] = 2000;
1110#endif // CONFIG_ALTREF2
Yaowu Xuc27fc142016-08-22 16:08:15 -07001111#endif // CONFIG_EXT_REFS
1112 rd->thresh_mult[THR_ZEROG] += 2000;
1113 rd->thresh_mult[THR_ZEROA] += 2000;
1114
1115 rd->thresh_mult[THR_TM] += 1000;
1116
1117#if CONFIG_EXT_INTER
1118
Zoe Liu85b66462017-04-20 14:28:19 -07001119#if CONFIG_COMPOUND_SINGLEREF
1120 rd->thresh_mult[THR_SR_NEAREST_NEARMV] += 1200;
1121#if CONFIG_EXT_REFS
1122 rd->thresh_mult[THR_SR_NEAREST_NEARL2] += 1200;
1123 rd->thresh_mult[THR_SR_NEAREST_NEARL3] += 1200;
1124 rd->thresh_mult[THR_SR_NEAREST_NEARB] += 1200;
1125#endif // CONFIG_EXT_REFS
1126 rd->thresh_mult[THR_SR_NEAREST_NEARA] += 1200;
1127 rd->thresh_mult[THR_SR_NEAREST_NEARG] += 1200;
1128
1129 /*
1130 rd->thresh_mult[THR_SR_NEAREST_NEWMV] += 1200;
1131#if CONFIG_EXT_REFS
1132 rd->thresh_mult[THR_SR_NEAREST_NEWL2] += 1200;
1133 rd->thresh_mult[THR_SR_NEAREST_NEWL3] += 1200;
1134 rd->thresh_mult[THR_SR_NEAREST_NEWB] += 1200;
1135#endif // CONFIG_EXT_REFS
1136 rd->thresh_mult[THR_SR_NEAREST_NEWA] += 1200;
1137 rd->thresh_mult[THR_SR_NEAREST_NEWG] += 1200;*/
1138
1139 rd->thresh_mult[THR_SR_NEAR_NEWMV] += 1500;
1140#if CONFIG_EXT_REFS
1141 rd->thresh_mult[THR_SR_NEAR_NEWL2] += 1500;
1142 rd->thresh_mult[THR_SR_NEAR_NEWL3] += 1500;
1143 rd->thresh_mult[THR_SR_NEAR_NEWB] += 1500;
1144#endif // CONFIG_EXT_REFS
1145 rd->thresh_mult[THR_SR_NEAR_NEWA] += 1500;
1146 rd->thresh_mult[THR_SR_NEAR_NEWG] += 1500;
1147
1148 rd->thresh_mult[THR_SR_ZERO_NEWMV] += 2000;
1149#if CONFIG_EXT_REFS
1150 rd->thresh_mult[THR_SR_ZERO_NEWL2] += 2000;
1151 rd->thresh_mult[THR_SR_ZERO_NEWL3] += 2000;
1152 rd->thresh_mult[THR_SR_ZERO_NEWB] += 2000;
1153#endif // CONFIG_EXT_REFS
1154 rd->thresh_mult[THR_SR_ZERO_NEWA] += 2000;
1155 rd->thresh_mult[THR_SR_ZERO_NEWG] += 2000;
1156
1157 rd->thresh_mult[THR_SR_NEW_NEWMV] += 1700;
1158#if CONFIG_EXT_REFS
1159 rd->thresh_mult[THR_SR_NEW_NEWL2] += 1700;
1160 rd->thresh_mult[THR_SR_NEW_NEWL3] += 1700;
1161 rd->thresh_mult[THR_SR_NEW_NEWB] += 1700;
1162#endif // CONFIG_EXT_REFS
1163 rd->thresh_mult[THR_SR_NEW_NEWA] += 1700;
1164 rd->thresh_mult[THR_SR_NEW_NEWG] += 1700;
1165#endif // CONFIG_COMPOUND_SINGLEREF
1166
Yaowu Xuc27fc142016-08-22 16:08:15 -07001167 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLA] += 1000;
1168#if CONFIG_EXT_REFS
1169 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL2A] += 1000;
1170 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL3A] += 1000;
1171#endif // CONFIG_EXT_REFS
1172 rd->thresh_mult[THR_COMP_NEAREST_NEARESTGA] += 1000;
1173#if CONFIG_EXT_REFS
1174 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLB] += 1000;
1175 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL2B] += 1000;
1176 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL3B] += 1000;
1177 rd->thresh_mult[THR_COMP_NEAREST_NEARESTGB] += 1000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001178#if CONFIG_ALTREF2
1179 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLA2] += 1000;
1180 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL2A2] += 1000;
1181 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL3A2] += 1000;
1182 rd->thresh_mult[THR_COMP_NEAREST_NEARESTGA2] += 1000;
1183#endif // CONFIG_ALTREF2
Zoe Liuc082bbc2017-05-17 13:31:37 -07001184
1185#if CONFIG_EXT_COMP_REFS
1186 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLL2] += 1000;
Zoe Liufcf5fa22017-06-26 16:00:38 -07001187 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLL3] += 1000;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001188 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLG] += 1000;
1189 rd->thresh_mult[THR_COMP_NEAREST_NEARESTBA] += 1000;
1190#endif // CONFIG_EXT_COMP_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001191#endif // CONFIG_EXT_REFS
1192
1193#else // CONFIG_EXT_INTER
1194
1195 rd->thresh_mult[THR_COMP_NEARESTLA] += 1000;
1196#if CONFIG_EXT_REFS
1197 rd->thresh_mult[THR_COMP_NEARESTL2A] += 1000;
1198 rd->thresh_mult[THR_COMP_NEARESTL3A] += 1000;
1199#endif // CONFIG_EXT_REFS
1200 rd->thresh_mult[THR_COMP_NEARESTGA] += 1000;
1201#if CONFIG_EXT_REFS
1202 rd->thresh_mult[THR_COMP_NEARESTLB] += 1000;
1203 rd->thresh_mult[THR_COMP_NEARESTL2B] += 1000;
1204 rd->thresh_mult[THR_COMP_NEARESTL3B] += 1000;
1205 rd->thresh_mult[THR_COMP_NEARESTGB] += 1000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001206#if CONFIG_ALTREF2
1207 rd->thresh_mult[THR_COMP_NEARESTLA2] += 1000;
1208 rd->thresh_mult[THR_COMP_NEARESTL2A2] += 1000;
1209 rd->thresh_mult[THR_COMP_NEARESTL3A2] += 1000;
1210 rd->thresh_mult[THR_COMP_NEARESTGA2] += 1000;
1211#endif // CONFIG_ALTREF2
1212
Zoe Liuc082bbc2017-05-17 13:31:37 -07001213#if CONFIG_EXT_COMP_REFS
1214 rd->thresh_mult[THR_COMP_NEARESTLL2] += 1000;
Zoe Liufcf5fa22017-06-26 16:00:38 -07001215 rd->thresh_mult[THR_COMP_NEARESTLL3] += 1000;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001216 rd->thresh_mult[THR_COMP_NEARESTLG] += 1000;
1217 rd->thresh_mult[THR_COMP_NEARESTBA] += 1000;
1218#endif // CONFIG_EXT_COMP_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001219#endif // CONFIG_EXT_REFS
1220
1221#endif // CONFIG_EXT_INTER
1222
1223#if CONFIG_EXT_INTER
1224
Yaowu Xuc27fc142016-08-22 16:08:15 -07001225 rd->thresh_mult[THR_COMP_NEAR_NEARLA] += 1200;
1226 rd->thresh_mult[THR_COMP_NEAREST_NEWLA] += 1500;
1227 rd->thresh_mult[THR_COMP_NEW_NEARESTLA] += 1500;
1228 rd->thresh_mult[THR_COMP_NEAR_NEWLA] += 1700;
1229 rd->thresh_mult[THR_COMP_NEW_NEARLA] += 1700;
1230 rd->thresh_mult[THR_COMP_NEW_NEWLA] += 2000;
1231 rd->thresh_mult[THR_COMP_ZERO_ZEROLA] += 2500;
1232
1233#if CONFIG_EXT_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001234 rd->thresh_mult[THR_COMP_NEAR_NEARL2A] += 1200;
1235 rd->thresh_mult[THR_COMP_NEAREST_NEWL2A] += 1500;
1236 rd->thresh_mult[THR_COMP_NEW_NEARESTL2A] += 1500;
1237 rd->thresh_mult[THR_COMP_NEAR_NEWL2A] += 1700;
1238 rd->thresh_mult[THR_COMP_NEW_NEARL2A] += 1700;
1239 rd->thresh_mult[THR_COMP_NEW_NEWL2A] += 2000;
1240 rd->thresh_mult[THR_COMP_ZERO_ZEROL2A] += 2500;
1241
Yaowu Xuc27fc142016-08-22 16:08:15 -07001242 rd->thresh_mult[THR_COMP_NEAR_NEARL3A] += 1200;
1243 rd->thresh_mult[THR_COMP_NEAREST_NEWL3A] += 1500;
1244 rd->thresh_mult[THR_COMP_NEW_NEARESTL3A] += 1500;
1245 rd->thresh_mult[THR_COMP_NEAR_NEWL3A] += 1700;
1246 rd->thresh_mult[THR_COMP_NEW_NEARL3A] += 1700;
1247 rd->thresh_mult[THR_COMP_NEW_NEWL3A] += 2000;
1248 rd->thresh_mult[THR_COMP_ZERO_ZEROL3A] += 2500;
1249#endif // CONFIG_EXT_REFS
1250
Yaowu Xuc27fc142016-08-22 16:08:15 -07001251 rd->thresh_mult[THR_COMP_NEAR_NEARGA] += 1200;
1252 rd->thresh_mult[THR_COMP_NEAREST_NEWGA] += 1500;
1253 rd->thresh_mult[THR_COMP_NEW_NEARESTGA] += 1500;
1254 rd->thresh_mult[THR_COMP_NEAR_NEWGA] += 1700;
1255 rd->thresh_mult[THR_COMP_NEW_NEARGA] += 1700;
1256 rd->thresh_mult[THR_COMP_NEW_NEWGA] += 2000;
1257 rd->thresh_mult[THR_COMP_ZERO_ZEROGA] += 2500;
1258
1259#if CONFIG_EXT_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001260 rd->thresh_mult[THR_COMP_NEAR_NEARLB] += 1200;
1261 rd->thresh_mult[THR_COMP_NEAREST_NEWLB] += 1500;
1262 rd->thresh_mult[THR_COMP_NEW_NEARESTLB] += 1500;
1263 rd->thresh_mult[THR_COMP_NEAR_NEWLB] += 1700;
1264 rd->thresh_mult[THR_COMP_NEW_NEARLB] += 1700;
1265 rd->thresh_mult[THR_COMP_NEW_NEWLB] += 2000;
1266 rd->thresh_mult[THR_COMP_ZERO_ZEROLB] += 2500;
1267
Yaowu Xuc27fc142016-08-22 16:08:15 -07001268 rd->thresh_mult[THR_COMP_NEAR_NEARL2B] += 1200;
1269 rd->thresh_mult[THR_COMP_NEAREST_NEWL2B] += 1500;
1270 rd->thresh_mult[THR_COMP_NEW_NEARESTL2B] += 1500;
1271 rd->thresh_mult[THR_COMP_NEAR_NEWL2B] += 1700;
1272 rd->thresh_mult[THR_COMP_NEW_NEARL2B] += 1700;
1273 rd->thresh_mult[THR_COMP_NEW_NEWL2B] += 2000;
1274 rd->thresh_mult[THR_COMP_ZERO_ZEROL2B] += 2500;
1275
Yaowu Xuc27fc142016-08-22 16:08:15 -07001276 rd->thresh_mult[THR_COMP_NEAR_NEARL3B] += 1200;
1277 rd->thresh_mult[THR_COMP_NEAREST_NEWL3B] += 1500;
1278 rd->thresh_mult[THR_COMP_NEW_NEARESTL3B] += 1500;
1279 rd->thresh_mult[THR_COMP_NEAR_NEWL3B] += 1700;
1280 rd->thresh_mult[THR_COMP_NEW_NEARL3B] += 1700;
1281 rd->thresh_mult[THR_COMP_NEW_NEWL3B] += 2000;
1282 rd->thresh_mult[THR_COMP_ZERO_ZEROL3B] += 2500;
1283
Yaowu Xuc27fc142016-08-22 16:08:15 -07001284 rd->thresh_mult[THR_COMP_NEAR_NEARGB] += 1200;
1285 rd->thresh_mult[THR_COMP_NEAREST_NEWGB] += 1500;
1286 rd->thresh_mult[THR_COMP_NEW_NEARESTGB] += 1500;
1287 rd->thresh_mult[THR_COMP_NEAR_NEWGB] += 1700;
1288 rd->thresh_mult[THR_COMP_NEW_NEARGB] += 1700;
1289 rd->thresh_mult[THR_COMP_NEW_NEWGB] += 2000;
1290 rd->thresh_mult[THR_COMP_ZERO_ZEROGB] += 2500;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001291
Zoe Liue9b15e22017-07-19 15:53:01 -07001292#if CONFIG_ALTREF2
1293 rd->thresh_mult[THR_COMP_NEAR_NEARLA2] += 1200;
1294 rd->thresh_mult[THR_COMP_NEAREST_NEWLA2] += 1500;
1295 rd->thresh_mult[THR_COMP_NEW_NEARESTLA2] += 1500;
1296 rd->thresh_mult[THR_COMP_NEAR_NEWLA2] += 1700;
1297 rd->thresh_mult[THR_COMP_NEW_NEARLA2] += 1700;
1298 rd->thresh_mult[THR_COMP_NEW_NEWLA2] += 2000;
1299 rd->thresh_mult[THR_COMP_ZERO_ZEROLA2] += 2500;
1300
1301 rd->thresh_mult[THR_COMP_NEAR_NEARL2A2] += 1200;
1302 rd->thresh_mult[THR_COMP_NEAREST_NEWL2A2] += 1500;
1303 rd->thresh_mult[THR_COMP_NEW_NEARESTL2A2] += 1500;
1304 rd->thresh_mult[THR_COMP_NEAR_NEWL2A2] += 1700;
1305 rd->thresh_mult[THR_COMP_NEW_NEARL2A2] += 1700;
1306 rd->thresh_mult[THR_COMP_NEW_NEWL2A2] += 2000;
1307 rd->thresh_mult[THR_COMP_ZERO_ZEROL2A2] += 2500;
1308
1309 rd->thresh_mult[THR_COMP_NEAR_NEARL3A2] += 1200;
1310 rd->thresh_mult[THR_COMP_NEAREST_NEWL3A2] += 1500;
1311 rd->thresh_mult[THR_COMP_NEW_NEARESTL3A2] += 1500;
1312 rd->thresh_mult[THR_COMP_NEAR_NEWL3A2] += 1700;
1313 rd->thresh_mult[THR_COMP_NEW_NEARL3A2] += 1700;
1314 rd->thresh_mult[THR_COMP_NEW_NEWL3A2] += 2000;
1315 rd->thresh_mult[THR_COMP_ZERO_ZEROL3A2] += 2500;
1316
1317 rd->thresh_mult[THR_COMP_NEAR_NEARGA2] += 1200;
1318 rd->thresh_mult[THR_COMP_NEAREST_NEWGA2] += 1500;
1319 rd->thresh_mult[THR_COMP_NEW_NEARESTGA2] += 1500;
1320 rd->thresh_mult[THR_COMP_NEAR_NEWGA2] += 1700;
1321 rd->thresh_mult[THR_COMP_NEW_NEARGA2] += 1700;
1322 rd->thresh_mult[THR_COMP_NEW_NEWGA2] += 2000;
1323 rd->thresh_mult[THR_COMP_ZERO_ZEROGA2] += 2500;
1324#endif // CONFIG_ALTREF2
1325
Zoe Liuc082bbc2017-05-17 13:31:37 -07001326#if CONFIG_EXT_COMP_REFS
Zoe Liuc082bbc2017-05-17 13:31:37 -07001327 rd->thresh_mult[THR_COMP_NEAR_NEARLL2] += 1200;
1328 rd->thresh_mult[THR_COMP_NEAREST_NEWLL2] += 1500;
1329 rd->thresh_mult[THR_COMP_NEW_NEARESTLL2] += 1500;
1330 rd->thresh_mult[THR_COMP_NEAR_NEWLL2] += 1700;
1331 rd->thresh_mult[THR_COMP_NEW_NEARLL2] += 1700;
1332 rd->thresh_mult[THR_COMP_NEW_NEWLL2] += 2000;
1333 rd->thresh_mult[THR_COMP_ZERO_ZEROLL2] += 2500;
1334
Zoe Liufcf5fa22017-06-26 16:00:38 -07001335 rd->thresh_mult[THR_COMP_NEAR_NEARLL3] += 1200;
1336 rd->thresh_mult[THR_COMP_NEAREST_NEWLL3] += 1500;
1337 rd->thresh_mult[THR_COMP_NEW_NEARESTLL3] += 1500;
1338 rd->thresh_mult[THR_COMP_NEAR_NEWLL3] += 1700;
1339 rd->thresh_mult[THR_COMP_NEW_NEARLL3] += 1700;
1340 rd->thresh_mult[THR_COMP_NEW_NEWLL3] += 2000;
1341 rd->thresh_mult[THR_COMP_ZERO_ZEROLL3] += 2500;
1342
Zoe Liuc082bbc2017-05-17 13:31:37 -07001343 rd->thresh_mult[THR_COMP_NEAR_NEARLG] += 1200;
1344 rd->thresh_mult[THR_COMP_NEAREST_NEWLG] += 1500;
1345 rd->thresh_mult[THR_COMP_NEW_NEARESTLG] += 1500;
1346 rd->thresh_mult[THR_COMP_NEAR_NEWLG] += 1700;
1347 rd->thresh_mult[THR_COMP_NEW_NEARLG] += 1700;
1348 rd->thresh_mult[THR_COMP_NEW_NEWLG] += 2000;
1349 rd->thresh_mult[THR_COMP_ZERO_ZEROLG] += 2500;
1350
Zoe Liuc082bbc2017-05-17 13:31:37 -07001351 rd->thresh_mult[THR_COMP_NEAR_NEARBA] += 1200;
1352 rd->thresh_mult[THR_COMP_NEAREST_NEWBA] += 1500;
1353 rd->thresh_mult[THR_COMP_NEW_NEARESTBA] += 1500;
1354 rd->thresh_mult[THR_COMP_NEAR_NEWBA] += 1700;
1355 rd->thresh_mult[THR_COMP_NEW_NEARBA] += 1700;
1356 rd->thresh_mult[THR_COMP_NEW_NEWBA] += 2000;
1357 rd->thresh_mult[THR_COMP_ZERO_ZEROBA] += 2500;
1358#endif // CONFIG_EXT_COMP_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001359#endif // CONFIG_EXT_REFS
1360
1361#else // CONFIG_EXT_INTER
1362
1363 rd->thresh_mult[THR_COMP_NEARLA] += 1500;
1364 rd->thresh_mult[THR_COMP_NEWLA] += 2000;
1365#if CONFIG_EXT_REFS
1366 rd->thresh_mult[THR_COMP_NEARL2A] += 1500;
1367 rd->thresh_mult[THR_COMP_NEWL2A] += 2000;
1368 rd->thresh_mult[THR_COMP_NEARL3A] += 1500;
1369 rd->thresh_mult[THR_COMP_NEWL3A] += 2000;
1370#endif // CONFIG_EXT_REFS
1371 rd->thresh_mult[THR_COMP_NEARGA] += 1500;
1372 rd->thresh_mult[THR_COMP_NEWGA] += 2000;
1373
1374#if CONFIG_EXT_REFS
1375 rd->thresh_mult[THR_COMP_NEARLB] += 1500;
1376 rd->thresh_mult[THR_COMP_NEWLB] += 2000;
1377 rd->thresh_mult[THR_COMP_NEARL2B] += 1500;
1378 rd->thresh_mult[THR_COMP_NEWL2B] += 2000;
1379 rd->thresh_mult[THR_COMP_NEARL3B] += 1500;
1380 rd->thresh_mult[THR_COMP_NEWL3B] += 2000;
1381 rd->thresh_mult[THR_COMP_NEARGB] += 1500;
1382 rd->thresh_mult[THR_COMP_NEWGB] += 2000;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001383
Zoe Liue9b15e22017-07-19 15:53:01 -07001384#if CONFIG_ALTREF2
1385 rd->thresh_mult[THR_COMP_NEARLA2] += 1500;
1386 rd->thresh_mult[THR_COMP_NEWLA2] += 2000;
1387 rd->thresh_mult[THR_COMP_NEARL2A2] += 1500;
1388 rd->thresh_mult[THR_COMP_NEWL2A2] += 2000;
1389 rd->thresh_mult[THR_COMP_NEARL3A2] += 1500;
1390 rd->thresh_mult[THR_COMP_NEWL3A2] += 2000;
1391 rd->thresh_mult[THR_COMP_NEARGA2] += 1500;
1392 rd->thresh_mult[THR_COMP_NEWGA2] += 2000;
1393#endif // CONFIG_ALTREF2
1394
Zoe Liuc082bbc2017-05-17 13:31:37 -07001395#if CONFIG_EXT_COMP_REFS
1396 rd->thresh_mult[THR_COMP_NEARLL2] += 1500;
1397 rd->thresh_mult[THR_COMP_NEWLL2] += 2000;
Zoe Liufcf5fa22017-06-26 16:00:38 -07001398 rd->thresh_mult[THR_COMP_NEARLL3] += 1500;
1399 rd->thresh_mult[THR_COMP_NEWLL3] += 2000;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001400 rd->thresh_mult[THR_COMP_NEARLG] += 1500;
1401 rd->thresh_mult[THR_COMP_NEWLG] += 2000;
1402 rd->thresh_mult[THR_COMP_NEARBA] += 1500;
1403 rd->thresh_mult[THR_COMP_NEWBA] += 2000;
1404#endif // CONFIG_EXT_COMP_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001405#endif // CONFIG_EXT_REFS
1406
1407 rd->thresh_mult[THR_COMP_ZEROLA] += 2500;
1408#if CONFIG_EXT_REFS
1409 rd->thresh_mult[THR_COMP_ZEROL2A] += 2500;
1410 rd->thresh_mult[THR_COMP_ZEROL3A] += 2500;
1411#endif // CONFIG_EXT_REFS
1412 rd->thresh_mult[THR_COMP_ZEROGA] += 2500;
1413
1414#if CONFIG_EXT_REFS
1415 rd->thresh_mult[THR_COMP_ZEROLB] += 2500;
1416 rd->thresh_mult[THR_COMP_ZEROL2B] += 2500;
1417 rd->thresh_mult[THR_COMP_ZEROL3B] += 2500;
1418 rd->thresh_mult[THR_COMP_ZEROGB] += 2500;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001419
Zoe Liue9b15e22017-07-19 15:53:01 -07001420#if CONFIG_ALTREF2
1421 rd->thresh_mult[THR_COMP_ZEROLA2] += 2500;
1422 rd->thresh_mult[THR_COMP_ZEROL2A2] += 2500;
1423 rd->thresh_mult[THR_COMP_ZEROL3A2] += 2500;
1424 rd->thresh_mult[THR_COMP_ZEROGA2] += 2500;
1425#endif // CONFIG_ALTREF2
1426
Zoe Liuc082bbc2017-05-17 13:31:37 -07001427#if CONFIG_EXT_COMP_REFS
1428 rd->thresh_mult[THR_COMP_ZEROLL2] += 2500;
Zoe Liufcf5fa22017-06-26 16:00:38 -07001429 rd->thresh_mult[THR_COMP_ZEROLL3] += 2500;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001430 rd->thresh_mult[THR_COMP_ZEROLG] += 2500;
1431 rd->thresh_mult[THR_COMP_ZEROBA] += 2500;
1432#endif // CONFIG_EXT_COMP_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001433#endif // CONFIG_EXT_REFS
1434
1435#endif // CONFIG_EXT_INTER
1436
1437 rd->thresh_mult[THR_H_PRED] += 2000;
1438 rd->thresh_mult[THR_V_PRED] += 2000;
1439 rd->thresh_mult[THR_D135_PRED] += 2500;
1440 rd->thresh_mult[THR_D207_PRED] += 2500;
1441 rd->thresh_mult[THR_D153_PRED] += 2500;
1442 rd->thresh_mult[THR_D63_PRED] += 2500;
1443 rd->thresh_mult[THR_D117_PRED] += 2500;
1444 rd->thresh_mult[THR_D45_PRED] += 2500;
1445
1446#if CONFIG_EXT_INTER
1447 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROL] += 1500;
1448 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTL] += 1500;
1449 rd->thresh_mult[THR_COMP_INTERINTRA_NEARL] += 1500;
1450 rd->thresh_mult[THR_COMP_INTERINTRA_NEWL] += 2000;
1451
1452#if CONFIG_EXT_REFS
1453 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROL2] += 1500;
1454 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTL2] += 1500;
1455 rd->thresh_mult[THR_COMP_INTERINTRA_NEARL2] += 1500;
1456 rd->thresh_mult[THR_COMP_INTERINTRA_NEWL2] += 2000;
1457
1458 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROL3] += 1500;
1459 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTL3] += 1500;
1460 rd->thresh_mult[THR_COMP_INTERINTRA_NEARL3] += 1500;
1461 rd->thresh_mult[THR_COMP_INTERINTRA_NEWL3] += 2000;
1462#endif // CONFIG_EXT_REFS
1463
1464 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROG] += 1500;
1465 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTG] += 1500;
1466 rd->thresh_mult[THR_COMP_INTERINTRA_NEARG] += 1500;
1467 rd->thresh_mult[THR_COMP_INTERINTRA_NEWG] += 2000;
1468
1469#if CONFIG_EXT_REFS
1470 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROB] += 1500;
1471 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTB] += 1500;
1472 rd->thresh_mult[THR_COMP_INTERINTRA_NEARB] += 1500;
1473 rd->thresh_mult[THR_COMP_INTERINTRA_NEWB] += 2000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001474
1475#if CONFIG_ALTREF2
1476 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROA2] += 1500;
1477 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTA2] += 1500;
1478 rd->thresh_mult[THR_COMP_INTERINTRA_NEARA2] += 1500;
1479 rd->thresh_mult[THR_COMP_INTERINTRA_NEWA2] += 2000;
1480#endif // CONFIG_ALTREF2
Yaowu Xuc27fc142016-08-22 16:08:15 -07001481#endif // CONFIG_EXT_REFS
1482
1483 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROA] += 1500;
1484 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTA] += 1500;
1485 rd->thresh_mult[THR_COMP_INTERINTRA_NEARA] += 1500;
1486 rd->thresh_mult[THR_COMP_INTERINTRA_NEWA] += 2000;
1487#endif // CONFIG_EXT_INTER
1488}
1489
Yaowu Xuf883b422016-08-30 14:01:10 -07001490void av1_set_rd_speed_thresholds_sub8x8(AV1_COMP *cpi) {
Thomas Daede6eca8352017-03-17 14:14:12 -07001491 static const int thresh_mult[MAX_REFS] = {
Yaowu Xuc27fc142016-08-22 16:08:15 -07001492#if CONFIG_EXT_REFS
Thomas Daede6eca8352017-03-17 14:14:12 -07001493 2500,
1494 2500,
1495 2500,
1496 2500,
Zoe Liue9b15e22017-07-19 15:53:01 -07001497#if CONFIG_ALTREF2
1498 2500,
1499#endif // CONFIG_ALTREF2
Thomas Daede6eca8352017-03-17 14:14:12 -07001500 2500,
1501 2500,
1502 4500,
1503 4500,
1504 4500,
1505 4500,
1506 4500,
1507 4500,
1508 4500,
1509 4500,
Zoe Liue9b15e22017-07-19 15:53:01 -07001510#if CONFIG_ALTREF2
1511 4500,
1512 4500,
1513 4500,
1514 4500,
1515#endif // CONFIG_ALTREF2
Thomas Daede6eca8352017-03-17 14:14:12 -07001516 2500
Zoe Liue9b15e22017-07-19 15:53:01 -07001517#else // !CONFIG_EXT_REFS
Thomas Daede6eca8352017-03-17 14:14:12 -07001518 2500,
1519 2500,
1520 2500,
1521 4500,
1522 4500,
1523 2500
Yaowu Xuc27fc142016-08-22 16:08:15 -07001524#endif // CONFIG_EXT_REFS
1525 };
1526 RD_OPT *const rd = &cpi->rd;
Thomas Daede6eca8352017-03-17 14:14:12 -07001527 memcpy(rd->thresh_mult_sub8x8, thresh_mult, sizeof(thresh_mult));
Yaowu Xuc27fc142016-08-22 16:08:15 -07001528}
1529
Yaowu Xuf883b422016-08-30 14:01:10 -07001530void av1_update_rd_thresh_fact(const AV1_COMMON *const cm,
1531 int (*factor_buf)[MAX_MODES], int rd_thresh,
1532 int bsize, int best_mode_index) {
Yaowu Xuc27fc142016-08-22 16:08:15 -07001533 if (rd_thresh > 0) {
Jingning Han9104bed2016-12-14 09:38:00 -08001534#if CONFIG_CB4X4
1535 const int top_mode = MAX_MODES;
1536#else
Yaowu Xuc27fc142016-08-22 16:08:15 -07001537 const int top_mode = bsize < BLOCK_8X8 ? MAX_REFS : MAX_MODES;
Jingning Han9104bed2016-12-14 09:38:00 -08001538#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -07001539 int mode;
1540 for (mode = 0; mode < top_mode; ++mode) {
Yaowu Xuf883b422016-08-30 14:01:10 -07001541 const BLOCK_SIZE min_size = AOMMAX(bsize - 1, BLOCK_4X4);
Urvang Joshicb586f32016-09-20 11:36:33 -07001542 const BLOCK_SIZE max_size = AOMMIN(bsize + 2, (int)cm->sb_size);
Yaowu Xuc27fc142016-08-22 16:08:15 -07001543 BLOCK_SIZE bs;
1544 for (bs = min_size; bs <= max_size; ++bs) {
1545 int *const fact = &factor_buf[bs][mode];
1546 if (mode == best_mode_index) {
1547 *fact -= (*fact >> 4);
1548 } else {
Yaowu Xuf883b422016-08-30 14:01:10 -07001549 *fact = AOMMIN(*fact + RD_THRESH_INC, rd_thresh * RD_THRESH_MAX_FACT);
Yaowu Xuc27fc142016-08-22 16:08:15 -07001550 }
1551 }
1552 }
1553 }
1554}
1555
Yaowu Xuf883b422016-08-30 14:01:10 -07001556int av1_get_intra_cost_penalty(int qindex, int qdelta,
1557 aom_bit_depth_t bit_depth) {
1558 const int q = av1_dc_quant(qindex, qdelta, bit_depth);
Sebastien Alaiwan71e87842017-04-12 16:03:28 +02001559#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -07001560 switch (bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -07001561 case AOM_BITS_8: return 20 * q;
1562 case AOM_BITS_10: return 5 * q;
1563 case AOM_BITS_12: return ROUND_POWER_OF_TWO(5 * q, 2);
Yaowu Xuc27fc142016-08-22 16:08:15 -07001564 default:
Yaowu Xuf883b422016-08-30 14:01:10 -07001565 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -07001566 return -1;
1567 }
1568#else
1569 return 20 * q;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +02001570#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -07001571}