blob: 504b4d97c6768829f7d3c4387c24ade4ff9dd8c3 [file] [log] [blame]
Yaowu Xuc27fc142016-08-22 16:08:15 -07001/*
Yaowu Xu2ab7ff02016-09-02 12:04:54 -07002 * Copyright (c) 2016, Alliance for Open Media. All rights reserved
Yaowu Xuc27fc142016-08-22 16:08:15 -07003 *
Yaowu Xu2ab7ff02016-09-02 12:04:54 -07004 * This source code is subject to the terms of the BSD 2 Clause License and
5 * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
6 * was not distributed with this source code in the LICENSE file, you can
7 * obtain it at www.aomedia.org/license/software. If the Alliance for Open
8 * Media Patent License 1.0 was not distributed with this source code in the
9 * PATENTS file, you can obtain it at www.aomedia.org/license/patent.
Yaowu Xuc27fc142016-08-22 16:08:15 -070010 */
11
12#include <assert.h>
13#include <math.h>
14#include <stdio.h>
15
Yaowu Xuf883b422016-08-30 14:01:10 -070016#include "./av1_rtcd.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070017
Yaowu Xuf883b422016-08-30 14:01:10 -070018#include "aom_dsp/aom_dsp_common.h"
19#include "aom_mem/aom_mem.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070020#include "aom_ports/bitops.h"
21#include "aom_ports/mem.h"
22#include "aom_ports/system_state.h"
23
24#include "av1/common/common.h"
25#include "av1/common/entropy.h"
26#include "av1/common/entropymode.h"
27#include "av1/common/mvref_common.h"
28#include "av1/common/pred_common.h"
29#include "av1/common/quant_common.h"
30#include "av1/common/reconinter.h"
31#include "av1/common/reconintra.h"
32#include "av1/common/seg_common.h"
33
Tom Finegan17ce8b12017-02-08 12:46:31 -080034#include "av1/encoder/av1_quantize.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070035#include "av1/encoder/cost.h"
36#include "av1/encoder/encodemb.h"
37#include "av1/encoder/encodemv.h"
38#include "av1/encoder/encoder.h"
39#include "av1/encoder/mcomp.h"
Yaowu Xuc27fc142016-08-22 16:08:15 -070040#include "av1/encoder/ratectrl.h"
41#include "av1/encoder/rd.h"
42#include "av1/encoder/tokenize.h"
43
44#define RD_THRESH_POW 1.25
45
46// Factor to weigh the rate for switchable interp filters.
47#define SWITCHABLE_INTERP_RATE_FACTOR 1
48
Yaowu Xuc27fc142016-08-22 16:08:15 -070049// The baseline rd thresholds for breaking out of the rd loop for
50// certain modes are assumed to be based on 8x8 blocks.
51// This table is used to correct for block size.
52// The factors here are << 2 (2 = x0.5, 32 = x8 etc).
Rupert Swarbrick93c39e92017-07-12 11:11:02 +010053static const uint8_t rd_thresh_block_size_factor[BLOCK_SIZES_ALL] = {
Timothy B. Terriberry81ec2612017-04-26 16:53:47 -070054#if CONFIG_CHROMA_2X2 || CONFIG_CHROMA_SUB8X8
Jingning Hanf1702dd2016-11-30 21:17:59 -080055 2, 2, 2,
56#endif
Rupert Swarbrick72678572017-08-02 12:05:26 +010057 2, 3, 3, 4, 6, 6, 8, 12, 12, 16, 24, 24, 32,
Yaowu Xuc27fc142016-08-22 16:08:15 -070058#if CONFIG_EXT_PARTITION
Rupert Swarbrick93c39e92017-07-12 11:11:02 +010059 48, 48, 64,
Yaowu Xuc27fc142016-08-22 16:08:15 -070060#endif // CONFIG_EXT_PARTITION
Rupert Swarbrick72678572017-08-02 12:05:26 +010061 4, 4, 8, 8, 16, 16
Yaowu Xuc27fc142016-08-22 16:08:15 -070062};
63
Yue Chenb23d00a2017-07-28 17:01:21 -070064void av1_fill_mode_rates(AV1_COMMON *const cm, MACROBLOCK *x,
65 FRAME_CONTEXT *fc) {
Yaowu Xuc27fc142016-08-22 16:08:15 -070066 int i, j;
67
Yue Chenb23d00a2017-07-28 17:01:21 -070068 if (cm->frame_type == KEY_FRAME) {
Yue Chenb23d00a2017-07-28 17:01:21 -070069 for (i = 0; i < PARTITION_CONTEXTS_PRIMARY; ++i)
Yue Chenba47c842017-08-02 16:07:59 -070070 av1_cost_tokens_from_cdf(x->partition_cost[i], fc->partition_cdf[i],
71 NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -070072#if CONFIG_UNPOISON_PARTITION_CTX
73 for (; i < PARTITION_CONTEXTS_PRIMARY + PARTITION_BLOCK_SIZES; ++i) {
74 aom_prob p = fc->partition_prob[i][PARTITION_VERT];
75 assert(p > 0);
76 x->partition_cost[i][PARTITION_NONE] = INT_MAX;
77 x->partition_cost[i][PARTITION_HORZ] = INT_MAX;
78 x->partition_cost[i][PARTITION_VERT] = av1_cost_bit(p, 0);
79 x->partition_cost[i][PARTITION_SPLIT] = av1_cost_bit(p, 1);
80 }
81 for (; i < PARTITION_CONTEXTS_PRIMARY + 2 * PARTITION_BLOCK_SIZES; ++i) {
82 aom_prob p = fc->partition_prob[i][PARTITION_HORZ];
83 assert(p > 0);
84 x->partition_cost[i][PARTITION_NONE] = INT_MAX;
85 x->partition_cost[i][PARTITION_HORZ] = av1_cost_bit(p, 0);
86 x->partition_cost[i][PARTITION_VERT] = INT_MAX;
87 x->partition_cost[i][PARTITION_SPLIT] = av1_cost_bit(p, 1);
88 }
89 x->partition_cost[PARTITION_CONTEXTS][PARTITION_NONE] = INT_MAX;
90 x->partition_cost[PARTITION_CONTEXTS][PARTITION_HORZ] = INT_MAX;
91 x->partition_cost[PARTITION_CONTEXTS][PARTITION_VERT] = INT_MAX;
92 x->partition_cost[PARTITION_CONTEXTS][PARTITION_SPLIT] = 0;
93#endif // CONFIG_UNPOISON_PARTITION_CTX
94 }
95
Yaowu Xuc27fc142016-08-22 16:08:15 -070096 for (i = 0; i < INTRA_MODES; ++i)
97 for (j = 0; j < INTRA_MODES; ++j)
Yue Chenb23d00a2017-07-28 17:01:21 -070098 av1_cost_tokens_from_cdf(x->y_mode_costs[i][j], av1_kf_y_mode_cdf[i][j],
Nathan E. Egge693eedd2017-06-29 20:01:58 -040099 av1_intra_mode_inv);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700100
101 for (i = 0; i < BLOCK_SIZE_GROUPS; ++i)
Yue Chenb23d00a2017-07-28 17:01:21 -0700102 av1_cost_tokens_from_cdf(x->mbmode_cost[i], fc->y_mode_cdf[i],
Nathan E. Egge693eedd2017-06-29 20:01:58 -0400103 av1_intra_mode_inv);
Luc Trudeau6e1cd782017-06-21 13:52:36 -0400104 const int *uv_mode_inv_map =
105#if CONFIG_CFL
106 // CfL codes the uv_mode without reordering it
107 NULL;
108#else
109 av1_intra_mode_inv;
110#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700111 for (i = 0; i < INTRA_MODES; ++i)
Yue Chenb23d00a2017-07-28 17:01:21 -0700112 av1_cost_tokens_from_cdf(x->intra_uv_mode_cost[i], fc->uv_mode_cdf[i],
Luc Trudeau6e1cd782017-06-21 13:52:36 -0400113 uv_mode_inv_map);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700114
115 for (i = 0; i < SWITCHABLE_FILTER_CONTEXTS; ++i)
Yue Chenba47c842017-08-02 16:07:59 -0700116 av1_cost_tokens_from_cdf(x->switchable_interp_costs[i],
117 fc->switchable_interp_cdf[i],
118 av1_switchable_interp_inv);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700119
120 for (i = 0; i < PALETTE_BLOCK_SIZES; ++i) {
Yue Chenb23d00a2017-07-28 17:01:21 -0700121 av1_cost_tokens_from_cdf(x->palette_y_size_cost[i],
hui su466ae062017-07-25 16:55:51 -0700122 fc->palette_y_size_cdf[i], NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700123 av1_cost_tokens_from_cdf(x->palette_uv_size_cost[i],
hui su466ae062017-07-25 16:55:51 -0700124 fc->palette_uv_size_cdf[i], NULL);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700125 }
126
Alex Converse92109812017-02-22 10:21:40 -0800127 for (i = 0; i < PALETTE_SIZES; ++i) {
Urvang Joshi23a61112017-01-30 14:59:27 -0800128 for (j = 0; j < PALETTE_COLOR_INDEX_CONTEXTS; ++j) {
Yue Chenb23d00a2017-07-28 17:01:21 -0700129 av1_cost_tokens_from_cdf(x->palette_y_color_cost[i][j],
hui su466ae062017-07-25 16:55:51 -0700130 fc->palette_y_color_index_cdf[i][j], NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700131 av1_cost_tokens_from_cdf(x->palette_uv_color_cost[i][j],
hui su466ae062017-07-25 16:55:51 -0700132 fc->palette_uv_color_index_cdf[i][j], NULL);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700133 }
Urvang Joshib100db72016-10-12 16:28:56 -0700134 }
Sarah Parker5c6744b2017-08-25 17:27:45 -0700135#if CONFIG_MRC_TX
136 for (i = 0; i < PALETTE_SIZES; ++i) {
137 for (j = 0; j < PALETTE_COLOR_INDEX_CONTEXTS; ++j) {
138 av1_cost_tokens_from_cdf(x->mrc_mask_inter_cost[i][j],
139 fc->mrc_mask_inter_cdf[i][j], NULL);
140 av1_cost_tokens_from_cdf(x->mrc_mask_intra_cost[i][j],
141 fc->mrc_mask_intra_cdf[i][j], NULL);
142 }
143 }
144#endif // CONFIG_MRC_TX
Yaowu Xuc27fc142016-08-22 16:08:15 -0700145
David Michael Barr38e560c2017-08-16 21:46:37 +0900146#if CONFIG_CFL
147 int sign_cost[CFL_JOINT_SIGNS];
148 av1_cost_tokens_from_cdf(sign_cost, fc->cfl_sign_cdf, NULL);
149 for (int joint_sign = 0; joint_sign < CFL_JOINT_SIGNS; joint_sign++) {
150 const aom_cdf_prob *cdf_u = fc->cfl_alpha_cdf[CFL_CONTEXT_U(joint_sign)];
151 const aom_cdf_prob *cdf_v = fc->cfl_alpha_cdf[CFL_CONTEXT_V(joint_sign)];
152 int *cost_u = x->cfl_cost[joint_sign][CFL_PRED_U];
153 int *cost_v = x->cfl_cost[joint_sign][CFL_PRED_V];
154 if (CFL_SIGN_U(joint_sign) == CFL_SIGN_ZERO)
155 memset(cost_u, 0, CFL_ALPHABET_SIZE * sizeof(*cost_u));
156 else
157 av1_cost_tokens_from_cdf(cost_u, cdf_u, NULL);
158 if (CFL_SIGN_V(joint_sign) == CFL_SIGN_ZERO)
159 memset(cost_v, 0, CFL_ALPHABET_SIZE * sizeof(*cost_v));
160 else
161 av1_cost_tokens_from_cdf(cost_v, cdf_v, NULL);
162 for (int u = 0; u < CFL_ALPHABET_SIZE; u++)
163 cost_u[u] += sign_cost[joint_sign];
164 }
165#endif // CONFIG_CFL
166
Jingning Hanaae72a62016-10-25 15:35:29 -0700167 for (i = 0; i < MAX_TX_DEPTH; ++i)
Yaowu Xuc27fc142016-08-22 16:08:15 -0700168 for (j = 0; j < TX_SIZE_CONTEXTS; ++j)
Yue Chenba47c842017-08-02 16:07:59 -0700169 av1_cost_tokens_from_cdf(x->tx_size_cost[i][j], fc->tx_size_cdf[i][j],
170 NULL);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700171
172#if CONFIG_EXT_TX
173 for (i = TX_4X4; i < EXT_TX_SIZES; ++i) {
174 int s;
175 for (s = 1; s < EXT_TX_SETS_INTER; ++s) {
176 if (use_inter_ext_tx_for_txsize[s][i]) {
Yue Chenba47c842017-08-02 16:07:59 -0700177 av1_cost_tokens_from_cdf(x->inter_tx_type_costs[s][i],
178 fc->inter_ext_tx_cdf[s][i],
179 av1_ext_tx_inter_inv[s]);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700180 }
181 }
182 for (s = 1; s < EXT_TX_SETS_INTRA; ++s) {
183 if (use_intra_ext_tx_for_txsize[s][i]) {
184 for (j = 0; j < INTRA_MODES; ++j)
Yue Chenba47c842017-08-02 16:07:59 -0700185 av1_cost_tokens_from_cdf(x->intra_tx_type_costs[s][i][j],
186 fc->intra_ext_tx_cdf[s][i][j],
187 av1_ext_tx_intra_inv[s]);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700188 }
189 }
190 }
191#else
192 for (i = TX_4X4; i < EXT_TX_SIZES; ++i) {
193 for (j = 0; j < TX_TYPES; ++j)
Yue Chenba47c842017-08-02 16:07:59 -0700194 av1_cost_tokens_from_cdf(x->intra_tx_type_costs[i][j],
195 fc->intra_ext_tx_cdf[i][j], av1_ext_tx_inv);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700196 }
197 for (i = TX_4X4; i < EXT_TX_SIZES; ++i) {
Yue Chenba47c842017-08-02 16:07:59 -0700198 av1_cost_tokens_from_cdf(x->inter_tx_type_costs[i], fc->inter_ext_tx_cdf[i],
199 av1_ext_tx_inv);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700200 }
201#endif // CONFIG_EXT_TX
202#if CONFIG_EXT_INTRA
hui sueda3d762016-12-06 16:58:23 -0800203#if CONFIG_INTRA_INTERP
Yaowu Xuc27fc142016-08-22 16:08:15 -0700204 for (i = 0; i < INTRA_FILTERS + 1; ++i)
Yue Chenba47c842017-08-02 16:07:59 -0700205 av1_cost_tokens_from_cdf(x->intra_filter_cost[i], fc->intra_filter_cdf[i],
206 NULL);
hui sueda3d762016-12-06 16:58:23 -0800207#endif // CONFIG_INTRA_INTERP
Yaowu Xuc27fc142016-08-22 16:08:15 -0700208#endif // CONFIG_EXT_INTRA
Debargha Mukherjee5cd2ab92016-09-08 15:15:17 -0700209#if CONFIG_LOOP_RESTORATION
Yue Chenb23d00a2017-07-28 17:01:21 -0700210 av1_cost_tokens(x->switchable_restore_cost, fc->switchable_restore_prob,
Debargha Mukherjee5cd2ab92016-09-08 15:15:17 -0700211 av1_switchable_restore_tree);
212#endif // CONFIG_LOOP_RESTORATION
Yue Chenb23d00a2017-07-28 17:01:21 -0700213
214 if (!frame_is_intra_only(cm)) {
215 for (i = 0; i < NEWMV_MODE_CONTEXTS; ++i) {
Yue Chenba47c842017-08-02 16:07:59 -0700216#if CONFIG_NEW_MULTISYMBOL
217 av1_cost_tokens_from_cdf(x->newmv_mode_cost[i], fc->newmv_cdf[i], NULL);
218#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700219 x->newmv_mode_cost[i][0] = av1_cost_bit(fc->newmv_prob[i], 0);
220 x->newmv_mode_cost[i][1] = av1_cost_bit(fc->newmv_prob[i], 1);
Yue Chenba47c842017-08-02 16:07:59 -0700221#endif
Yue Chenb23d00a2017-07-28 17:01:21 -0700222 }
223
224 for (i = 0; i < ZEROMV_MODE_CONTEXTS; ++i) {
Yue Chenba47c842017-08-02 16:07:59 -0700225#if CONFIG_NEW_MULTISYMBOL
226 av1_cost_tokens_from_cdf(x->zeromv_mode_cost[i], fc->zeromv_cdf[i], NULL);
227#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700228 x->zeromv_mode_cost[i][0] = av1_cost_bit(fc->zeromv_prob[i], 0);
229 x->zeromv_mode_cost[i][1] = av1_cost_bit(fc->zeromv_prob[i], 1);
Yue Chenba47c842017-08-02 16:07:59 -0700230#endif
Yue Chenb23d00a2017-07-28 17:01:21 -0700231 }
232
233 for (i = 0; i < REFMV_MODE_CONTEXTS; ++i) {
Yue Chenba47c842017-08-02 16:07:59 -0700234#if CONFIG_NEW_MULTISYMBOL
235 av1_cost_tokens_from_cdf(x->refmv_mode_cost[i], fc->refmv_cdf[i], NULL);
236#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700237 x->refmv_mode_cost[i][0] = av1_cost_bit(fc->refmv_prob[i], 0);
238 x->refmv_mode_cost[i][1] = av1_cost_bit(fc->refmv_prob[i], 1);
Yue Chenba47c842017-08-02 16:07:59 -0700239#endif
Yue Chenb23d00a2017-07-28 17:01:21 -0700240 }
241
242 for (i = 0; i < DRL_MODE_CONTEXTS; ++i) {
Yue Chenba47c842017-08-02 16:07:59 -0700243#if CONFIG_NEW_MULTISYMBOL
244 av1_cost_tokens_from_cdf(x->drl_mode_cost0[i], fc->drl_cdf[i], NULL);
245#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700246 x->drl_mode_cost0[i][0] = av1_cost_bit(fc->drl_prob[i], 0);
247 x->drl_mode_cost0[i][1] = av1_cost_bit(fc->drl_prob[i], 1);
Yue Chenba47c842017-08-02 16:07:59 -0700248#endif
Yue Chenb23d00a2017-07-28 17:01:21 -0700249 }
250#if CONFIG_EXT_INTER
251 for (i = 0; i < INTER_MODE_CONTEXTS; ++i)
Yue Chenba47c842017-08-02 16:07:59 -0700252 av1_cost_tokens_from_cdf(x->inter_compound_mode_cost[i],
253 fc->inter_compound_mode_cdf[i], NULL);
Yue Chena4245512017-08-31 11:58:08 -0700254 for (i = 0; i < BLOCK_SIZES_ALL; ++i)
255 av1_cost_tokens_from_cdf(x->compound_type_cost[i],
256 fc->compound_type_cdf[i], NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700257#if CONFIG_COMPOUND_SINGLEREF
258 for (i = 0; i < INTER_MODE_CONTEXTS; ++i)
Yue Chenba47c842017-08-02 16:07:59 -0700259 av1_cost_tokens_from_cdf(x->inter_singleref_comp_mode_cost[i],
260 fc->inter_singleref_comp_mode_cdf[i], NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700261#endif // CONFIG_COMPOUND_SINGLEREF
262#if CONFIG_INTERINTRA
263 for (i = 0; i < BLOCK_SIZE_GROUPS; ++i)
Yue Chenba47c842017-08-02 16:07:59 -0700264 av1_cost_tokens_from_cdf(x->interintra_mode_cost[i],
265 fc->interintra_mode_cdf[i], NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700266#endif // CONFIG_INTERINTRA
267#endif // CONFIG_EXT_INTER
268#if CONFIG_MOTION_VAR || CONFIG_WARPED_MOTION
269 for (i = BLOCK_8X8; i < BLOCK_SIZES_ALL; i++) {
Wei-Ting Lin060f7f22017-08-01 10:26:24 -0700270 av1_cost_tokens_from_cdf(x->motion_mode_cost[i], fc->motion_mode_cdf[i],
271 NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700272 }
273#if CONFIG_MOTION_VAR && CONFIG_WARPED_MOTION
274 for (i = BLOCK_8X8; i < BLOCK_SIZES_ALL; i++) {
Yue Chenba47c842017-08-02 16:07:59 -0700275#if CONFIG_NEW_MULTISYMBOL
276 av1_cost_tokens_from_cdf(x->motion_mode_cost1[i], fc->obmc_cdf[i], NULL);
277#else
Yue Chenb23d00a2017-07-28 17:01:21 -0700278 x->motion_mode_cost1[i][0] = av1_cost_bit(fc->obmc_prob[i], 0);
279 x->motion_mode_cost1[i][1] = av1_cost_bit(fc->obmc_prob[i], 1);
Yue Chenba47c842017-08-02 16:07:59 -0700280#endif
Yue Chenb23d00a2017-07-28 17:01:21 -0700281 }
282#endif // CONFIG_MOTION_VAR && CONFIG_WARPED_MOTION
283#if CONFIG_MOTION_VAR && CONFIG_NCOBMC_ADAPT_WEIGHT
284 for (i = ADAPT_OVERLAP_BLOCK_8X8; i < ADAPT_OVERLAP_BLOCKS; ++i) {
Wei-Ting Lin060f7f22017-08-01 10:26:24 -0700285 av1_cost_tokens_from_cdf(x->ncobmc_mode_cost[i], fc->ncobmc_mode_cdf[i],
286 NULL);
Yue Chenb23d00a2017-07-28 17:01:21 -0700287 }
288#endif // CONFIG_MOTION_VAR && CONFIG_NCOBMC_ADAPT_WEIGHT
289#endif // CONFIG_MOTION_VAR || CONFIG_WARPED_MOTION
290 }
Yaowu Xuc27fc142016-08-22 16:08:15 -0700291}
292
Yaowu Xuc27fc142016-08-22 16:08:15 -0700293// Values are now correlated to quantizer.
294static int sad_per_bit16lut_8[QINDEX_RANGE];
295static int sad_per_bit4lut_8[QINDEX_RANGE];
296
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200297#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700298static int sad_per_bit16lut_10[QINDEX_RANGE];
299static int sad_per_bit4lut_10[QINDEX_RANGE];
300static int sad_per_bit16lut_12[QINDEX_RANGE];
301static int sad_per_bit4lut_12[QINDEX_RANGE];
302#endif
303
304static void init_me_luts_bd(int *bit16lut, int *bit4lut, int range,
Yaowu Xuf883b422016-08-30 14:01:10 -0700305 aom_bit_depth_t bit_depth) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700306 int i;
307 // Initialize the sad lut tables using a formulaic calculation for now.
308 // This is to make it easier to resolve the impact of experimental changes
309 // to the quantizer tables.
310 for (i = 0; i < range; i++) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700311 const double q = av1_convert_qindex_to_q(i, bit_depth);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700312 bit16lut[i] = (int)(0.0418 * q + 2.4107);
313 bit4lut[i] = (int)(0.063 * q + 2.742);
314 }
315}
316
Yaowu Xuf883b422016-08-30 14:01:10 -0700317void av1_init_me_luts(void) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700318 init_me_luts_bd(sad_per_bit16lut_8, sad_per_bit4lut_8, QINDEX_RANGE,
Yaowu Xuf883b422016-08-30 14:01:10 -0700319 AOM_BITS_8);
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200320#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700321 init_me_luts_bd(sad_per_bit16lut_10, sad_per_bit4lut_10, QINDEX_RANGE,
Yaowu Xuf883b422016-08-30 14:01:10 -0700322 AOM_BITS_10);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700323 init_me_luts_bd(sad_per_bit16lut_12, sad_per_bit4lut_12, QINDEX_RANGE,
Yaowu Xuf883b422016-08-30 14:01:10 -0700324 AOM_BITS_12);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700325#endif
326}
327
328static const int rd_boost_factor[16] = { 64, 32, 32, 32, 24, 16, 12, 12,
329 8, 8, 4, 4, 2, 2, 1, 0 };
330static const int rd_frame_type_factor[FRAME_UPDATE_TYPES] = {
331 128, 144, 128, 128, 144,
332#if CONFIG_EXT_REFS
333 // TODO(zoeliu): To adjust further following factor values.
Zoe Liu3ac20932017-08-30 16:35:55 -0700334 128, 128, 128,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700335 // TODO(weitinglin): We should investigate if the values should be the same
336 // as the value used by OVERLAY frame
Zoe Liu3ac20932017-08-30 16:35:55 -0700337 144, // INTNL_OVERLAY_UPDATE
Zoe Liue9b15e22017-07-19 15:53:01 -0700338 128 // INTNL_ARF_UPDATE
Yaowu Xuc27fc142016-08-22 16:08:15 -0700339#endif // CONFIG_EXT_REFS
340};
341
Yaowu Xuf883b422016-08-30 14:01:10 -0700342int av1_compute_rd_mult(const AV1_COMP *cpi, int qindex) {
343 const int64_t q = av1_dc_quant(qindex, 0, cpi->common.bit_depth);
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200344#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700345 int64_t rdmult = 0;
346 switch (cpi->common.bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700347 case AOM_BITS_8: rdmult = 88 * q * q / 24; break;
348 case AOM_BITS_10: rdmult = ROUND_POWER_OF_TWO(88 * q * q / 24, 4); break;
349 case AOM_BITS_12: rdmult = ROUND_POWER_OF_TWO(88 * q * q / 24, 8); break;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700350 default:
Yaowu Xuf883b422016-08-30 14:01:10 -0700351 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -0700352 return -1;
353 }
354#else
355 int64_t rdmult = 88 * q * q / 24;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200356#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700357 if (cpi->oxcf.pass == 2 && (cpi->common.frame_type != KEY_FRAME)) {
358 const GF_GROUP *const gf_group = &cpi->twopass.gf_group;
359 const FRAME_UPDATE_TYPE frame_type = gf_group->update_type[gf_group->index];
Yaowu Xuf883b422016-08-30 14:01:10 -0700360 const int boost_index = AOMMIN(15, (cpi->rc.gfu_boost / 100));
Yaowu Xuc27fc142016-08-22 16:08:15 -0700361
362 rdmult = (rdmult * rd_frame_type_factor[frame_type]) >> 7;
363 rdmult += ((rdmult * rd_boost_factor[boost_index]) >> 7);
364 }
365 if (rdmult < 1) rdmult = 1;
366 return (int)rdmult;
367}
368
Yaowu Xuf883b422016-08-30 14:01:10 -0700369static int compute_rd_thresh_factor(int qindex, aom_bit_depth_t bit_depth) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700370 double q;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200371#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700372 switch (bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700373 case AOM_BITS_8: q = av1_dc_quant(qindex, 0, AOM_BITS_8) / 4.0; break;
374 case AOM_BITS_10: q = av1_dc_quant(qindex, 0, AOM_BITS_10) / 16.0; break;
375 case AOM_BITS_12: q = av1_dc_quant(qindex, 0, AOM_BITS_12) / 64.0; break;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700376 default:
Yaowu Xuf883b422016-08-30 14:01:10 -0700377 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -0700378 return -1;
379 }
380#else
381 (void)bit_depth;
Yaowu Xuf883b422016-08-30 14:01:10 -0700382 q = av1_dc_quant(qindex, 0, AOM_BITS_8) / 4.0;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200383#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700384 // TODO(debargha): Adjust the function below.
Yaowu Xuf883b422016-08-30 14:01:10 -0700385 return AOMMAX((int)(pow(q, RD_THRESH_POW) * 5.12), 8);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700386}
387
Yaowu Xuf883b422016-08-30 14:01:10 -0700388void av1_initialize_me_consts(const AV1_COMP *cpi, MACROBLOCK *x, int qindex) {
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200389#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700390 switch (cpi->common.bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -0700391 case AOM_BITS_8:
Yaowu Xuc27fc142016-08-22 16:08:15 -0700392 x->sadperbit16 = sad_per_bit16lut_8[qindex];
393 x->sadperbit4 = sad_per_bit4lut_8[qindex];
394 break;
Yaowu Xuf883b422016-08-30 14:01:10 -0700395 case AOM_BITS_10:
Yaowu Xuc27fc142016-08-22 16:08:15 -0700396 x->sadperbit16 = sad_per_bit16lut_10[qindex];
397 x->sadperbit4 = sad_per_bit4lut_10[qindex];
398 break;
Yaowu Xuf883b422016-08-30 14:01:10 -0700399 case AOM_BITS_12:
Yaowu Xuc27fc142016-08-22 16:08:15 -0700400 x->sadperbit16 = sad_per_bit16lut_12[qindex];
401 x->sadperbit4 = sad_per_bit4lut_12[qindex];
402 break;
403 default:
Yaowu Xuf883b422016-08-30 14:01:10 -0700404 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -0700405 }
406#else
407 (void)cpi;
408 x->sadperbit16 = sad_per_bit16lut_8[qindex];
409 x->sadperbit4 = sad_per_bit4lut_8[qindex];
Sebastien Alaiwan71e87842017-04-12 16:03:28 +0200410#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -0700411}
412
Yaowu Xuf883b422016-08-30 14:01:10 -0700413static void set_block_thresholds(const AV1_COMMON *cm, RD_OPT *rd) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700414 int i, bsize, segment_id;
415
416 for (segment_id = 0; segment_id < MAX_SEGMENTS; ++segment_id) {
417 const int qindex =
Yaowu Xuf883b422016-08-30 14:01:10 -0700418 clamp(av1_get_qindex(&cm->seg, segment_id, cm->base_qindex) +
Yaowu Xuc27fc142016-08-22 16:08:15 -0700419 cm->y_dc_delta_q,
420 0, MAXQ);
421 const int q = compute_rd_thresh_factor(qindex, cm->bit_depth);
422
Rupert Swarbrick93c39e92017-07-12 11:11:02 +0100423 for (bsize = 0; bsize < BLOCK_SIZES_ALL; ++bsize) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700424 // Threshold here seems unnecessarily harsh but fine given actual
425 // range of values used for cpi->sf.thresh_mult[].
426 const int t = q * rd_thresh_block_size_factor[bsize];
427 const int thresh_max = INT_MAX / t;
428
Jingning Han9104bed2016-12-14 09:38:00 -0800429#if CONFIG_CB4X4
430 for (i = 0; i < MAX_MODES; ++i)
431 rd->threshes[segment_id][bsize][i] = rd->thresh_mult[i] < thresh_max
432 ? rd->thresh_mult[i] * t / 4
433 : INT_MAX;
434#else
Yaowu Xuc27fc142016-08-22 16:08:15 -0700435 if (bsize >= BLOCK_8X8) {
436 for (i = 0; i < MAX_MODES; ++i)
437 rd->threshes[segment_id][bsize][i] = rd->thresh_mult[i] < thresh_max
438 ? rd->thresh_mult[i] * t / 4
439 : INT_MAX;
440 } else {
441 for (i = 0; i < MAX_REFS; ++i)
442 rd->threshes[segment_id][bsize][i] =
443 rd->thresh_mult_sub8x8[i] < thresh_max
444 ? rd->thresh_mult_sub8x8[i] * t / 4
445 : INT_MAX;
446 }
Jingning Han9104bed2016-12-14 09:38:00 -0800447#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700448 }
449 }
450}
451
Yaowu Xu4306b6e2016-09-27 12:55:32 -0700452void av1_set_mvcost(MACROBLOCK *x, MV_REFERENCE_FRAME ref_frame, int ref,
453 int ref_mv_idx) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700454 MB_MODE_INFO_EXT *mbmi_ext = x->mbmi_ext;
Yaowu Xu4306b6e2016-09-27 12:55:32 -0700455 int8_t rf_type = av1_ref_frame_type(x->e_mbd.mi[0]->mbmi.ref_frame);
456 int nmv_ctx = av1_nmv_ctx(mbmi_ext->ref_mv_count[rf_type],
457 mbmi_ext->ref_mv_stack[rf_type], ref, ref_mv_idx);
458 (void)ref_frame;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700459 x->mvcost = x->mv_cost_stack[nmv_ctx];
460 x->nmvjointcost = x->nmv_vec_cost[nmv_ctx];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700461}
Yaowu Xuc27fc142016-08-22 16:08:15 -0700462
Jingning Handfd72322017-08-09 14:04:12 -0700463#if CONFIG_LV_MAP
Jingning Han24b0cf92017-08-18 22:50:18 -0700464#if !LV_MAP_PROB
Jingning Handfd72322017-08-09 14:04:12 -0700465static void get_rate_cost(aom_prob p, int cost[2]) {
466 cost[0] = av1_cost_bit(p, 0);
467 cost[1] = av1_cost_bit(p, 1);
468}
Jingning Han24b0cf92017-08-18 22:50:18 -0700469#endif // !LV_MAP_PROB
Jingning Handfd72322017-08-09 14:04:12 -0700470
471void av1_fill_coeff_costs(MACROBLOCK *x, FRAME_CONTEXT *fc) {
472 for (TX_SIZE tx_size = 0; tx_size < TX_SIZES; ++tx_size) {
473 for (int plane = 0; plane < PLANE_TYPES; ++plane) {
474 LV_MAP_COEFF_COST *pcost = &x->coeff_costs[tx_size][plane];
475
Jingning Han24b0cf92017-08-18 22:50:18 -0700476#if LV_MAP_PROB
477 for (int ctx = 0; ctx < TXB_SKIP_CONTEXTS; ++ctx)
478 av1_cost_tokens_from_cdf(pcost->txb_skip_cost[ctx],
479 fc->txb_skip_cdf[tx_size][ctx], NULL);
480
481 for (int ctx = 0; ctx < SIG_COEF_CONTEXTS; ++ctx)
482 av1_cost_tokens_from_cdf(pcost->nz_map_cost[ctx],
483 fc->nz_map_cdf[tx_size][plane][ctx], NULL);
484
485 for (int ctx = 0; ctx < EOB_COEF_CONTEXTS; ++ctx)
486 av1_cost_tokens_from_cdf(pcost->eob_cost[ctx],
487 fc->eob_flag_cdf[tx_size][plane][ctx], NULL);
488
489 for (int ctx = 0; ctx < DC_SIGN_CONTEXTS; ++ctx)
490 av1_cost_tokens_from_cdf(pcost->dc_sign_cost[ctx],
491 fc->dc_sign_cdf[plane][ctx], NULL);
492
493 for (int layer = 0; layer < NUM_BASE_LEVELS; ++layer)
494 for (int ctx = 0; ctx < COEFF_BASE_CONTEXTS; ++ctx)
495 av1_cost_tokens_from_cdf(
496 pcost->base_cost[layer][ctx],
497 fc->coeff_base_cdf[tx_size][plane][layer][ctx], NULL);
498
499 for (int ctx = 0; ctx < LEVEL_CONTEXTS; ++ctx)
500 av1_cost_tokens_from_cdf(pcost->lps_cost[ctx],
501 fc->coeff_lps_cdf[tx_size][plane][ctx], NULL);
502#else
Jingning Handfd72322017-08-09 14:04:12 -0700503 for (int ctx = 0; ctx < TXB_SKIP_CONTEXTS; ++ctx)
504 get_rate_cost(fc->txb_skip[tx_size][ctx], pcost->txb_skip_cost[ctx]);
505
506 for (int ctx = 0; ctx < SIG_COEF_CONTEXTS; ++ctx)
507 get_rate_cost(fc->nz_map[tx_size][plane][ctx], pcost->nz_map_cost[ctx]);
508
509 for (int ctx = 0; ctx < EOB_COEF_CONTEXTS; ++ctx)
510 get_rate_cost(fc->eob_flag[tx_size][plane][ctx], pcost->eob_cost[ctx]);
511
512 for (int ctx = 0; ctx < DC_SIGN_CONTEXTS; ++ctx)
513 get_rate_cost(fc->dc_sign[plane][ctx], pcost->dc_sign_cost[ctx]);
514
515 for (int layer = 0; layer < NUM_BASE_LEVELS; ++layer)
516 for (int ctx = 0; ctx < COEFF_BASE_CONTEXTS; ++ctx)
517 get_rate_cost(fc->coeff_base[tx_size][plane][layer][ctx],
518 pcost->base_cost[layer][ctx]);
519
520 for (int ctx = 0; ctx < LEVEL_CONTEXTS; ++ctx)
521 get_rate_cost(fc->coeff_lps[tx_size][plane][ctx], pcost->lps_cost[ctx]);
Jingning Han24b0cf92017-08-18 22:50:18 -0700522#endif
Jingning Handfd72322017-08-09 14:04:12 -0700523 }
524 }
525}
526#endif
527
hui subd57abe2017-07-24 18:14:03 -0700528void av1_fill_token_costs_from_cdf(av1_coeff_cost *cost,
529 coeff_cdf_model (*cdf)[PLANE_TYPES]) {
hui suc0cf71d2017-07-20 16:38:50 -0700530 for (int tx = 0; tx < TX_SIZES; ++tx) {
531 for (int pt = 0; pt < PLANE_TYPES; ++pt) {
532 for (int rt = 0; rt < REF_TYPES; ++rt) {
533 for (int band = 0; band < COEF_BANDS; ++band) {
534 for (int ctx = 0; ctx < BAND_COEFF_CONTEXTS(band); ++ctx) {
535 av1_cost_tokens_from_cdf(cost[tx][pt][rt][band][ctx],
536 cdf[tx][pt][rt][band][ctx], NULL);
537 }
538 }
539 }
540 }
541 }
542}
543
Yaowu Xuf883b422016-08-30 14:01:10 -0700544void av1_initialize_rd_consts(AV1_COMP *cpi) {
545 AV1_COMMON *const cm = &cpi->common;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700546 MACROBLOCK *const x = &cpi->td.mb;
547 RD_OPT *const rd = &cpi->rd;
James Zern01a9d702017-08-25 19:09:33 +0000548 int nmv_ctx;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700549
Yaowu Xuf883b422016-08-30 14:01:10 -0700550 aom_clear_system_state();
Yaowu Xuc27fc142016-08-22 16:08:15 -0700551
Yaowu Xuf883b422016-08-30 14:01:10 -0700552 rd->RDMULT = av1_compute_rd_mult(cpi, cm->base_qindex + cm->y_dc_delta_q);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700553
554 set_error_per_bit(x, rd->RDMULT);
555
556 set_block_thresholds(cm, rd);
557
James Zern01a9d702017-08-25 19:09:33 +0000558 for (nmv_ctx = 0; nmv_ctx < NMV_CONTEXTS; ++nmv_ctx) {
559 av1_build_nmv_cost_table(
560 x->nmv_vec_cost[nmv_ctx],
561 cm->allow_high_precision_mv ? x->nmvcost_hp[nmv_ctx]
562 : x->nmvcost[nmv_ctx],
563 &cm->fc->nmvc[nmv_ctx], cm->allow_high_precision_mv);
564 }
565 x->mvcost = x->mv_cost_stack[0];
566 x->nmvjointcost = x->nmv_vec_cost[0];
Jingning Hanb3b034d2016-11-29 17:57:14 -0800567
Alex Conversed5d9b6c2017-05-23 15:23:45 -0700568#if CONFIG_INTRABC
569 if (frame_is_intra_only(cm) && cm->allow_screen_content_tools &&
570 cpi->oxcf.pass != 1) {
571 av1_build_nmv_cost_table(
572 x->nmv_vec_cost[0],
573 cm->allow_high_precision_mv ? x->nmvcost_hp[0] : x->nmvcost[0],
574 &cm->fc->ndvc, MV_SUBPEL_NONE);
575 }
576#endif
577
Yue Chenb23d00a2017-07-28 17:01:21 -0700578#if CONFIG_GLOBAL_MOTION
hui subd57abe2017-07-24 18:14:03 -0700579 if (cpi->oxcf.pass != 1) {
Zoe Liubc030ee2017-07-31 15:20:46 -0700580 for (int i = 0; i < TRANS_TYPES; ++i)
Sarah Parker323d5352017-08-17 14:58:03 -0700581#if GLOBAL_TRANS_TYPES > 4
Yue Chenb23d00a2017-07-28 17:01:21 -0700582 cpi->gmtype_cost[i] = (1 + (i > 0 ? GLOBAL_TYPE_BITS : 0))
583 << AV1_PROB_COST_SHIFT;
Sarah Parker323d5352017-08-17 14:58:03 -0700584#else
585 // IDENTITY: 1 bit
586 // TRANSLATION: 3 bits
587 // ROTZOOM: 2 bits
588 // AFFINE: 3 bits
589 cpi->gmtype_cost[i] = (1 + (i > 0 ? (i == ROTZOOM ? 1 : 2) : 0))
590 << AV1_PROB_COST_SHIFT;
591#endif // GLOBAL_TRANS_TYPES > 4
Yaowu Xuc27fc142016-08-22 16:08:15 -0700592 }
hui subd57abe2017-07-24 18:14:03 -0700593#endif // CONFIG_GLOBAL_MOTION
Yaowu Xuc27fc142016-08-22 16:08:15 -0700594}
595
596static void model_rd_norm(int xsq_q10, int *r_q10, int *d_q10) {
597 // NOTE: The tables below must be of the same size.
598
599 // The functions described below are sampled at the four most significant
600 // bits of x^2 + 8 / 256.
601
602 // Normalized rate:
603 // This table models the rate for a Laplacian source with given variance
604 // when quantized with a uniform quantizer with given stepsize. The
605 // closed form expression is:
606 // Rn(x) = H(sqrt(r)) + sqrt(r)*[1 + H(r)/(1 - r)],
607 // where r = exp(-sqrt(2) * x) and x = qpstep / sqrt(variance),
608 // and H(x) is the binary entropy function.
609 static const int rate_tab_q10[] = {
610 65536, 6086, 5574, 5275, 5063, 4899, 4764, 4651, 4553, 4389, 4255, 4142,
611 4044, 3958, 3881, 3811, 3748, 3635, 3538, 3453, 3376, 3307, 3244, 3186,
612 3133, 3037, 2952, 2877, 2809, 2747, 2690, 2638, 2589, 2501, 2423, 2353,
613 2290, 2232, 2179, 2130, 2084, 2001, 1928, 1862, 1802, 1748, 1698, 1651,
614 1608, 1530, 1460, 1398, 1342, 1290, 1243, 1199, 1159, 1086, 1021, 963,
615 911, 864, 821, 781, 745, 680, 623, 574, 530, 490, 455, 424,
616 395, 345, 304, 269, 239, 213, 190, 171, 154, 126, 104, 87,
617 73, 61, 52, 44, 38, 28, 21, 16, 12, 10, 8, 6,
618 5, 3, 2, 1, 1, 1, 0, 0,
619 };
620 // Normalized distortion:
621 // This table models the normalized distortion for a Laplacian source
622 // with given variance when quantized with a uniform quantizer
623 // with given stepsize. The closed form expression is:
624 // Dn(x) = 1 - 1/sqrt(2) * x / sinh(x/sqrt(2))
625 // where x = qpstep / sqrt(variance).
626 // Note the actual distortion is Dn * variance.
627 static const int dist_tab_q10[] = {
628 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 4, 5,
629 5, 6, 7, 7, 8, 9, 11, 12, 13, 15, 16, 17,
630 18, 21, 24, 26, 29, 31, 34, 36, 39, 44, 49, 54,
631 59, 64, 69, 73, 78, 88, 97, 106, 115, 124, 133, 142,
632 151, 167, 184, 200, 215, 231, 245, 260, 274, 301, 327, 351,
633 375, 397, 418, 439, 458, 495, 528, 559, 587, 613, 637, 659,
634 680, 717, 749, 777, 801, 823, 842, 859, 874, 899, 919, 936,
635 949, 960, 969, 977, 983, 994, 1001, 1006, 1010, 1013, 1015, 1017,
636 1018, 1020, 1022, 1022, 1023, 1023, 1023, 1024,
637 };
638 static const int xsq_iq_q10[] = {
639 0, 4, 8, 12, 16, 20, 24, 28, 32,
640 40, 48, 56, 64, 72, 80, 88, 96, 112,
641 128, 144, 160, 176, 192, 208, 224, 256, 288,
642 320, 352, 384, 416, 448, 480, 544, 608, 672,
643 736, 800, 864, 928, 992, 1120, 1248, 1376, 1504,
644 1632, 1760, 1888, 2016, 2272, 2528, 2784, 3040, 3296,
645 3552, 3808, 4064, 4576, 5088, 5600, 6112, 6624, 7136,
646 7648, 8160, 9184, 10208, 11232, 12256, 13280, 14304, 15328,
647 16352, 18400, 20448, 22496, 24544, 26592, 28640, 30688, 32736,
648 36832, 40928, 45024, 49120, 53216, 57312, 61408, 65504, 73696,
649 81888, 90080, 98272, 106464, 114656, 122848, 131040, 147424, 163808,
650 180192, 196576, 212960, 229344, 245728,
651 };
652 const int tmp = (xsq_q10 >> 2) + 8;
653 const int k = get_msb(tmp) - 3;
654 const int xq = (k << 3) + ((tmp >> k) & 0x7);
655 const int one_q10 = 1 << 10;
656 const int a_q10 = ((xsq_q10 - xsq_iq_q10[xq]) << 10) >> (2 + k);
657 const int b_q10 = one_q10 - a_q10;
658 *r_q10 = (rate_tab_q10[xq] * b_q10 + rate_tab_q10[xq + 1] * a_q10) >> 10;
659 *d_q10 = (dist_tab_q10[xq] * b_q10 + dist_tab_q10[xq + 1] * a_q10) >> 10;
660}
661
Yaowu Xuf883b422016-08-30 14:01:10 -0700662void av1_model_rd_from_var_lapndz(int64_t var, unsigned int n_log2,
663 unsigned int qstep, int *rate,
664 int64_t *dist) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700665 // This function models the rate and distortion for a Laplacian
666 // source with given variance when quantized with a uniform quantizer
667 // with given stepsize. The closed form expressions are in:
668 // Hang and Chen, "Source Model for transform video coder and its
669 // application - Part I: Fundamental Theory", IEEE Trans. Circ.
670 // Sys. for Video Tech., April 1997.
671 if (var == 0) {
672 *rate = 0;
673 *dist = 0;
674 } else {
675 int d_q10, r_q10;
676 static const uint32_t MAX_XSQ_Q10 = 245727;
677 const uint64_t xsq_q10_64 =
678 (((uint64_t)qstep * qstep << (n_log2 + 10)) + (var >> 1)) / var;
Yaowu Xuf883b422016-08-30 14:01:10 -0700679 const int xsq_q10 = (int)AOMMIN(xsq_q10_64, MAX_XSQ_Q10);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700680 model_rd_norm(xsq_q10, &r_q10, &d_q10);
Yaowu Xuf883b422016-08-30 14:01:10 -0700681 *rate = ROUND_POWER_OF_TWO(r_q10 << n_log2, 10 - AV1_PROB_COST_SHIFT);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700682 *dist = (var * (int64_t)d_q10 + 512) >> 10;
683 }
684}
685
686static void get_entropy_contexts_plane(
687 BLOCK_SIZE plane_bsize, TX_SIZE tx_size, const struct macroblockd_plane *pd,
688 ENTROPY_CONTEXT t_above[2 * MAX_MIB_SIZE],
689 ENTROPY_CONTEXT t_left[2 * MAX_MIB_SIZE]) {
Jingning Han9eef06d2016-12-05 12:39:34 -0800690 const int num_4x4_w = block_size_wide[plane_bsize] >> tx_size_wide_log2[0];
691 const int num_4x4_h = block_size_high[plane_bsize] >> tx_size_high_log2[0];
Yaowu Xuc27fc142016-08-22 16:08:15 -0700692 const ENTROPY_CONTEXT *const above = pd->above_context;
693 const ENTROPY_CONTEXT *const left = pd->left_context;
694
Angie Chiangfb42c7f2017-06-01 18:36:18 -0700695#if CONFIG_LV_MAP
696 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
697 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
698 return;
699#endif // CONFIG_LV_MAP
700
Yaowu Xuc27fc142016-08-22 16:08:15 -0700701 int i;
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800702
Timothy B. Terriberryfe67ed62017-04-26 16:53:47 -0700703#if CONFIG_CHROMA_2X2
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800704 switch (tx_size) {
Jingning Han39772c12016-12-01 12:47:05 -0800705 case TX_2X2:
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800706 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
707 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
708 break;
709 case TX_4X4:
710 for (i = 0; i < num_4x4_w; i += 2)
711 t_above[i] = !!*(const uint16_t *)&above[i];
712 for (i = 0; i < num_4x4_h; i += 2)
713 t_left[i] = !!*(const uint16_t *)&left[i];
714 break;
715 case TX_8X8:
716 for (i = 0; i < num_4x4_w; i += 4)
717 t_above[i] = !!*(const uint32_t *)&above[i];
718 for (i = 0; i < num_4x4_h; i += 4)
719 t_left[i] = !!*(const uint32_t *)&left[i];
720 break;
721 case TX_16X16:
722 for (i = 0; i < num_4x4_w; i += 8)
723 t_above[i] = !!*(const uint64_t *)&above[i];
724 for (i = 0; i < num_4x4_h; i += 8)
725 t_left[i] = !!*(const uint64_t *)&left[i];
726 break;
727 case TX_32X32:
728 for (i = 0; i < num_4x4_w; i += 16)
729 t_above[i] =
730 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
731 for (i = 0; i < num_4x4_h; i += 16)
732 t_left[i] =
733 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
734 break;
Urvang Joshi4c6d4362017-05-11 12:35:46 -0700735#if CONFIG_TX64X64
736 case TX_64X64:
737 for (i = 0; i < num_4x4_w; i += 32)
738 t_above[i] =
739 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8] |
740 *(const uint64_t *)&above[i + 16] |
741 *(const uint64_t *)&above[i + 24]);
742 for (i = 0; i < num_4x4_h; i += 32)
743 t_left[i] =
744 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8] |
745 *(const uint64_t *)&left[i + 16] |
746 *(const uint64_t *)&left[i + 24]);
747 break;
748#endif // CONFIG_TX64X64
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800749 case TX_4X8:
750 for (i = 0; i < num_4x4_w; i += 2)
751 t_above[i] = !!*(const uint16_t *)&above[i];
752 for (i = 0; i < num_4x4_h; i += 4)
753 t_left[i] = !!*(const uint32_t *)&left[i];
754 break;
755 case TX_8X4:
756 for (i = 0; i < num_4x4_w; i += 4)
757 t_above[i] = !!*(const uint32_t *)&above[i];
758 for (i = 0; i < num_4x4_h; i += 2)
759 t_left[i] = !!*(const uint16_t *)&left[i];
760 break;
761 case TX_8X16:
762 for (i = 0; i < num_4x4_w; i += 4)
763 t_above[i] = !!*(const uint32_t *)&above[i];
764 for (i = 0; i < num_4x4_h; i += 8)
765 t_left[i] = !!*(const uint64_t *)&left[i];
766 break;
767 case TX_16X8:
768 for (i = 0; i < num_4x4_w; i += 8)
769 t_above[i] = !!*(const uint64_t *)&above[i];
770 for (i = 0; i < num_4x4_h; i += 4)
771 t_left[i] = !!*(const uint32_t *)&left[i];
772 break;
773 case TX_16X32:
774 for (i = 0; i < num_4x4_w; i += 8)
775 t_above[i] = !!*(const uint64_t *)&above[i];
776 for (i = 0; i < num_4x4_h; i += 16)
777 t_left[i] =
778 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
779 break;
780 case TX_32X16:
781 for (i = 0; i < num_4x4_w; i += 16)
782 t_above[i] =
783 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
784 for (i = 0; i < num_4x4_h; i += 8)
785 t_left[i] = !!*(const uint64_t *)&left[i];
Jingning Han0f6a60a2017-01-20 09:25:40 -0800786 break;
Yue Chend6bdd462017-07-19 16:05:43 -0700787#if CONFIG_RECT_TX_EXT && (CONFIG_EXT_TX || CONFIG_VAR_TX)
Yue Chen56e226e2017-05-02 16:21:40 -0700788 case TX_4X16:
789 for (i = 0; i < num_4x4_w; i += 2)
790 t_above[i] = !!*(const uint16_t *)&above[i];
791 for (i = 0; i < num_4x4_h; i += 8)
792 t_left[i] = !!*(const uint64_t *)&left[i];
793 break;
794 case TX_16X4:
795 for (i = 0; i < num_4x4_w; i += 8)
796 t_above[i] = !!*(const uint64_t *)&above[i];
797 for (i = 0; i < num_4x4_h; i += 2)
798 t_left[i] = !!*(const uint16_t *)&left[i];
799 break;
800 case TX_8X32:
801 for (i = 0; i < num_4x4_w; i += 4)
802 t_above[i] = !!*(const uint32_t *)&above[i];
803 for (i = 0; i < num_4x4_h; i += 16)
804 t_left[i] =
805 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
806 break;
807 case TX_32X8:
808 for (i = 0; i < num_4x4_w; i += 16)
809 t_above[i] =
810 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
811 for (i = 0; i < num_4x4_h; i += 4)
812 t_left[i] = !!*(const uint32_t *)&left[i];
813 break;
Yue Chend6bdd462017-07-19 16:05:43 -0700814#endif
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800815
816 default: assert(0 && "Invalid transform size."); break;
817 }
818 return;
Timothy B. Terriberryfe67ed62017-04-26 16:53:47 -0700819#endif // CONFIG_CHROMA_2X2
Jingning Hanaa8a4a52016-12-13 17:30:48 -0800820
821 switch (tx_size) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700822 case TX_4X4:
823 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
824 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
825 break;
826 case TX_8X8:
827 for (i = 0; i < num_4x4_w; i += 2)
828 t_above[i] = !!*(const uint16_t *)&above[i];
829 for (i = 0; i < num_4x4_h; i += 2)
830 t_left[i] = !!*(const uint16_t *)&left[i];
831 break;
832 case TX_16X16:
833 for (i = 0; i < num_4x4_w; i += 4)
834 t_above[i] = !!*(const uint32_t *)&above[i];
835 for (i = 0; i < num_4x4_h; i += 4)
836 t_left[i] = !!*(const uint32_t *)&left[i];
837 break;
838 case TX_32X32:
839 for (i = 0; i < num_4x4_w; i += 8)
840 t_above[i] = !!*(const uint64_t *)&above[i];
841 for (i = 0; i < num_4x4_h; i += 8)
842 t_left[i] = !!*(const uint64_t *)&left[i];
843 break;
Debargha Mukherjee153e1f82016-11-17 09:59:14 -0800844#if CONFIG_TX64X64
845 case TX_64X64:
846 for (i = 0; i < num_4x4_w; i += 16)
847 t_above[i] =
848 !!(*(const uint64_t *)&above[i] | *(const uint64_t *)&above[i + 8]);
849 for (i = 0; i < num_4x4_h; i += 16)
Debargha Mukherjee932cf692016-11-18 08:14:10 -0800850 t_left[i] =
851 !!(*(const uint64_t *)&left[i] | *(const uint64_t *)&left[i + 8]);
Debargha Mukherjee153e1f82016-11-17 09:59:14 -0800852 break;
853#endif // CONFIG_TX64X64
Yaowu Xuc27fc142016-08-22 16:08:15 -0700854 case TX_4X8:
855 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
856 for (i = 0; i < num_4x4_h; i += 2)
857 t_left[i] = !!*(const uint16_t *)&left[i];
858 break;
859 case TX_8X4:
860 for (i = 0; i < num_4x4_w; i += 2)
861 t_above[i] = !!*(const uint16_t *)&above[i];
862 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
863 break;
864 case TX_8X16:
865 for (i = 0; i < num_4x4_w; i += 2)
866 t_above[i] = !!*(const uint16_t *)&above[i];
867 for (i = 0; i < num_4x4_h; i += 4)
868 t_left[i] = !!*(const uint32_t *)&left[i];
869 break;
870 case TX_16X8:
871 for (i = 0; i < num_4x4_w; i += 4)
872 t_above[i] = !!*(const uint32_t *)&above[i];
873 for (i = 0; i < num_4x4_h; i += 2)
874 t_left[i] = !!*(const uint16_t *)&left[i];
875 break;
876 case TX_16X32:
877 for (i = 0; i < num_4x4_w; i += 4)
878 t_above[i] = !!*(const uint32_t *)&above[i];
879 for (i = 0; i < num_4x4_h; i += 8)
880 t_left[i] = !!*(const uint64_t *)&left[i];
881 break;
882 case TX_32X16:
883 for (i = 0; i < num_4x4_w; i += 8)
884 t_above[i] = !!*(const uint64_t *)&above[i];
885 for (i = 0; i < num_4x4_h; i += 4)
886 t_left[i] = !!*(const uint32_t *)&left[i];
887 break;
Yue Chend6bdd462017-07-19 16:05:43 -0700888#if CONFIG_RECT_TX_EXT && (CONFIG_EXT_TX || CONFIG_VAR_TX)
Yue Chen56e226e2017-05-02 16:21:40 -0700889 case TX_4X16:
890 memcpy(t_above, above, sizeof(ENTROPY_CONTEXT) * num_4x4_w);
891 for (i = 0; i < num_4x4_h; i += 4)
892 t_left[i] = !!*(const uint32_t *)&left[i];
893 break;
894 case TX_16X4:
895 for (i = 0; i < num_4x4_w; i += 4)
896 t_above[i] = !!*(const uint32_t *)&above[i];
897 memcpy(t_left, left, sizeof(ENTROPY_CONTEXT) * num_4x4_h);
898 break;
899 case TX_8X32:
900 for (i = 0; i < num_4x4_w; i += 2)
901 t_above[i] = !!*(const uint16_t *)&above[i];
902 for (i = 0; i < num_4x4_h; i += 8)
903 t_left[i] = !!*(const uint64_t *)&left[i];
904 break;
905 case TX_32X8:
906 for (i = 0; i < num_4x4_w; i += 8)
907 t_above[i] = !!*(const uint64_t *)&above[i];
908 for (i = 0; i < num_4x4_h; i += 2)
909 t_left[i] = !!*(const uint16_t *)&left[i];
910 break;
Yue Chend6bdd462017-07-19 16:05:43 -0700911#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700912 default: assert(0 && "Invalid transform size."); break;
913 }
914}
915
Yaowu Xuf883b422016-08-30 14:01:10 -0700916void av1_get_entropy_contexts(BLOCK_SIZE bsize, TX_SIZE tx_size,
917 const struct macroblockd_plane *pd,
918 ENTROPY_CONTEXT t_above[2 * MAX_MIB_SIZE],
919 ENTROPY_CONTEXT t_left[2 * MAX_MIB_SIZE]) {
Timothy B. Terriberry81ec2612017-04-26 16:53:47 -0700920#if CONFIG_CHROMA_SUB8X8
Timothy B. Terriberry32b8d462017-05-22 12:02:56 -0700921 const BLOCK_SIZE plane_bsize =
922 AOMMAX(BLOCK_4X4, get_plane_block_size(bsize, pd));
923#else
Yaowu Xuc27fc142016-08-22 16:08:15 -0700924 const BLOCK_SIZE plane_bsize = get_plane_block_size(bsize, pd);
Timothy B. Terriberry32b8d462017-05-22 12:02:56 -0700925#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -0700926 get_entropy_contexts_plane(plane_bsize, tx_size, pd, t_above, t_left);
927}
928
Urvang Joshi52648442016-10-13 17:27:51 -0700929void av1_mv_pred(const AV1_COMP *cpi, MACROBLOCK *x, uint8_t *ref_y_buffer,
Yaowu Xuf883b422016-08-30 14:01:10 -0700930 int ref_y_stride, int ref_frame, BLOCK_SIZE block_size) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700931 int i;
932 int zero_seen = 0;
933 int best_index = 0;
934 int best_sad = INT_MAX;
935 int this_sad = INT_MAX;
936 int max_mv = 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700937 uint8_t *src_y_ptr = x->plane[0].src.buf;
938 uint8_t *ref_y_ptr;
Thomas Daede07438572017-05-10 11:22:33 -0700939 MV pred_mv[MAX_MV_REF_CANDIDATES + 1];
Debargha Mukherjeed80d63f2017-05-17 15:53:27 -0700940 int num_mv_refs = 0;
941
942 pred_mv[num_mv_refs++] = x->mbmi_ext->ref_mvs[ref_frame][0].as_mv;
943 if (x->mbmi_ext->ref_mvs[ref_frame][0].as_int !=
944 x->mbmi_ext->ref_mvs[ref_frame][1].as_int) {
945 pred_mv[num_mv_refs++] = x->mbmi_ext->ref_mvs[ref_frame][1].as_mv;
Thomas Daede07438572017-05-10 11:22:33 -0700946 }
Debargha Mukherjeed80d63f2017-05-17 15:53:27 -0700947 if (cpi->sf.adaptive_motion_search && block_size < x->max_partition_size)
948 pred_mv[num_mv_refs++] = x->pred_mv[ref_frame];
949
Yaowu Xuc27fc142016-08-22 16:08:15 -0700950 assert(num_mv_refs <= (int)(sizeof(pred_mv) / sizeof(pred_mv[0])));
Debargha Mukherjeed80d63f2017-05-17 15:53:27 -0700951
Yaowu Xuc27fc142016-08-22 16:08:15 -0700952 // Get the sad for each candidate reference mv.
953 for (i = 0; i < num_mv_refs; ++i) {
954 const MV *this_mv = &pred_mv[i];
955 int fp_row, fp_col;
Yaowu Xuc27fc142016-08-22 16:08:15 -0700956 fp_row = (this_mv->row + 3 + (this_mv->row >= 0)) >> 3;
957 fp_col = (this_mv->col + 3 + (this_mv->col >= 0)) >> 3;
Yaowu Xuf883b422016-08-30 14:01:10 -0700958 max_mv = AOMMAX(max_mv, AOMMAX(abs(this_mv->row), abs(this_mv->col)) >> 3);
Yaowu Xuc27fc142016-08-22 16:08:15 -0700959
960 if (fp_row == 0 && fp_col == 0 && zero_seen) continue;
961 zero_seen |= (fp_row == 0 && fp_col == 0);
962
963 ref_y_ptr = &ref_y_buffer[ref_y_stride * fp_row + fp_col];
964 // Find sad for current vector.
965 this_sad = cpi->fn_ptr[block_size].sdf(src_y_ptr, x->plane[0].src.stride,
966 ref_y_ptr, ref_y_stride);
967 // Note if it is the best so far.
968 if (this_sad < best_sad) {
969 best_sad = this_sad;
970 best_index = i;
971 }
972 }
973
974 // Note the index of the mv that worked best in the reference list.
975 x->mv_best_ref_index[ref_frame] = best_index;
976 x->max_mv_context[ref_frame] = max_mv;
977 x->pred_mv_sad[ref_frame] = best_sad;
978}
979
Yaowu Xuf883b422016-08-30 14:01:10 -0700980void av1_setup_pred_block(const MACROBLOCKD *xd,
981 struct buf_2d dst[MAX_MB_PLANE],
982 const YV12_BUFFER_CONFIG *src, int mi_row, int mi_col,
983 const struct scale_factors *scale,
984 const struct scale_factors *scale_uv) {
Yaowu Xuc27fc142016-08-22 16:08:15 -0700985 int i;
986
987 dst[0].buf = src->y_buffer;
988 dst[0].stride = src->y_stride;
989 dst[1].buf = src->u_buffer;
990 dst[2].buf = src->v_buffer;
991 dst[1].stride = dst[2].stride = src->uv_stride;
992
993 for (i = 0; i < MAX_MB_PLANE; ++i) {
Jingning Han91d9a792017-04-18 12:01:52 -0700994 setup_pred_plane(dst + i, xd->mi[0]->mbmi.sb_type, dst[i].buf,
Yaowu Xuc27fc142016-08-22 16:08:15 -0700995 i ? src->uv_crop_width : src->y_crop_width,
996 i ? src->uv_crop_height : src->y_crop_height,
997 dst[i].stride, mi_row, mi_col, i ? scale_uv : scale,
998 xd->plane[i].subsampling_x, xd->plane[i].subsampling_y);
999 }
1000}
1001
Yaowu Xuf883b422016-08-30 14:01:10 -07001002int av1_raster_block_offset(BLOCK_SIZE plane_bsize, int raster_block,
1003 int stride) {
Yaowu Xuc27fc142016-08-22 16:08:15 -07001004 const int bw = b_width_log2_lookup[plane_bsize];
1005 const int y = 4 * (raster_block >> bw);
1006 const int x = 4 * (raster_block & ((1 << bw) - 1));
1007 return y * stride + x;
1008}
1009
Yaowu Xuf883b422016-08-30 14:01:10 -07001010int16_t *av1_raster_block_offset_int16(BLOCK_SIZE plane_bsize, int raster_block,
1011 int16_t *base) {
Jingning Hanae5cfde2016-11-30 12:01:44 -08001012 const int stride = block_size_wide[plane_bsize];
Yaowu Xuf883b422016-08-30 14:01:10 -07001013 return base + av1_raster_block_offset(plane_bsize, raster_block, stride);
Yaowu Xuc27fc142016-08-22 16:08:15 -07001014}
1015
Yaowu Xuf883b422016-08-30 14:01:10 -07001016YV12_BUFFER_CONFIG *av1_get_scaled_ref_frame(const AV1_COMP *cpi,
1017 int ref_frame) {
1018 const AV1_COMMON *const cm = &cpi->common;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001019 const int scaled_idx = cpi->scaled_ref_idx[ref_frame - 1];
1020 const int ref_idx = get_ref_frame_buf_idx(cpi, ref_frame);
1021 return (scaled_idx != ref_idx && scaled_idx != INVALID_IDX)
1022 ? &cm->buffer_pool->frame_bufs[scaled_idx].buf
1023 : NULL;
1024}
1025
1026#if CONFIG_DUAL_FILTER
Yue Chenb23d00a2017-07-28 17:01:21 -07001027int av1_get_switchable_rate(const AV1_COMMON *const cm, MACROBLOCK *x,
1028 const MACROBLOCKD *xd) {
Angie Chiang75c22092016-10-25 12:19:16 -07001029 if (cm->interp_filter == SWITCHABLE) {
1030 const MB_MODE_INFO *const mbmi = &xd->mi[0]->mbmi;
1031 int inter_filter_cost = 0;
1032 int dir;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001033
Angie Chiang75c22092016-10-25 12:19:16 -07001034 for (dir = 0; dir < 2; ++dir) {
1035 if (has_subpel_mv_component(xd->mi[0], xd, dir) ||
1036 (mbmi->ref_frame[1] > INTRA_FRAME &&
1037 has_subpel_mv_component(xd->mi[0], xd, dir + 2))) {
1038 const int ctx = av1_get_pred_context_switchable_interp(xd, dir);
1039 inter_filter_cost +=
Yue Chenb23d00a2017-07-28 17:01:21 -07001040 x->switchable_interp_costs[ctx][mbmi->interp_filter[dir]];
Angie Chiang75c22092016-10-25 12:19:16 -07001041 }
Yaowu Xuc27fc142016-08-22 16:08:15 -07001042 }
Angie Chiang75c22092016-10-25 12:19:16 -07001043 return SWITCHABLE_INTERP_RATE_FACTOR * inter_filter_cost;
1044 } else {
1045 return 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001046 }
Yaowu Xuc27fc142016-08-22 16:08:15 -07001047}
1048#else
Yue Chenb23d00a2017-07-28 17:01:21 -07001049int av1_get_switchable_rate(const AV1_COMMON *const cm, MACROBLOCK *x,
1050 const MACROBLOCKD *xd) {
Angie Chiang75c22092016-10-25 12:19:16 -07001051 if (cm->interp_filter == SWITCHABLE) {
Angie Chiang1733f6b2017-01-05 09:52:20 -08001052 const MB_MODE_INFO *const mbmi = &xd->mi[0]->mbmi;
1053 const int ctx = av1_get_pred_context_switchable_interp(xd);
1054 return SWITCHABLE_INTERP_RATE_FACTOR *
Yue Chenb23d00a2017-07-28 17:01:21 -07001055 x->switchable_interp_costs[ctx][mbmi->interp_filter];
Angie Chiang75c22092016-10-25 12:19:16 -07001056 }
1057 return 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001058}
1059#endif
1060
Yaowu Xuf883b422016-08-30 14:01:10 -07001061void av1_set_rd_speed_thresholds(AV1_COMP *cpi) {
Yaowu Xuc27fc142016-08-22 16:08:15 -07001062 int i;
1063 RD_OPT *const rd = &cpi->rd;
1064 SPEED_FEATURES *const sf = &cpi->sf;
1065
1066 // Set baseline threshold values.
Thomas Daede6eca8352017-03-17 14:14:12 -07001067 for (i = 0; i < MAX_MODES; ++i) rd->thresh_mult[i] = cpi->oxcf.mode == 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001068
1069 if (sf->adaptive_rd_thresh) {
1070 rd->thresh_mult[THR_NEARESTMV] = 300;
1071#if CONFIG_EXT_REFS
1072 rd->thresh_mult[THR_NEARESTL2] = 300;
1073 rd->thresh_mult[THR_NEARESTL3] = 300;
1074 rd->thresh_mult[THR_NEARESTB] = 300;
Zoe Liue9b15e22017-07-19 15:53:01 -07001075 rd->thresh_mult[THR_NEARESTA2] = 300;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001076#endif // CONFIG_EXT_REFS
1077 rd->thresh_mult[THR_NEARESTA] = 300;
1078 rd->thresh_mult[THR_NEARESTG] = 300;
1079 } else {
1080 rd->thresh_mult[THR_NEARESTMV] = 0;
1081#if CONFIG_EXT_REFS
1082 rd->thresh_mult[THR_NEARESTL2] = 0;
1083 rd->thresh_mult[THR_NEARESTL3] = 0;
1084 rd->thresh_mult[THR_NEARESTB] = 0;
Zoe Liue9b15e22017-07-19 15:53:01 -07001085 rd->thresh_mult[THR_NEARESTA2] = 0;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001086#endif // CONFIG_EXT_REFS
1087 rd->thresh_mult[THR_NEARESTA] = 0;
1088 rd->thresh_mult[THR_NEARESTG] = 0;
1089 }
1090
1091 rd->thresh_mult[THR_DC] += 1000;
1092
1093 rd->thresh_mult[THR_NEWMV] += 1000;
1094#if CONFIG_EXT_REFS
1095 rd->thresh_mult[THR_NEWL2] += 1000;
1096 rd->thresh_mult[THR_NEWL3] += 1000;
1097 rd->thresh_mult[THR_NEWB] += 1000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001098 rd->thresh_mult[THR_NEWA2] = 1000;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001099#endif // CONFIG_EXT_REFS
1100 rd->thresh_mult[THR_NEWA] += 1000;
1101 rd->thresh_mult[THR_NEWG] += 1000;
1102
1103 rd->thresh_mult[THR_NEARMV] += 1000;
1104#if CONFIG_EXT_REFS
1105 rd->thresh_mult[THR_NEARL2] += 1000;
1106 rd->thresh_mult[THR_NEARL3] += 1000;
1107 rd->thresh_mult[THR_NEARB] += 1000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001108 rd->thresh_mult[THR_NEARA2] = 1000;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001109#endif // CONFIG_EXT_REFS
1110 rd->thresh_mult[THR_NEARA] += 1000;
1111 rd->thresh_mult[THR_NEARG] += 1000;
1112
Yaowu Xuc27fc142016-08-22 16:08:15 -07001113 rd->thresh_mult[THR_ZEROMV] += 2000;
1114#if CONFIG_EXT_REFS
1115 rd->thresh_mult[THR_ZEROL2] += 2000;
1116 rd->thresh_mult[THR_ZEROL3] += 2000;
1117 rd->thresh_mult[THR_ZEROB] += 2000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001118 rd->thresh_mult[THR_ZEROA2] = 2000;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001119#endif // CONFIG_EXT_REFS
1120 rd->thresh_mult[THR_ZEROG] += 2000;
1121 rd->thresh_mult[THR_ZEROA] += 2000;
1122
1123 rd->thresh_mult[THR_TM] += 1000;
1124
1125#if CONFIG_EXT_INTER
1126
Zoe Liu85b66462017-04-20 14:28:19 -07001127#if CONFIG_COMPOUND_SINGLEREF
1128 rd->thresh_mult[THR_SR_NEAREST_NEARMV] += 1200;
1129#if CONFIG_EXT_REFS
1130 rd->thresh_mult[THR_SR_NEAREST_NEARL2] += 1200;
1131 rd->thresh_mult[THR_SR_NEAREST_NEARL3] += 1200;
1132 rd->thresh_mult[THR_SR_NEAREST_NEARB] += 1200;
1133#endif // CONFIG_EXT_REFS
1134 rd->thresh_mult[THR_SR_NEAREST_NEARA] += 1200;
1135 rd->thresh_mult[THR_SR_NEAREST_NEARG] += 1200;
1136
1137 /*
1138 rd->thresh_mult[THR_SR_NEAREST_NEWMV] += 1200;
1139#if CONFIG_EXT_REFS
1140 rd->thresh_mult[THR_SR_NEAREST_NEWL2] += 1200;
1141 rd->thresh_mult[THR_SR_NEAREST_NEWL3] += 1200;
1142 rd->thresh_mult[THR_SR_NEAREST_NEWB] += 1200;
1143#endif // CONFIG_EXT_REFS
1144 rd->thresh_mult[THR_SR_NEAREST_NEWA] += 1200;
1145 rd->thresh_mult[THR_SR_NEAREST_NEWG] += 1200;*/
1146
1147 rd->thresh_mult[THR_SR_NEAR_NEWMV] += 1500;
1148#if CONFIG_EXT_REFS
1149 rd->thresh_mult[THR_SR_NEAR_NEWL2] += 1500;
1150 rd->thresh_mult[THR_SR_NEAR_NEWL3] += 1500;
1151 rd->thresh_mult[THR_SR_NEAR_NEWB] += 1500;
1152#endif // CONFIG_EXT_REFS
1153 rd->thresh_mult[THR_SR_NEAR_NEWA] += 1500;
1154 rd->thresh_mult[THR_SR_NEAR_NEWG] += 1500;
1155
1156 rd->thresh_mult[THR_SR_ZERO_NEWMV] += 2000;
1157#if CONFIG_EXT_REFS
1158 rd->thresh_mult[THR_SR_ZERO_NEWL2] += 2000;
1159 rd->thresh_mult[THR_SR_ZERO_NEWL3] += 2000;
1160 rd->thresh_mult[THR_SR_ZERO_NEWB] += 2000;
1161#endif // CONFIG_EXT_REFS
1162 rd->thresh_mult[THR_SR_ZERO_NEWA] += 2000;
1163 rd->thresh_mult[THR_SR_ZERO_NEWG] += 2000;
1164
1165 rd->thresh_mult[THR_SR_NEW_NEWMV] += 1700;
1166#if CONFIG_EXT_REFS
1167 rd->thresh_mult[THR_SR_NEW_NEWL2] += 1700;
1168 rd->thresh_mult[THR_SR_NEW_NEWL3] += 1700;
1169 rd->thresh_mult[THR_SR_NEW_NEWB] += 1700;
1170#endif // CONFIG_EXT_REFS
1171 rd->thresh_mult[THR_SR_NEW_NEWA] += 1700;
1172 rd->thresh_mult[THR_SR_NEW_NEWG] += 1700;
1173#endif // CONFIG_COMPOUND_SINGLEREF
1174
Yaowu Xuc27fc142016-08-22 16:08:15 -07001175 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLA] += 1000;
1176#if CONFIG_EXT_REFS
1177 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL2A] += 1000;
1178 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL3A] += 1000;
1179#endif // CONFIG_EXT_REFS
1180 rd->thresh_mult[THR_COMP_NEAREST_NEARESTGA] += 1000;
1181#if CONFIG_EXT_REFS
1182 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLB] += 1000;
1183 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL2B] += 1000;
1184 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL3B] += 1000;
1185 rd->thresh_mult[THR_COMP_NEAREST_NEARESTGB] += 1000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001186 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLA2] += 1000;
1187 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL2A2] += 1000;
1188 rd->thresh_mult[THR_COMP_NEAREST_NEARESTL3A2] += 1000;
1189 rd->thresh_mult[THR_COMP_NEAREST_NEARESTGA2] += 1000;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001190
1191#if CONFIG_EXT_COMP_REFS
1192 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLL2] += 1000;
Zoe Liufcf5fa22017-06-26 16:00:38 -07001193 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLL3] += 1000;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001194 rd->thresh_mult[THR_COMP_NEAREST_NEARESTLG] += 1000;
1195 rd->thresh_mult[THR_COMP_NEAREST_NEARESTBA] += 1000;
1196#endif // CONFIG_EXT_COMP_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001197#endif // CONFIG_EXT_REFS
1198
1199#else // CONFIG_EXT_INTER
1200
1201 rd->thresh_mult[THR_COMP_NEARESTLA] += 1000;
1202#if CONFIG_EXT_REFS
1203 rd->thresh_mult[THR_COMP_NEARESTL2A] += 1000;
1204 rd->thresh_mult[THR_COMP_NEARESTL3A] += 1000;
1205#endif // CONFIG_EXT_REFS
1206 rd->thresh_mult[THR_COMP_NEARESTGA] += 1000;
1207#if CONFIG_EXT_REFS
1208 rd->thresh_mult[THR_COMP_NEARESTLB] += 1000;
1209 rd->thresh_mult[THR_COMP_NEARESTL2B] += 1000;
1210 rd->thresh_mult[THR_COMP_NEARESTL3B] += 1000;
1211 rd->thresh_mult[THR_COMP_NEARESTGB] += 1000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001212 rd->thresh_mult[THR_COMP_NEARESTLA2] += 1000;
1213 rd->thresh_mult[THR_COMP_NEARESTL2A2] += 1000;
1214 rd->thresh_mult[THR_COMP_NEARESTL3A2] += 1000;
1215 rd->thresh_mult[THR_COMP_NEARESTGA2] += 1000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001216
Zoe Liuc082bbc2017-05-17 13:31:37 -07001217#if CONFIG_EXT_COMP_REFS
1218 rd->thresh_mult[THR_COMP_NEARESTLL2] += 1000;
Zoe Liufcf5fa22017-06-26 16:00:38 -07001219 rd->thresh_mult[THR_COMP_NEARESTLL3] += 1000;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001220 rd->thresh_mult[THR_COMP_NEARESTLG] += 1000;
1221 rd->thresh_mult[THR_COMP_NEARESTBA] += 1000;
1222#endif // CONFIG_EXT_COMP_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001223#endif // CONFIG_EXT_REFS
1224
1225#endif // CONFIG_EXT_INTER
1226
1227#if CONFIG_EXT_INTER
1228
Yaowu Xuc27fc142016-08-22 16:08:15 -07001229 rd->thresh_mult[THR_COMP_NEAR_NEARLA] += 1200;
1230 rd->thresh_mult[THR_COMP_NEAREST_NEWLA] += 1500;
1231 rd->thresh_mult[THR_COMP_NEW_NEARESTLA] += 1500;
1232 rd->thresh_mult[THR_COMP_NEAR_NEWLA] += 1700;
1233 rd->thresh_mult[THR_COMP_NEW_NEARLA] += 1700;
1234 rd->thresh_mult[THR_COMP_NEW_NEWLA] += 2000;
1235 rd->thresh_mult[THR_COMP_ZERO_ZEROLA] += 2500;
1236
1237#if CONFIG_EXT_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001238 rd->thresh_mult[THR_COMP_NEAR_NEARL2A] += 1200;
1239 rd->thresh_mult[THR_COMP_NEAREST_NEWL2A] += 1500;
1240 rd->thresh_mult[THR_COMP_NEW_NEARESTL2A] += 1500;
1241 rd->thresh_mult[THR_COMP_NEAR_NEWL2A] += 1700;
1242 rd->thresh_mult[THR_COMP_NEW_NEARL2A] += 1700;
1243 rd->thresh_mult[THR_COMP_NEW_NEWL2A] += 2000;
1244 rd->thresh_mult[THR_COMP_ZERO_ZEROL2A] += 2500;
1245
Yaowu Xuc27fc142016-08-22 16:08:15 -07001246 rd->thresh_mult[THR_COMP_NEAR_NEARL3A] += 1200;
1247 rd->thresh_mult[THR_COMP_NEAREST_NEWL3A] += 1500;
1248 rd->thresh_mult[THR_COMP_NEW_NEARESTL3A] += 1500;
1249 rd->thresh_mult[THR_COMP_NEAR_NEWL3A] += 1700;
1250 rd->thresh_mult[THR_COMP_NEW_NEARL3A] += 1700;
1251 rd->thresh_mult[THR_COMP_NEW_NEWL3A] += 2000;
1252 rd->thresh_mult[THR_COMP_ZERO_ZEROL3A] += 2500;
1253#endif // CONFIG_EXT_REFS
1254
Yaowu Xuc27fc142016-08-22 16:08:15 -07001255 rd->thresh_mult[THR_COMP_NEAR_NEARGA] += 1200;
1256 rd->thresh_mult[THR_COMP_NEAREST_NEWGA] += 1500;
1257 rd->thresh_mult[THR_COMP_NEW_NEARESTGA] += 1500;
1258 rd->thresh_mult[THR_COMP_NEAR_NEWGA] += 1700;
1259 rd->thresh_mult[THR_COMP_NEW_NEARGA] += 1700;
1260 rd->thresh_mult[THR_COMP_NEW_NEWGA] += 2000;
1261 rd->thresh_mult[THR_COMP_ZERO_ZEROGA] += 2500;
1262
1263#if CONFIG_EXT_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001264 rd->thresh_mult[THR_COMP_NEAR_NEARLB] += 1200;
1265 rd->thresh_mult[THR_COMP_NEAREST_NEWLB] += 1500;
1266 rd->thresh_mult[THR_COMP_NEW_NEARESTLB] += 1500;
1267 rd->thresh_mult[THR_COMP_NEAR_NEWLB] += 1700;
1268 rd->thresh_mult[THR_COMP_NEW_NEARLB] += 1700;
1269 rd->thresh_mult[THR_COMP_NEW_NEWLB] += 2000;
1270 rd->thresh_mult[THR_COMP_ZERO_ZEROLB] += 2500;
1271
Yaowu Xuc27fc142016-08-22 16:08:15 -07001272 rd->thresh_mult[THR_COMP_NEAR_NEARL2B] += 1200;
1273 rd->thresh_mult[THR_COMP_NEAREST_NEWL2B] += 1500;
1274 rd->thresh_mult[THR_COMP_NEW_NEARESTL2B] += 1500;
1275 rd->thresh_mult[THR_COMP_NEAR_NEWL2B] += 1700;
1276 rd->thresh_mult[THR_COMP_NEW_NEARL2B] += 1700;
1277 rd->thresh_mult[THR_COMP_NEW_NEWL2B] += 2000;
1278 rd->thresh_mult[THR_COMP_ZERO_ZEROL2B] += 2500;
1279
Yaowu Xuc27fc142016-08-22 16:08:15 -07001280 rd->thresh_mult[THR_COMP_NEAR_NEARL3B] += 1200;
1281 rd->thresh_mult[THR_COMP_NEAREST_NEWL3B] += 1500;
1282 rd->thresh_mult[THR_COMP_NEW_NEARESTL3B] += 1500;
1283 rd->thresh_mult[THR_COMP_NEAR_NEWL3B] += 1700;
1284 rd->thresh_mult[THR_COMP_NEW_NEARL3B] += 1700;
1285 rd->thresh_mult[THR_COMP_NEW_NEWL3B] += 2000;
1286 rd->thresh_mult[THR_COMP_ZERO_ZEROL3B] += 2500;
1287
Yaowu Xuc27fc142016-08-22 16:08:15 -07001288 rd->thresh_mult[THR_COMP_NEAR_NEARGB] += 1200;
1289 rd->thresh_mult[THR_COMP_NEAREST_NEWGB] += 1500;
1290 rd->thresh_mult[THR_COMP_NEW_NEARESTGB] += 1500;
1291 rd->thresh_mult[THR_COMP_NEAR_NEWGB] += 1700;
1292 rd->thresh_mult[THR_COMP_NEW_NEARGB] += 1700;
1293 rd->thresh_mult[THR_COMP_NEW_NEWGB] += 2000;
1294 rd->thresh_mult[THR_COMP_ZERO_ZEROGB] += 2500;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001295
Zoe Liue9b15e22017-07-19 15:53:01 -07001296 rd->thresh_mult[THR_COMP_NEAR_NEARLA2] += 1200;
1297 rd->thresh_mult[THR_COMP_NEAREST_NEWLA2] += 1500;
1298 rd->thresh_mult[THR_COMP_NEW_NEARESTLA2] += 1500;
1299 rd->thresh_mult[THR_COMP_NEAR_NEWLA2] += 1700;
1300 rd->thresh_mult[THR_COMP_NEW_NEARLA2] += 1700;
1301 rd->thresh_mult[THR_COMP_NEW_NEWLA2] += 2000;
1302 rd->thresh_mult[THR_COMP_ZERO_ZEROLA2] += 2500;
1303
1304 rd->thresh_mult[THR_COMP_NEAR_NEARL2A2] += 1200;
1305 rd->thresh_mult[THR_COMP_NEAREST_NEWL2A2] += 1500;
1306 rd->thresh_mult[THR_COMP_NEW_NEARESTL2A2] += 1500;
1307 rd->thresh_mult[THR_COMP_NEAR_NEWL2A2] += 1700;
1308 rd->thresh_mult[THR_COMP_NEW_NEARL2A2] += 1700;
1309 rd->thresh_mult[THR_COMP_NEW_NEWL2A2] += 2000;
1310 rd->thresh_mult[THR_COMP_ZERO_ZEROL2A2] += 2500;
1311
1312 rd->thresh_mult[THR_COMP_NEAR_NEARL3A2] += 1200;
1313 rd->thresh_mult[THR_COMP_NEAREST_NEWL3A2] += 1500;
1314 rd->thresh_mult[THR_COMP_NEW_NEARESTL3A2] += 1500;
1315 rd->thresh_mult[THR_COMP_NEAR_NEWL3A2] += 1700;
1316 rd->thresh_mult[THR_COMP_NEW_NEARL3A2] += 1700;
1317 rd->thresh_mult[THR_COMP_NEW_NEWL3A2] += 2000;
1318 rd->thresh_mult[THR_COMP_ZERO_ZEROL3A2] += 2500;
1319
1320 rd->thresh_mult[THR_COMP_NEAR_NEARGA2] += 1200;
1321 rd->thresh_mult[THR_COMP_NEAREST_NEWGA2] += 1500;
1322 rd->thresh_mult[THR_COMP_NEW_NEARESTGA2] += 1500;
1323 rd->thresh_mult[THR_COMP_NEAR_NEWGA2] += 1700;
1324 rd->thresh_mult[THR_COMP_NEW_NEARGA2] += 1700;
1325 rd->thresh_mult[THR_COMP_NEW_NEWGA2] += 2000;
1326 rd->thresh_mult[THR_COMP_ZERO_ZEROGA2] += 2500;
Zoe Liue9b15e22017-07-19 15:53:01 -07001327
Zoe Liuc082bbc2017-05-17 13:31:37 -07001328#if CONFIG_EXT_COMP_REFS
Zoe Liuc082bbc2017-05-17 13:31:37 -07001329 rd->thresh_mult[THR_COMP_NEAR_NEARLL2] += 1200;
1330 rd->thresh_mult[THR_COMP_NEAREST_NEWLL2] += 1500;
1331 rd->thresh_mult[THR_COMP_NEW_NEARESTLL2] += 1500;
1332 rd->thresh_mult[THR_COMP_NEAR_NEWLL2] += 1700;
1333 rd->thresh_mult[THR_COMP_NEW_NEARLL2] += 1700;
1334 rd->thresh_mult[THR_COMP_NEW_NEWLL2] += 2000;
1335 rd->thresh_mult[THR_COMP_ZERO_ZEROLL2] += 2500;
1336
Zoe Liufcf5fa22017-06-26 16:00:38 -07001337 rd->thresh_mult[THR_COMP_NEAR_NEARLL3] += 1200;
1338 rd->thresh_mult[THR_COMP_NEAREST_NEWLL3] += 1500;
1339 rd->thresh_mult[THR_COMP_NEW_NEARESTLL3] += 1500;
1340 rd->thresh_mult[THR_COMP_NEAR_NEWLL3] += 1700;
1341 rd->thresh_mult[THR_COMP_NEW_NEARLL3] += 1700;
1342 rd->thresh_mult[THR_COMP_NEW_NEWLL3] += 2000;
1343 rd->thresh_mult[THR_COMP_ZERO_ZEROLL3] += 2500;
1344
Zoe Liuc082bbc2017-05-17 13:31:37 -07001345 rd->thresh_mult[THR_COMP_NEAR_NEARLG] += 1200;
1346 rd->thresh_mult[THR_COMP_NEAREST_NEWLG] += 1500;
1347 rd->thresh_mult[THR_COMP_NEW_NEARESTLG] += 1500;
1348 rd->thresh_mult[THR_COMP_NEAR_NEWLG] += 1700;
1349 rd->thresh_mult[THR_COMP_NEW_NEARLG] += 1700;
1350 rd->thresh_mult[THR_COMP_NEW_NEWLG] += 2000;
1351 rd->thresh_mult[THR_COMP_ZERO_ZEROLG] += 2500;
1352
Zoe Liuc082bbc2017-05-17 13:31:37 -07001353 rd->thresh_mult[THR_COMP_NEAR_NEARBA] += 1200;
1354 rd->thresh_mult[THR_COMP_NEAREST_NEWBA] += 1500;
1355 rd->thresh_mult[THR_COMP_NEW_NEARESTBA] += 1500;
1356 rd->thresh_mult[THR_COMP_NEAR_NEWBA] += 1700;
1357 rd->thresh_mult[THR_COMP_NEW_NEARBA] += 1700;
1358 rd->thresh_mult[THR_COMP_NEW_NEWBA] += 2000;
1359 rd->thresh_mult[THR_COMP_ZERO_ZEROBA] += 2500;
1360#endif // CONFIG_EXT_COMP_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001361#endif // CONFIG_EXT_REFS
1362
1363#else // CONFIG_EXT_INTER
1364
1365 rd->thresh_mult[THR_COMP_NEARLA] += 1500;
1366 rd->thresh_mult[THR_COMP_NEWLA] += 2000;
1367#if CONFIG_EXT_REFS
1368 rd->thresh_mult[THR_COMP_NEARL2A] += 1500;
1369 rd->thresh_mult[THR_COMP_NEWL2A] += 2000;
1370 rd->thresh_mult[THR_COMP_NEARL3A] += 1500;
1371 rd->thresh_mult[THR_COMP_NEWL3A] += 2000;
1372#endif // CONFIG_EXT_REFS
1373 rd->thresh_mult[THR_COMP_NEARGA] += 1500;
1374 rd->thresh_mult[THR_COMP_NEWGA] += 2000;
1375
1376#if CONFIG_EXT_REFS
1377 rd->thresh_mult[THR_COMP_NEARLB] += 1500;
1378 rd->thresh_mult[THR_COMP_NEWLB] += 2000;
1379 rd->thresh_mult[THR_COMP_NEARL2B] += 1500;
1380 rd->thresh_mult[THR_COMP_NEWL2B] += 2000;
1381 rd->thresh_mult[THR_COMP_NEARL3B] += 1500;
1382 rd->thresh_mult[THR_COMP_NEWL3B] += 2000;
1383 rd->thresh_mult[THR_COMP_NEARGB] += 1500;
1384 rd->thresh_mult[THR_COMP_NEWGB] += 2000;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001385
Zoe Liue9b15e22017-07-19 15:53:01 -07001386 rd->thresh_mult[THR_COMP_NEARLA2] += 1500;
1387 rd->thresh_mult[THR_COMP_NEWLA2] += 2000;
1388 rd->thresh_mult[THR_COMP_NEARL2A2] += 1500;
1389 rd->thresh_mult[THR_COMP_NEWL2A2] += 2000;
1390 rd->thresh_mult[THR_COMP_NEARL3A2] += 1500;
1391 rd->thresh_mult[THR_COMP_NEWL3A2] += 2000;
1392 rd->thresh_mult[THR_COMP_NEARGA2] += 1500;
1393 rd->thresh_mult[THR_COMP_NEWGA2] += 2000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001394
Zoe Liuc082bbc2017-05-17 13:31:37 -07001395#if CONFIG_EXT_COMP_REFS
1396 rd->thresh_mult[THR_COMP_NEARLL2] += 1500;
1397 rd->thresh_mult[THR_COMP_NEWLL2] += 2000;
Zoe Liufcf5fa22017-06-26 16:00:38 -07001398 rd->thresh_mult[THR_COMP_NEARLL3] += 1500;
1399 rd->thresh_mult[THR_COMP_NEWLL3] += 2000;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001400 rd->thresh_mult[THR_COMP_NEARLG] += 1500;
1401 rd->thresh_mult[THR_COMP_NEWLG] += 2000;
1402 rd->thresh_mult[THR_COMP_NEARBA] += 1500;
1403 rd->thresh_mult[THR_COMP_NEWBA] += 2000;
1404#endif // CONFIG_EXT_COMP_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001405#endif // CONFIG_EXT_REFS
1406
1407 rd->thresh_mult[THR_COMP_ZEROLA] += 2500;
1408#if CONFIG_EXT_REFS
1409 rd->thresh_mult[THR_COMP_ZEROL2A] += 2500;
1410 rd->thresh_mult[THR_COMP_ZEROL3A] += 2500;
1411#endif // CONFIG_EXT_REFS
1412 rd->thresh_mult[THR_COMP_ZEROGA] += 2500;
1413
1414#if CONFIG_EXT_REFS
1415 rd->thresh_mult[THR_COMP_ZEROLB] += 2500;
1416 rd->thresh_mult[THR_COMP_ZEROL2B] += 2500;
1417 rd->thresh_mult[THR_COMP_ZEROL3B] += 2500;
1418 rd->thresh_mult[THR_COMP_ZEROGB] += 2500;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001419
Zoe Liue9b15e22017-07-19 15:53:01 -07001420 rd->thresh_mult[THR_COMP_ZEROLA2] += 2500;
1421 rd->thresh_mult[THR_COMP_ZEROL2A2] += 2500;
1422 rd->thresh_mult[THR_COMP_ZEROL3A2] += 2500;
1423 rd->thresh_mult[THR_COMP_ZEROGA2] += 2500;
Zoe Liue9b15e22017-07-19 15:53:01 -07001424
Zoe Liuc082bbc2017-05-17 13:31:37 -07001425#if CONFIG_EXT_COMP_REFS
1426 rd->thresh_mult[THR_COMP_ZEROLL2] += 2500;
Zoe Liufcf5fa22017-06-26 16:00:38 -07001427 rd->thresh_mult[THR_COMP_ZEROLL3] += 2500;
Zoe Liuc082bbc2017-05-17 13:31:37 -07001428 rd->thresh_mult[THR_COMP_ZEROLG] += 2500;
1429 rd->thresh_mult[THR_COMP_ZEROBA] += 2500;
1430#endif // CONFIG_EXT_COMP_REFS
Yaowu Xuc27fc142016-08-22 16:08:15 -07001431#endif // CONFIG_EXT_REFS
1432
1433#endif // CONFIG_EXT_INTER
1434
1435 rd->thresh_mult[THR_H_PRED] += 2000;
1436 rd->thresh_mult[THR_V_PRED] += 2000;
1437 rd->thresh_mult[THR_D135_PRED] += 2500;
1438 rd->thresh_mult[THR_D207_PRED] += 2500;
1439 rd->thresh_mult[THR_D153_PRED] += 2500;
1440 rd->thresh_mult[THR_D63_PRED] += 2500;
1441 rd->thresh_mult[THR_D117_PRED] += 2500;
1442 rd->thresh_mult[THR_D45_PRED] += 2500;
1443
1444#if CONFIG_EXT_INTER
1445 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROL] += 1500;
1446 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTL] += 1500;
1447 rd->thresh_mult[THR_COMP_INTERINTRA_NEARL] += 1500;
1448 rd->thresh_mult[THR_COMP_INTERINTRA_NEWL] += 2000;
1449
1450#if CONFIG_EXT_REFS
1451 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROL2] += 1500;
1452 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTL2] += 1500;
1453 rd->thresh_mult[THR_COMP_INTERINTRA_NEARL2] += 1500;
1454 rd->thresh_mult[THR_COMP_INTERINTRA_NEWL2] += 2000;
1455
1456 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROL3] += 1500;
1457 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTL3] += 1500;
1458 rd->thresh_mult[THR_COMP_INTERINTRA_NEARL3] += 1500;
1459 rd->thresh_mult[THR_COMP_INTERINTRA_NEWL3] += 2000;
1460#endif // CONFIG_EXT_REFS
1461
1462 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROG] += 1500;
1463 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTG] += 1500;
1464 rd->thresh_mult[THR_COMP_INTERINTRA_NEARG] += 1500;
1465 rd->thresh_mult[THR_COMP_INTERINTRA_NEWG] += 2000;
1466
1467#if CONFIG_EXT_REFS
1468 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROB] += 1500;
1469 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTB] += 1500;
1470 rd->thresh_mult[THR_COMP_INTERINTRA_NEARB] += 1500;
1471 rd->thresh_mult[THR_COMP_INTERINTRA_NEWB] += 2000;
Zoe Liue9b15e22017-07-19 15:53:01 -07001472
Zoe Liue9b15e22017-07-19 15:53:01 -07001473 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROA2] += 1500;
1474 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTA2] += 1500;
1475 rd->thresh_mult[THR_COMP_INTERINTRA_NEARA2] += 1500;
1476 rd->thresh_mult[THR_COMP_INTERINTRA_NEWA2] += 2000;
Yaowu Xuc27fc142016-08-22 16:08:15 -07001477#endif // CONFIG_EXT_REFS
1478
1479 rd->thresh_mult[THR_COMP_INTERINTRA_ZEROA] += 1500;
1480 rd->thresh_mult[THR_COMP_INTERINTRA_NEARESTA] += 1500;
1481 rd->thresh_mult[THR_COMP_INTERINTRA_NEARA] += 1500;
1482 rd->thresh_mult[THR_COMP_INTERINTRA_NEWA] += 2000;
1483#endif // CONFIG_EXT_INTER
1484}
1485
Yaowu Xuf883b422016-08-30 14:01:10 -07001486void av1_set_rd_speed_thresholds_sub8x8(AV1_COMP *cpi) {
Thomas Daede6eca8352017-03-17 14:14:12 -07001487 static const int thresh_mult[MAX_REFS] = {
Yaowu Xuc27fc142016-08-22 16:08:15 -07001488#if CONFIG_EXT_REFS
Thomas Daede6eca8352017-03-17 14:14:12 -07001489 2500,
1490 2500,
1491 2500,
1492 2500,
Zoe Liue9b15e22017-07-19 15:53:01 -07001493 2500,
Thomas Daede6eca8352017-03-17 14:14:12 -07001494 2500,
1495 2500,
1496 4500,
1497 4500,
1498 4500,
1499 4500,
1500 4500,
1501 4500,
1502 4500,
1503 4500,
Zoe Liue9b15e22017-07-19 15:53:01 -07001504 4500,
1505 4500,
1506 4500,
1507 4500,
Thomas Daede6eca8352017-03-17 14:14:12 -07001508 2500
Zoe Liue9b15e22017-07-19 15:53:01 -07001509#else // !CONFIG_EXT_REFS
Thomas Daede6eca8352017-03-17 14:14:12 -07001510 2500,
1511 2500,
1512 2500,
1513 4500,
1514 4500,
1515 2500
Yaowu Xuc27fc142016-08-22 16:08:15 -07001516#endif // CONFIG_EXT_REFS
1517 };
1518 RD_OPT *const rd = &cpi->rd;
Thomas Daede6eca8352017-03-17 14:14:12 -07001519 memcpy(rd->thresh_mult_sub8x8, thresh_mult, sizeof(thresh_mult));
Yaowu Xuc27fc142016-08-22 16:08:15 -07001520}
1521
Yaowu Xuf883b422016-08-30 14:01:10 -07001522void av1_update_rd_thresh_fact(const AV1_COMMON *const cm,
1523 int (*factor_buf)[MAX_MODES], int rd_thresh,
1524 int bsize, int best_mode_index) {
Yaowu Xuc27fc142016-08-22 16:08:15 -07001525 if (rd_thresh > 0) {
Jingning Han9104bed2016-12-14 09:38:00 -08001526#if CONFIG_CB4X4
1527 const int top_mode = MAX_MODES;
1528#else
Yaowu Xuc27fc142016-08-22 16:08:15 -07001529 const int top_mode = bsize < BLOCK_8X8 ? MAX_REFS : MAX_MODES;
Jingning Han9104bed2016-12-14 09:38:00 -08001530#endif
Yaowu Xuc27fc142016-08-22 16:08:15 -07001531 int mode;
1532 for (mode = 0; mode < top_mode; ++mode) {
Yaowu Xuf883b422016-08-30 14:01:10 -07001533 const BLOCK_SIZE min_size = AOMMAX(bsize - 1, BLOCK_4X4);
Urvang Joshicb586f32016-09-20 11:36:33 -07001534 const BLOCK_SIZE max_size = AOMMIN(bsize + 2, (int)cm->sb_size);
Yaowu Xuc27fc142016-08-22 16:08:15 -07001535 BLOCK_SIZE bs;
1536 for (bs = min_size; bs <= max_size; ++bs) {
1537 int *const fact = &factor_buf[bs][mode];
1538 if (mode == best_mode_index) {
1539 *fact -= (*fact >> 4);
1540 } else {
Yaowu Xuf883b422016-08-30 14:01:10 -07001541 *fact = AOMMIN(*fact + RD_THRESH_INC, rd_thresh * RD_THRESH_MAX_FACT);
Yaowu Xuc27fc142016-08-22 16:08:15 -07001542 }
1543 }
1544 }
1545 }
1546}
1547
Yaowu Xuf883b422016-08-30 14:01:10 -07001548int av1_get_intra_cost_penalty(int qindex, int qdelta,
1549 aom_bit_depth_t bit_depth) {
1550 const int q = av1_dc_quant(qindex, qdelta, bit_depth);
Sebastien Alaiwan71e87842017-04-12 16:03:28 +02001551#if CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -07001552 switch (bit_depth) {
Yaowu Xuf883b422016-08-30 14:01:10 -07001553 case AOM_BITS_8: return 20 * q;
1554 case AOM_BITS_10: return 5 * q;
1555 case AOM_BITS_12: return ROUND_POWER_OF_TWO(5 * q, 2);
Yaowu Xuc27fc142016-08-22 16:08:15 -07001556 default:
Yaowu Xuf883b422016-08-30 14:01:10 -07001557 assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12");
Yaowu Xuc27fc142016-08-22 16:08:15 -07001558 return -1;
1559 }
1560#else
1561 return 20 * q;
Sebastien Alaiwan71e87842017-04-12 16:03:28 +02001562#endif // CONFIG_HIGHBITDEPTH
Yaowu Xuc27fc142016-08-22 16:08:15 -07001563}